| /xnu-8792.61.2/osfmk/arm64/ |
| H A D | start.s | 51 msr VBAR_EL1, x0
62 msr TCR_EL1, x1
72 msr TTBR1_EL1, x0
84 msr SPSel, #0 // Back to SP0
87 msr SCTLR_EL1, x0
130 msr OSLAR_EL1, xzr
131 msr DAIFSet, #(DAIFSC_ALL) // Disable all interrupts
137 msr VBAR_EL1, x0
191 msr TPIDR_EL1, x13
319 msr TPIDR_EL0, x0
[all …]
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| H A D | pinst.s | 62 msr TTBR1_EL1, x0
66 msr VBAR_EL1, x0
70 msr TCR_EL1, x0
75 msr SCTLR_EL1, x0
114 msr SPSel, #1
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| H A D | machine_routines_asm.s | 141 msr CPU_CFG, x13
202 msr FPSR, x1 // Write FPCR
203 msr FPCR, x2 // Write FPSR
232 msr MDSCR_EL1, x2
269 msr TTBR1_EL1, x0
287 msr TTBR0_EL1, x0
308 msr ACTLR_EL1, x0
321 msr VBAR_EL1, x0
347 msr TCR_EL1, x0
384 msr DAIFSet, #(DAIFSC_IRQF | DAIFSC_FIQF) // Disable IRQ
[all …]
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| H A D | cswitch.s | 131 msr SSBS, x$1
137 msr DIT, x$1
142 msr UAO, x$1
178 msr TPIDR_EL1, $0 // Write new thread pointer to TPIDR_EL1
183 msr TPIDR_EL0, $2
186 msr TPIDRRO_EL0, $1
190 msr CONTEXTIDR_EL1, $1 // CONTEXTIDR_EL1 (top 32-bits are RES0).
354 msr DAIFSet, #(DAIFSC_FIQF | DAIFSC_IRQF) // Disable interrupts
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| H A D | locore.s | 80 msr TTBR0_EL1, x18
96 msr TCR_EL1, x18
297 msr SPSel, #0 // Switch to SP0
393 msr SP_EL0, x0 // Copy the user PCB pointer to SP0
395 msr SPSel, #0 // Switch to SP0
489 msr ELR_EL1, lr // Return to caller
808 msr DAIFSet, #DAIFSC_ALL // Disable exceptions
866 msr DAIFSet, #DAIFSC_ALL // Disable exceptions
930 msr CPACR_EL1, x0
948 msr TPIDR_EL0, x0
[all …]
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| H A D | machine_routines_asm.h | 57 msr SPSel, #1
92 msr SPSel, #0
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| H A D | exception_asm.h | 211 msr SPSel, #1
213 msr SPSel, x19
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| H A D | proc_reg.h | 2322 msr $0, $2
2580 msr $0, $2
2592 msr $0, $2
2606 msr $0, $3
2622 msr \sreg, \scr1
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| H A D | caches_asm.s | 95 msr CSSELR_EL1, $0 // Select appropriate cache
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| /xnu-8792.61.2/osfmk/i386/ |
| H A D | proc_reg.h | 415 extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
416 extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
449 #define rdmsr(msr, lo, hi) \ argument
450 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
452 #define wrmsr(msr, lo, hi) \ argument
453 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
501 rdmsr64(uint32_t msr) in rdmsr64() argument
504 rdmsr(msr, lo, hi); in rdmsr64()
509 wrmsr64(uint32_t msr, uint64_t val) in wrmsr64() argument
511 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL)); in wrmsr64()
[all …]
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| H A D | cpuid.c | 985 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
986 if (0 == msr) { in cpuid_set_info()
988 msr = (1 << 16) | 1; in cpuid_set_info()
990 info_p->core_count = bitfield32((uint32_t)msr, 19, 16); in cpuid_set_info()
991 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
996 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
997 if (0 == msr) { in cpuid_set_info()
999 msr = (1 << 16) | 1; in cpuid_set_info()
1001 info_p->core_count = bitfield32((uint32_t)msr, 31, 16); in cpuid_set_info()
1002 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
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| /xnu-8792.61.2/osfmk/i386/vmx/ |
| H A D | vmx_cpu.h | 72 #define VMX_CAP(msr, shift, mask) (rdmsr64(msr) & ((mask) << (shift))) argument
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| H A D | vmx_cpu.c | 150 #define rdmsr_mask(msr, mask) (uint32_t)(rdmsr64(msr) & (mask)) in vmx_cpu_init() argument
409 #define CHK(msr, shift, mask) if (!VMX_CAP(msr, shift, mask)) return FALSE; in vmx_hv_support() argument
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| /xnu-8792.61.2/pexpert/pexpert/arm64/ |
| H A D | apple_arm64_regs.h | 136 msr $2, $1
141 msr $3, $1
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| /xnu-8792.61.2/osfmk/kdp/ml/i386/ |
| H A D | kdp_x86_common.c | 391 uint32_t msr = rq->address; in kdp_machine_msr64_read() local
397 *value = rdmsr64(msr); in kdp_machine_msr64_read()
405 uint32_t msr = rq->address; in kdp_machine_msr64_write() local
411 wrmsr64(msr, *value); in kdp_machine_msr64_write()
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