Lines Matching refs:msr

51 	msr		VBAR_EL1, x0
62 	msr		TCR_EL1, x1
72 	msr		TTBR1_EL1, x0
84 	msr		SPSel, #0									// Back to SP0
87 	msr		SCTLR_EL1, x0
130 	msr		OSLAR_EL1, xzr
131 	msr		DAIFSet, #(DAIFSC_ALL)				// Disable all interrupts
137 	msr     VBAR_EL1, x0
191 	msr		TPIDR_EL1, x13
319 	msr		TPIDR_EL0, x0
322 	msr		TPIDRRO_EL0, xzr
335 	msr		SPSel, #1
341 	msr		SPSel, #0
460 	msr		OSLAR_EL1, xzr
461 	msr		DAIFSet, #(DAIFSC_ALL)				// Disable all interrupts
482 	msr		TPIDRRO_EL0, xzr
483 	msr		TPIDR_EL0, xzr
495 	msr		SPSel, #1
505 	msr		SPSel, #0							// Set SP_EL0 to interrupt stack
683 	msr		MAIR_EL1, x0
761 	msr		CPACR_EL1, x0
765 	msr		TPIDR_EL1, xzr						// Set thread register
771 	msr		MDSCR_EL1, x12
785 	msr		CPU_OVRD, x9