1<?xml version='1.0' encoding='utf-8'?> 2<!DOCTYPE register_page SYSTEM "registers.dtd"> 3<!-- Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. --> 4<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --> 5<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?> 6 7 8 9 10 11 12<register_page> 13 <registers> 14 <register execution_state="AArch64" is_register="True" is_internal="True" is_banked="False" is_optional="False" is_stub_entry="False"> 15 <reg_short_name>ESR_EL1</reg_short_name> 16 <reg_long_name>Exception Syndrome Register (EL1)</reg_long_name> 17 18 19 <reg_reset_value></reg_reset_value> 20 <reg_mappings> 21 <reg_mapping> 22 23 <mapped_name filename="AArch32-dfsr.xml">DFSR</mapped_name> 24 <mapped_type>Architectural</mapped_type> 25 <mapped_execution_state>AArch32</mapped_execution_state> 26 <mapped_from_startbit>31</mapped_from_startbit> 27 <mapped_from_endbit>0</mapped_from_endbit> 28 29 <mapped_to_startbit>31</mapped_to_startbit> 30 <mapped_to_endbit>0</mapped_to_endbit> 31 32 </reg_mapping> 33 </reg_mappings> 34 <reg_purpose> 35 36 37 <purpose_text> 38 <para>Holds syndrome information for an exception taken to EL1.</para> 39 </purpose_text> 40 41 </reg_purpose> 42 <reg_groups> 43 <reg_group>Exception and fault handling registers</reg_group> 44 </reg_groups> 45 <reg_usage_constraints> 46 47 48 </reg_usage_constraints> 49 <reg_configuration> 50 51 52 </reg_configuration> 53 <reg_attributes> 54 <attributes_text> 55 <para>ESR_EL1 is a 64-bit register.</para> 56 </attributes_text> 57 </reg_attributes> 58 <reg_fieldsets> 59 60 61 62 63 64 65 66 67 68 69 70 71 <fields length="64"> 72 <text_before_fields> 73 74 <para>ESR_EL1 is made <arm-defined-word>UNKNOWN</arm-defined-word> as a result of an exception return from EL1.</para> 75<para>When an <arm-defined-word>UNPREDICTABLE</arm-defined-word> instruction is treated as <arm-defined-word>UNDEFINED</arm-defined-word>, and the exception is taken to EL1, the value of ESR_EL1 is <arm-defined-word>UNKNOWN</arm-defined-word>. The value written to ESR_EL1 must be consistent with a value that could be created as a result of an exception from the same Exception level that generated the exception as a result of a situation that is not <arm-defined-word>UNPREDICTABLE</arm-defined-word> at that Exception level, in order to avoid the possibility of a privilege violation.</para> 76 77 </text_before_fields> 78 79 <field 80 id="0_63_32" 81 is_variable_length="False" 82 has_partial_fieldset="False" 83 is_linked_to_partial_fieldset="False" 84 is_access_restriction_possible="False" 85 is_constant_value="False" 86 rwtype="RES0" 87 > 88 <field_name>0</field_name> 89 <field_msb>63</field_msb> 90 <field_lsb>32</field_lsb> 91 <field_description order="before"> 92 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 93 </field_description> 94 <field_values> 95 </field_values> 96 </field> 97 <field 98 id="EC_31_26" 99 is_variable_length="False" 100 has_partial_fieldset="False" 101 is_linked_to_partial_fieldset="True" 102 is_access_restriction_possible="False" 103 is_constant_value="False" 104 > 105 <field_name>EC</field_name> 106 <field_msb>31</field_msb> 107 <field_lsb>26</field_lsb> 108 <field_description order="before"> 109 110 <para>Exception Class. Indicates the reason for the exception that this register holds information about.</para> 111<para>For each EC value, the table references a subsection that gives information about:</para> 112<list type="unordered"> 113<listitem><content>The cause of the exception, for example the configuration required to enable the trap.</content> 114</listitem><listitem><content>The encoding of the associated ISS.</content> 115</listitem></list> 116<para>Possible values of the EC field are:</para> 117 118 </field_description> 119 <field_values> 120 121 122 <field_value_instance> 123 <field_value>0b000000</field_value> 124 <field_value_description> 125 <para>Unknown reason.</para> 126</field_value_description> 127 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exceptions with an unknown reason"/> 128 </field_value_instance> 129 <field_value_instance> 130 <field_value>0b000001</field_value> 131 <field_value_description> 132 <para>Trapped WFI or WFE instruction execution.</para> 133<para>Conditional WFE and WFI instructions that fail their condition code check do not cause an exception.</para> 134</field_value_description> 135 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a WFI or WFE instruction"/> 136 </field_value_instance> 137 <field_value_instance> 138 <field_value>0b000011</field_value> 139 <field_value_description> 140 <para>Trapped MCR or MRC access with (coproc==<binarynumber>0b1111</binarynumber>) that is not reported using EC <binarynumber>0b000000</binarynumber>.</para> 141</field_value_description> 142 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCR or MRC access"/> 143 </field_value_instance> 144 <field_value_instance> 145 <field_value>0b000100</field_value> 146 <field_value_description> 147 <para>Trapped MCRR or MRRC access with (coproc==<binarynumber>0b1111</binarynumber>) that is not reported using EC <binarynumber>0b000000</binarynumber>.</para> 148</field_value_description> 149 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCRR or MRRC access"/> 150 </field_value_instance> 151 <field_value_instance> 152 <field_value>0b000101</field_value> 153 <field_value_description> 154 <para>Trapped MCR or MRC access with (coproc==<binarynumber>0b1110</binarynumber>).</para> 155</field_value_description> 156 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCR or MRC access"/> 157 </field_value_instance> 158 <field_value_instance> 159 <field_value>0b000110</field_value> 160 <field_value_description> 161 <para>Trapped LDC or STC access.</para> 162<para>The only architected uses of these instruction are:</para> 163<list type="unordered"> 164<listitem><content>An STC to write data to memory from <register_link state="AArch32" id="AArch32-dbgdtrrxint.xml">DBGDTRRXint</register_link>.</content> 165</listitem><listitem><content>An LDC to read data from memory to <register_link state="AArch32" id="AArch32-dbgdtrtxint.xml">DBGDTRTXint</register_link>.</content> 166</listitem></list> 167</field_value_description> 168 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an LDC or STC instruction"/> 169 </field_value_instance> 170 <field_value_instance> 171 <field_value>0b000111</field_value> 172 <field_value_description> 173 <para>Access to SVE, Advanced SIMD, or floating-point functionality trapped by <register_link state="AArch64" id="AArch64-cpacr_el1.xml">CPACR_EL1</register_link>.FPEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.FPEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.TFP, or <register_link state="AArch64" id="AArch64-cptr_el3.xml">CPTR_EL3</register_link>.TFP control.</para> 174<para>Excludes exceptions resulting from <register_link state="AArch64" id="AArch64-cpacr_el1.xml">CPACR_EL1</register_link> when the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1, or because SVE or Advanced SIMD and floating-point are not implemented. These are reported with EC value <binarynumber>0b000000</binarynumber> as described in <xref linkend="CHDJCBHE" browsertext="'EC encodings when routing exceptions to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.10.4" filename="D_the_aarch64_system_level_programmers_model"/>.</para> 175</field_value_description> 176 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an access to SVE, Advanced SIMD or floating-point functionality, resulting from CPACR_EL1.FPEN, CPTR_EL2.FPEN or CPTR_ELx.TFP"/> 177 </field_value_instance> 178 <field_value_instance> 179 <field_value>0b001100</field_value> 180 <field_value_description> 181 <para>Trapped MRRC access with (coproc==<binarynumber>0b1110</binarynumber>).</para> 182</field_value_description> 183 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCRR or MRRC access"/> 184 </field_value_instance> 185 <field_value_instance> 186 <field_value>0b001101</field_value> 187 <field_value_description> 188 <para>Branch Target Exception.</para> 189</field_value_description> 190 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from Branch Target Identification instruction"/> 191 <field_value_condition>When ARMv8.5-BTI is implemented</field_value_condition> 192 </field_value_instance> 193 <field_value_instance> 194 <field_value>0b001110</field_value> 195 <field_value_description> 196 <para>Illegal Execution state.</para> 197</field_value_description> 198 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Illegal Execution state, or a PC or SP alignment fault"/> 199 </field_value_instance> 200 <field_value_instance> 201 <field_value>0b010001</field_value> 202 <field_value_description> 203 <para>SVC instruction execution in AArch32 state.</para> 204<para>This is reported in ESR_EL2 only when the exception is generated because the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1.</para> 205</field_value_description> 206 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from HVC or SVC instruction execution"/> 207 </field_value_instance> 208 <field_value_instance> 209 <field_value>0b010101</field_value> 210 <field_value_description> 211 <para>SVC instruction execution in AArch64 state.</para> 212</field_value_description> 213 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from HVC or SVC instruction execution"/> 214 </field_value_instance> 215 <field_value_instance> 216 <field_value>0b011000</field_value> 217 <field_value_description> 218 <para>Trapped MSR, MRS or System instruction execution in AArch64 state, that is not reported using EC <binarynumber>0b000000</binarynumber>, <binarynumber>0b000001</binarynumber> or <binarynumber>0b000111</binarynumber>.</para> 219<para>If <xref browsertext="ARMv8.4-IDST" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.4.IDST"></xref> is implemented, also exceptions generated on a read of an ID register.</para> 220<para>If <xref browsertext="ARMv8.0-CSV2" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.0.CSV2"></xref> is implemented, also Cache Speculation Variant exceptions.</para> 221<para>This includes all instructions that cause exceptions that are part of the encoding space defined in <xref linkend="BEIJIEIE" browsertext="'System instruction class encoding overview' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C5.2.2" filename="C_the_a64_system_instruction_class"/>, except for those exceptions reported using EC values <binarynumber>0b000000</binarynumber>, <binarynumber>0b000001</binarynumber>, or <binarynumber>0b000111</binarynumber>.</para> 222</field_value_description> 223 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from MSR, MRS, or System instruction execution in AArch64 state"/> 224 </field_value_instance> 225 <field_value_instance> 226 <field_value>0b011001</field_value> 227 <field_value_description> 228 <para>Access to SVE functionality trapped as a result of <register_link state="AArch64" id="AArch64-cpacr_el1.xml">CPACR_EL1</register_link>.ZEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.ZEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.TZ, or <register_link state="AArch64" id="AArch64-cptr_el3.xml">CPTR_EL3</register_link>.EZ, that is not reported using EC <binarynumber>0b000000</binarynumber>.</para> 229<para>This EC is defined only if <xref linkend="SVE" browsertext="SVE" filename="A_introduction_to_the_armv8_architecture.fm"/> is implemented.</para> 230</field_value_description> 231 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an access to SVE functionality, resulting from CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ"/> 232 </field_value_instance> 233 <field_value_instance> 234 <field_value>0b100000</field_value> 235 <field_value_description> 236 <para>Instruction Abort from a lower Exception level, that might be using AArch32 or AArch64.</para> 237<para>Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para> 238</field_value_description> 239 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Instruction Abort"/> 240 </field_value_instance> 241 <field_value_instance> 242 <field_value>0b100001</field_value> 243 <field_value_description> 244 <para>Instruction Abort taken without a change in Exception level.</para> 245<para>Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para> 246</field_value_description> 247 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Instruction Abort"/> 248 </field_value_instance> 249 <field_value_instance> 250 <field_value>0b100010</field_value> 251 <field_value_description> 252 <para>PC alignment fault exception.</para> 253</field_value_description> 254 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Illegal Execution state, or a PC or SP alignment fault"/> 255 </field_value_instance> 256 <field_value_instance> 257 <field_value>0b100100</field_value> 258 <field_value_description> 259 <para>Data Abort from a lower Exception level, that might be using AArch32 or AArch64.</para> 260<para>Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para> 261</field_value_description> 262 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Data Abort"/> 263 </field_value_instance> 264 <field_value_instance> 265 <field_value>0b100101</field_value> 266 <field_value_description> 267 <para>Data Abort taken without a change in Exception level.</para> 268<para>Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para> 269</field_value_description> 270 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Data Abort"/> 271 </field_value_instance> 272 <field_value_instance> 273 <field_value>0b100110</field_value> 274 <field_value_description> 275 <para>SP alignment fault exception.</para> 276</field_value_description> 277 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Illegal Execution state, or a PC or SP alignment fault"/> 278 </field_value_instance> 279 <field_value_instance> 280 <field_value>0b101000</field_value> 281 <field_value_description> 282 <para>Trapped floating-point exception taken from AArch32 state.</para> 283<para>This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para> 284</field_value_description> 285 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a trapped floating-point exception"/> 286 </field_value_instance> 287 <field_value_instance> 288 <field_value>0b101100</field_value> 289 <field_value_description> 290 <para>Trapped floating-point exception taken from AArch64 state.</para> 291<para>This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para> 292</field_value_description> 293 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a trapped floating-point exception"/> 294 </field_value_instance> 295 <field_value_instance> 296 <field_value>0b101111</field_value> 297 <field_value_description> 298 <para>SError interrupt.</para> 299</field_value_description> 300 <field_value_links_to linked_field_name="ISS" linked_field_condition="SError interrupt"/> 301 </field_value_instance> 302 <field_value_instance> 303 <field_value>0b110000</field_value> 304 <field_value_description> 305 <para>Breakpoint exception from a lower Exception level, that might be using AArch32 or AArch64.</para> 306</field_value_description> 307 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Breakpoint or Vector Catch debug exception"/> 308 </field_value_instance> 309 <field_value_instance> 310 <field_value>0b110001</field_value> 311 <field_value_description> 312 <para>Breakpoint exception taken without a change in Exception level.</para> 313</field_value_description> 314 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Breakpoint or Vector Catch debug exception"/> 315 </field_value_instance> 316 <field_value_instance> 317 <field_value>0b110010</field_value> 318 <field_value_description> 319 <para>Software Step exception from a lower Exception level, that might be using AArch32 or AArch64.</para> 320</field_value_description> 321 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Software Step exception"/> 322 </field_value_instance> 323 <field_value_instance> 324 <field_value>0b110011</field_value> 325 <field_value_description> 326 <para>Software Step exception taken without a change in Exception level.</para> 327</field_value_description> 328 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Software Step exception"/> 329 </field_value_instance> 330 <field_value_instance> 331 <field_value>0b110100</field_value> 332 <field_value_description> 333 <para>Watchpoint exception from a lower Exception level, that might be using AArch32 or AArch64.</para> 334</field_value_description> 335 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Watchpoint exception"/> 336 </field_value_instance> 337 <field_value_instance> 338 <field_value>0b110101</field_value> 339 <field_value_description> 340 <para>Watchpoint exception taken without a change in Exception level.</para> 341</field_value_description> 342 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Watchpoint exception"/> 343 </field_value_instance> 344 <field_value_instance> 345 <field_value>0b111000</field_value> 346 <field_value_description> 347 <para>BKPT instruction execution in AArch32 state.</para> 348</field_value_description> 349 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from execution of a Breakpoint instruction"/> 350 </field_value_instance> 351 <field_value_instance> 352 <field_value>0b111100</field_value> 353 <field_value_description> 354 <para>BRK instruction execution in AArch64 state.</para> 355<para>This is reported in <register_link state="AArch64" id="AArch64-esr_el3.xml">ESR_EL3</register_link> only if a BRK instruction is executed.</para> 356</field_value_description> 357 <field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from execution of a Breakpoint instruction"/> 358 </field_value_instance> 359 </field_values> 360 <field_description order="after"> 361 362 <para>All other EC values are reserved by Arm, and:</para> 363<list type="unordered"> 364<listitem><content>Unused values in the range <binarynumber>0b000000</binarynumber> - <binarynumber>0b101100</binarynumber> (<hexnumber>0x00</hexnumber> - <hexnumber>0x2C</hexnumber>) are reserved for future use for synchronous exceptions.</content> 365</listitem><listitem><content>Unused values in the range <binarynumber>0b101101</binarynumber> - <binarynumber>0b111111</binarynumber> (<hexnumber>0x2D</hexnumber> - <hexnumber>0x3F</hexnumber>) are reserved for future use, and might be used for synchronous or asynchronous exceptions.</content> 366</listitem></list> 367<para>The effect of programming this field to a reserved value is that behavior is <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word>, as described in <xref linkend="CEGHGHJI" browsertext="'Reserved values in System and memory-mapped registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.1.11"/>.</para> 368 369 </field_description> 370 <field_resets> 371 372 <field_reset> 373 374 <field_reset_standard_text>U</field_reset_standard_text> 375 376 </field_reset> 377</field_resets> 378 </field> 379 <field 380 id="IL_25_25" 381 is_variable_length="False" 382 has_partial_fieldset="False" 383 is_linked_to_partial_fieldset="False" 384 is_access_restriction_possible="False" 385 is_constant_value="False" 386 > 387 <field_name>IL</field_name> 388 <field_msb>25</field_msb> 389 <field_lsb>25</field_lsb> 390 <field_description order="before"> 391 392 <para>Instruction Length for synchronous exceptions. Possible values of this bit are:</para> 393 394 </field_description> 395 <field_values> 396 397 398 <field_value_instance> 399 <field_value>0b0</field_value> 400 <field_value_description> 401 <para>16-bit instruction trapped.</para> 402</field_value_description> 403 </field_value_instance> 404 <field_value_instance> 405 <field_value>0b1</field_value> 406 <field_value_description> 407 <list type="unordered"> 408<listitem><content> 409<para>An SError interrupt.</para> 410</content> 411</listitem><listitem><content> 412<para>An Instruction Abort exception.</para> 413</content> 414</listitem><listitem><content> 415<para>A PC alignment fault exception.</para> 416</content> 417</listitem><listitem><content> 418<para>An SP alignment fault exception.</para> 419</content> 420</listitem><listitem><content> 421<para>A Data Abort exception for which the value of the ISV bit is 0.</para> 422</content> 423</listitem><listitem><content> 424<para>An Illegal Execution state exception.</para> 425</content> 426</listitem><listitem><content> 427<para>Any debug exception except for Breakpoint instruction exceptions. For Breakpoint instruction exceptions, this bit has its standard meaning:</para> 428<list type="unordered"> 429<listitem><content> 430<para><binarynumber>0b0</binarynumber>: 16-bit T32 BKPT instruction.</para> 431</content> 432</listitem><listitem><content> 433<para><binarynumber>0b1</binarynumber>: 32-bit A32 BKPT instruction or A64 BRK instruction.</para> 434</content> 435</listitem></list> 436</content> 437</listitem><listitem><content> 438<para>An exception reported using EC value <binarynumber>0b000000</binarynumber>.</para> 439</content> 440</listitem></list> 441</field_value_description> 442 </field_value_instance> 443 </field_values> 444 <field_resets> 445 446 <field_reset> 447 448 <field_reset_standard_text>U</field_reset_standard_text> 449 450 </field_reset> 451</field_resets> 452 </field> 453 <field 454 id="ISS_24_0" 455 is_variable_length="False" 456 has_partial_fieldset="True" 457 is_linked_to_partial_fieldset="False" 458 is_access_restriction_possible="False" 459 is_constant_value="False" 460 > 461 <field_name>ISS</field_name> 462 <field_msb>24</field_msb> 463 <field_lsb>0</field_lsb> 464 <field_description order="before"> 465 466 <para>Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class.</para> 467<para>Typically, an ISS encoding has a number of subfields. When an ISS subfield holds a register number, the value returned in that field is the AArch64 view of the register number. For an exception taken from AArch32 state, <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1,"/> defines this view of the specified AArch32 register. If the AArch32 register descriptor is <binarynumber>0b1111</binarynumber>, then:</para> 468<list type="unordered"> 469<listitem><content>If the instruction that generated the exception was not <arm-defined-word>UNPREDICTABLE</arm-defined-word>, the field takes the value <binarynumber>0b11111</binarynumber>.</content> 470</listitem><listitem><content>If the instruction that generated the exception was <arm-defined-word>UNPREDICTABLE</arm-defined-word>, the field takes an <arm-defined-word>UNKNOWN</arm-defined-word> value that must be either:<list type="unordered"> 471<listitem><content>The AArch64 view of the register number of a register that might have been used at the Exception level from which the exception was taken.</content> 472</listitem><listitem><content>The value <binarynumber>0b11111</binarynumber>.</content> 473</listitem></list> 474</content> 475</listitem></list> 476<para>When the EC field is <binarynumber>0b000000</binarynumber>, indicating an exception with an unknown reason, the ISS field is not valid, <arm-defined-word>RES0</arm-defined-word>.</para> 477 478 </field_description> 479 <field_values> 480 481 <field_value_name>I</field_value_name> 482 </field_values> 483 <field_resets> 484 485</field_resets> 486 <partial_fieldset> 487 <fields length="25"> 488 <fields_instance>Exceptions with an unknown reason</fields_instance> 489 <text_before_fields> 490 491 492 493 </text_before_fields> 494 495 <field 496 id="0_24_0" 497 is_variable_length="False" 498 has_partial_fieldset="False" 499 is_linked_to_partial_fieldset="False" 500 is_access_restriction_possible="False" 501 is_constant_value="False" 502 rwtype="RES0" 503 > 504 <field_name>0</field_name> 505 <field_msb>24</field_msb> 506 <field_lsb>0</field_lsb> 507 <field_description order="before"> 508 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 509 </field_description> 510 <field_values> 511 </field_values> 512 </field> 513 <text_after_fields> 514 515 <para>When an exception is reported using this EC code the IL field is set to 1.</para> 516<para>This EC code is used for all exceptions that are not covered by any other EC value. This includes exceptions that are generated in the following situations:</para> 517<list type="unordered"> 518<listitem><content>The attempted execution of an instruction bit pattern that has no allocated instruction at the current Exception level and Security state, including:<list type="unordered"> 519<listitem><content>A read access using a System register pattern that is not allocated for reads at the current Exception level and Security state.</content> 520</listitem><listitem><content>A write access using a System register pattern that is not allocated for writes at the current Exception level and Security state.</content> 521</listitem><listitem><content>Instruction encodings for instructions not implemented in the implementation.</content> 522</listitem></list> 523</content> 524</listitem><listitem><content>In Debug state, the attempted execution of an instruction bit pattern that is unallocated in Debug state.</content> 525</listitem><listitem><content>In Non-debug state, the attempted execution of an instruction bit pattern that is unallocated in Non-debug state.</content> 526</listitem><listitem><content>In AArch32 state, attempted execution of a short vector floating-point instruction.</content> 527</listitem><listitem><content>In an implementation that does not include Advanced SIMD and floating-point functionality, an attempted access to Advanced SIMD or floating-point functionality under conditions where that access would be permitted if that functionality was present. This includes the attempted execution of an Advanced SIMD or floating-point instruction, and attempted accesses to Advanced SIMD and floating-point System registers.</content> 528</listitem><listitem><content>An exception generated because of the value of one of the <register_link state="AArch64" id="AArch64-sctlr_el1.xml">SCTLR_EL1</register_link>.{ITD, SED, CP15BEN} control bits.</content> 529</listitem><listitem><content>Attempted execution of:<list type="unordered"> 530<listitem><content>An HVC instruction when disabled by <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.HCD or <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.HCE.</content> 531</listitem><listitem><content>An SMC instruction when disabled by <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.SMD.</content> 532</listitem><listitem><content>An HLT instruction when disabled by <register_link state="ext" id="ext-edscr.xml">EDSCR</register_link>.HDE.</content> 533</listitem></list> 534</content> 535</listitem><listitem><content>Attempted execution of an MSR or MRS instruction to access <register_link state="AArch64" id="AArch64-sp_el0.xml">SP_EL0</register_link> when the value of <register_link state="AArch64" id="AArch64-spsel.xml">SPSel</register_link>.SP is 0.</content> 536</listitem><listitem><content>Attempted execution, in Debug state, of:<list type="unordered"> 537<listitem><content>A DCPS1 instruction when the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1 and EL2 is disabled or not implemented in the current Security state.</content> 538</listitem><listitem><content>A DCPS2 instruction from EL1 or EL0 when EL2 is disabled or not implemented in the current Security state.</content> 539</listitem><listitem><content>A DCPS3 instruction when the value of <register_link state="ext" id="ext-edscr.xml">EDSCR</register_link>.SDD is 1, or when EL3 is not implemented.</content> 540</listitem></list> 541</content> 542</listitem><listitem><content>When EL3 is using AArch64, attempted execution from Secure EL1 of an SRS instruction using R13_mon. See <xref linkend="CHDJIEBG" browsertext="'Traps to EL3 of monitor functionality from Secure EL1 using AArch32' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 543</listitem><listitem><content>In Debug state when the value of <register_link state="ext" id="ext-edscr.xml">EDSCR</register_link>.SDD is 1, the attempted execution at EL2, EL1, or EL0 of an instruction that is configured to trap to EL3.</content> 544</listitem><listitem><content>In AArch32 state, the attempted execution of an MRS (banked register) or an MSR (banked register) instruction to SPSR_mon, SP_mon, or LR_mon.</content> 545</listitem><listitem><content>An exception that is taken to EL2 because the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1 that, if the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE was 0 would have been reported with an ESR_ELx.EC value of <binarynumber>0b000111</binarynumber>.</content> 546</listitem><listitem><content>When SVE is not implemented, attempted execution of:<list type="unordered"> 547<listitem><content>An SVE instruction.</content> 548</listitem><listitem><content>An MSR or MRS instruction to access <register_link state="AArch64" id="AArch64-zcr_el1.xml">ZCR_EL1</register_link>, <register_link state="AArch64" id="AArch64-zcr_el2.xml">ZCR_EL2</register_link>, or <register_link state="AArch64" id="AArch64-zcr_el3.xml">ZCR_EL3</register_link>.</content> 549</listitem></list> 550</content> 551</listitem></list> 552 553 </text_after_fields> 554 </fields> 555 <reg_fieldset length="25"> 556 557 558 559 560 <fieldat id="0_24_0" msb="24" lsb="0"/> 561 </reg_fieldset> 562 </partial_fieldset> 563 <partial_fieldset> 564 <fields length="25"> 565 <fields_instance>Exception from a WFI or WFE instruction</fields_instance> 566 <text_before_fields> 567 568 569 570 </text_before_fields> 571 572 <field 573 id="CV_24_24" 574 is_variable_length="False" 575 has_partial_fieldset="False" 576 is_linked_to_partial_fieldset="False" 577 is_access_restriction_possible="False" 578 is_constant_value="False" 579 > 580 <field_name>CV</field_name> 581 <field_msb>24</field_msb> 582 <field_lsb>24</field_lsb> 583 <field_description order="before"> 584 585 <para>Condition code valid. Possible values of this bit are:</para> 586 587 </field_description> 588 <field_values> 589 590 591 <field_value_instance> 592 <field_value>0b0</field_value> 593 <field_value_description> 594 <para>The COND field is not valid.</para> 595</field_value_description> 596 </field_value_instance> 597 <field_value_instance> 598 <field_value>0b1</field_value> 599 <field_value_description> 600 <para>The COND field is valid.</para> 601</field_value_description> 602 </field_value_instance> 603 </field_values> 604 <field_description order="after"> 605 606 <para>For exceptions taken from AArch64, CV is set to 1.</para> 607<para>For exceptions taken from AArch32:</para> 608<list type="unordered"> 609<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content> 610</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content> 611</listitem></list> 612 613 </field_description> 614 <field_resets> 615 616 <field_reset> 617 618 <field_reset_standard_text>U</field_reset_standard_text> 619 620 </field_reset> 621</field_resets> 622 </field> 623 <field 624 id="COND_23_20" 625 is_variable_length="False" 626 has_partial_fieldset="False" 627 is_linked_to_partial_fieldset="False" 628 is_access_restriction_possible="False" 629 is_constant_value="False" 630 > 631 <field_name>COND</field_name> 632 <field_msb>23</field_msb> 633 <field_lsb>20</field_lsb> 634 <field_description order="before"> 635 636 <para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para> 637<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para> 638<para>For exceptions taken from AArch32:</para> 639<list type="unordered"> 640<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered"> 641<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content> 642</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content> 643</listitem></list> 644</content> 645</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered"> 646<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content> 647</listitem><listitem><content>With the COND value held in the instruction.</content> 648</listitem></list> 649</content> 650</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered"> 651<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content> 652</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content> 653</listitem></list> 654</content> 655</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content> 656</listitem></list> 657 658 </field_description> 659 <field_values> 660 661 662 </field_values> 663 <field_resets> 664 665 <field_reset> 666 667 <field_reset_standard_text>U</field_reset_standard_text> 668 669 </field_reset> 670</field_resets> 671 </field> 672 <field 673 id="0_19_1" 674 is_variable_length="False" 675 has_partial_fieldset="False" 676 is_linked_to_partial_fieldset="False" 677 is_access_restriction_possible="False" 678 is_constant_value="False" 679 rwtype="RES0" 680 > 681 <field_name>0</field_name> 682 <field_msb>19</field_msb> 683 <field_lsb>1</field_lsb> 684 <field_description order="before"> 685 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 686 </field_description> 687 <field_values> 688 </field_values> 689 </field> 690 <field 691 id="TI_0_0" 692 is_variable_length="False" 693 has_partial_fieldset="False" 694 is_linked_to_partial_fieldset="False" 695 is_access_restriction_possible="False" 696 is_constant_value="False" 697 > 698 <field_name>TI</field_name> 699 <field_msb>0</field_msb> 700 <field_lsb>0</field_lsb> 701 <field_description order="before"> 702 703 <para>Trapped instruction. Possible values of this bit are:</para> 704 705 </field_description> 706 <field_values> 707 708 709 <field_value_instance> 710 <field_value>0b0</field_value> 711 <field_value_description> 712 <para>WFI trapped.</para> 713</field_value_description> 714 </field_value_instance> 715 <field_value_instance> 716 <field_value>0b1</field_value> 717 <field_value_description> 718 <para>WFE trapped.</para> 719</field_value_description> 720 </field_value_instance> 721 </field_values> 722 <field_resets> 723 724 <field_reset> 725 726 <field_reset_standard_text>U</field_reset_standard_text> 727 728 </field_reset> 729</field_resets> 730 </field> 731 <text_after_fields> 732 733 <para>The following sections describe configuration settings for generating this exception:</para> 734<list type="unordered"> 735<listitem><content><xref linkend="D1CHDJGAIC" browsertext="'Controls for exceptions taken to EL1 using AArch64' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 736</listitem><listitem><content><xref linkend="D1BEIBHJCJ" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 execution of WFE and WFI instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 737</listitem><listitem><content><xref linkend="D1CHDEGCIJ" browsertext="'Traps to EL3 of EL2, EL1, and EL0 execution of WFE and WFI instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 738</listitem></list> 739 740 </text_after_fields> 741 </fields> 742 <reg_fieldset length="25"> 743 744 745 746 747 748 749 750 751 752 753 <fieldat id="CV_24_24" msb="24" lsb="24"/> 754 <fieldat id="COND_23_20" msb="23" lsb="20"/> 755 <fieldat id="0_19_1" msb="19" lsb="1"/> 756 <fieldat id="TI_0_0" msb="0" lsb="0"/> 757 </reg_fieldset> 758 </partial_fieldset> 759 <partial_fieldset> 760 <fields length="25"> 761 <fields_instance>Exception from an MCR or MRC access</fields_instance> 762 <text_before_fields> 763 764 765 766 </text_before_fields> 767 768 <field 769 id="CV_24_24" 770 is_variable_length="False" 771 has_partial_fieldset="False" 772 is_linked_to_partial_fieldset="False" 773 is_access_restriction_possible="False" 774 is_constant_value="False" 775 > 776 <field_name>CV</field_name> 777 <field_msb>24</field_msb> 778 <field_lsb>24</field_lsb> 779 <field_description order="before"> 780 781 <para>Condition code valid. Possible values of this bit are:</para> 782 783 </field_description> 784 <field_values> 785 786 787 <field_value_instance> 788 <field_value>0b0</field_value> 789 <field_value_description> 790 <para>The COND field is not valid.</para> 791</field_value_description> 792 </field_value_instance> 793 <field_value_instance> 794 <field_value>0b1</field_value> 795 <field_value_description> 796 <para>The COND field is valid.</para> 797</field_value_description> 798 </field_value_instance> 799 </field_values> 800 <field_description order="after"> 801 802 <para>For exceptions taken from AArch64, CV is set to 1.</para> 803<para>For exceptions taken from AArch32:</para> 804<list type="unordered"> 805<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content> 806</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content> 807</listitem></list> 808 809 </field_description> 810 <field_resets> 811 812 <field_reset> 813 814 <field_reset_standard_text>U</field_reset_standard_text> 815 816 </field_reset> 817</field_resets> 818 </field> 819 <field 820 id="COND_23_20" 821 is_variable_length="False" 822 has_partial_fieldset="False" 823 is_linked_to_partial_fieldset="False" 824 is_access_restriction_possible="False" 825 is_constant_value="False" 826 > 827 <field_name>COND</field_name> 828 <field_msb>23</field_msb> 829 <field_lsb>20</field_lsb> 830 <field_description order="before"> 831 832 <para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para> 833<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para> 834<para>For exceptions taken from AArch32:</para> 835<list type="unordered"> 836<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered"> 837<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content> 838</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content> 839</listitem></list> 840</content> 841</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered"> 842<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content> 843</listitem><listitem><content>With the COND value held in the instruction.</content> 844</listitem></list> 845</content> 846</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered"> 847<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content> 848</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content> 849</listitem></list> 850</content> 851</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content> 852</listitem></list> 853 854 </field_description> 855 <field_values> 856 857 858 </field_values> 859 <field_resets> 860 861 <field_reset> 862 863 <field_reset_standard_text>U</field_reset_standard_text> 864 865 </field_reset> 866</field_resets> 867 </field> 868 <field 869 id="Opc2_19_17" 870 is_variable_length="False" 871 has_partial_fieldset="False" 872 is_linked_to_partial_fieldset="False" 873 is_access_restriction_possible="False" 874 is_constant_value="False" 875 > 876 <field_name>Opc2</field_name> 877 <field_msb>19</field_msb> 878 <field_lsb>17</field_lsb> 879 <field_description order="before"> 880 881 <para>The Opc2 value from the issued instruction.</para> 882<para>For a trapped VMRS access, holds the value <binarynumber>0b000</binarynumber>.</para> 883 884 </field_description> 885 <field_values> 886 887 888 </field_values> 889 <field_resets> 890 891 <field_reset> 892 893 <field_reset_standard_text>U</field_reset_standard_text> 894 895 </field_reset> 896</field_resets> 897 </field> 898 <field 899 id="Opc1_16_14" 900 is_variable_length="False" 901 has_partial_fieldset="False" 902 is_linked_to_partial_fieldset="False" 903 is_access_restriction_possible="False" 904 is_constant_value="False" 905 > 906 <field_name>Opc1</field_name> 907 <field_msb>16</field_msb> 908 <field_lsb>14</field_lsb> 909 <field_description order="before"> 910 911 <para>The Opc1 value from the issued instruction.</para> 912<para>For a trapped VMRS access, holds the value <binarynumber>0b111</binarynumber>.</para> 913 914 </field_description> 915 <field_values> 916 917 918 </field_values> 919 <field_resets> 920 921 <field_reset> 922 923 <field_reset_standard_text>U</field_reset_standard_text> 924 925 </field_reset> 926</field_resets> 927 </field> 928 <field 929 id="CRn_13_10" 930 is_variable_length="False" 931 has_partial_fieldset="False" 932 is_linked_to_partial_fieldset="False" 933 is_access_restriction_possible="False" 934 is_constant_value="False" 935 > 936 <field_name>CRn</field_name> 937 <field_msb>13</field_msb> 938 <field_lsb>10</field_lsb> 939 <field_description order="before"> 940 941 <para>The CRn value from the issued instruction.</para> 942<para>For a trapped VMRS access, holds the reg field from the VMRS instruction encoding.</para> 943 944 </field_description> 945 <field_values> 946 947 948 </field_values> 949 <field_resets> 950 951 <field_reset> 952 953 <field_reset_standard_text>U</field_reset_standard_text> 954 955 </field_reset> 956</field_resets> 957 </field> 958 <field 959 id="Rt_9_5" 960 is_variable_length="False" 961 has_partial_fieldset="False" 962 is_linked_to_partial_fieldset="False" 963 is_access_restriction_possible="False" 964 is_constant_value="False" 965 > 966 <field_name>Rt</field_name> 967 <field_msb>9</field_msb> 968 <field_lsb>5</field_lsb> 969 <field_description order="before"> 970 971 <para>The Rt value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para> 972 973 </field_description> 974 <field_values> 975 976 977 </field_values> 978 <field_resets> 979 980 <field_reset> 981 982 <field_reset_standard_text>U</field_reset_standard_text> 983 984 </field_reset> 985</field_resets> 986 </field> 987 <field 988 id="CRm_4_1" 989 is_variable_length="False" 990 has_partial_fieldset="False" 991 is_linked_to_partial_fieldset="False" 992 is_access_restriction_possible="False" 993 is_constant_value="False" 994 > 995 <field_name>CRm</field_name> 996 <field_msb>4</field_msb> 997 <field_lsb>1</field_lsb> 998 <field_description order="before"> 999 1000 <para>The CRm value from the issued instruction.</para> 1001<para>For a trapped VMRS access, holds the value <binarynumber>0b0000</binarynumber>.</para> 1002 1003 </field_description> 1004 <field_values> 1005 1006 1007 </field_values> 1008 <field_resets> 1009 1010 <field_reset> 1011 1012 <field_reset_standard_text>U</field_reset_standard_text> 1013 1014 </field_reset> 1015</field_resets> 1016 </field> 1017 <field 1018 id="Direction_0_0" 1019 is_variable_length="False" 1020 has_partial_fieldset="False" 1021 is_linked_to_partial_fieldset="False" 1022 is_access_restriction_possible="False" 1023 is_constant_value="False" 1024 > 1025 <field_name>Direction</field_name> 1026 <field_msb>0</field_msb> 1027 <field_lsb>0</field_lsb> 1028 <field_description order="before"> 1029 1030 <para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para> 1031 1032 </field_description> 1033 <field_values> 1034 1035 1036 <field_value_instance> 1037 <field_value>0b0</field_value> 1038 <field_value_description> 1039 <para>Write to System register space. MCR instruction.</para> 1040</field_value_description> 1041 </field_value_instance> 1042 <field_value_instance> 1043 <field_value>0b1</field_value> 1044 <field_value_description> 1045 <para>Read from System register space. MRC or VMRS instruction.</para> 1046</field_value_description> 1047 </field_value_instance> 1048 </field_values> 1049 <field_resets> 1050 1051 <field_reset> 1052 1053 <field_reset_standard_text>U</field_reset_standard_text> 1054 1055 </field_reset> 1056</field_resets> 1057 </field> 1058 <text_after_fields> 1059 1060 <para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b000011</binarynumber>:</para> 1061<list type="unordered"> 1062<listitem><content><xref linkend="CHDJFHAI" browsertext="'Traps to EL1 of EL0 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1063</listitem><listitem><content><xref linkend="D1CHDGDIEA" browsertext="'Traps to EL1 of EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1064</listitem><listitem><content><xref linkend="BEICGACA" browsertext="'Traps to EL1 of EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1065</listitem><listitem><content><xref linkend="D1BEIGHBDF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1066</listitem><listitem><content><xref linkend="D1BEICAEBH" browsertext="'Traps to EL2 of Non-secure EL1 execution of TLB maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1067</listitem><listitem><content><xref linkend="D1BEICHIHA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 execution of cache maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1068</listitem><listitem><content><xref linkend="D1BEIFCHFF" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the Auxiliary Control Register' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1069</listitem><listitem><content><xref linkend="BEIDHFBB" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to lockdown, DMA, and TCM operations' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1070</listitem><listitem><content><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1071</listitem><listitem><content><xref linkend="D1BEIFFJII" browsertext="'Trapping to EL2 of Non-secure EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1072</listitem><listitem><content><xref linkend="D1BEIDJJAH" browsertext="'Generic trapping to EL2 of Non-secure EL1 and EL0 accesses to System registers, from AArch32 state only' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/></content> 1073</listitem><listitem><content><xref linkend="CHDFFCIB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/></content> 1074</listitem><listitem><content><xref linkend="D1BEICIHGI" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1075</listitem><listitem><content><xref linkend="BEIGCEGJ" browsertext="'Traps to EL2 of EL1 and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1076</listitem><listitem><content><xref linkend="CHDJIEBG" browsertext="'Traps to EL3 of Secure monitor functionality from Secure EL1 using AArch32' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1077</listitem><listitem><content><xref linkend="D1CHDJACCE" browsertext="'Trapping to EL3 of EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1078</listitem><listitem><content><xref linkend="D1CHDGGBGH" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1079</listitem><listitem><content><xref linkend="BEIHHEIC" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1080</listitem></list> 1081<para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b000101</binarynumber>:</para> 1082<list type="unordered"> 1083<listitem><content><xref linkend="D1CHDBAICA" browsertext="'Traps to EL1 of EL0 and EL1 System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1084</listitem><listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1085</listitem><listitem><content><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>, for trapped accesses to the JIDR.</content> 1086</listitem><listitem><content><xref linkend="D1BEIIHJHA" browsertext="'Traps to EL2 of Non-secure system register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1087</listitem><listitem><content><xref linkend="D1BEIHBBIC" browsertext="'Trapping System register accesses to Debug ROM registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1088</listitem><listitem><content><xref linkend="D1BEIECEGJ" browsertext="'Trapping System register accesses to OS-related debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1089</listitem><listitem><content><xref linkend="D1BEICAABI" browsertext="'Trapping general System register accesses to debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1090</listitem><listitem><content><xref linkend="D1CHDJICAB" browsertext="'Traps to EL3 of all System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1091</listitem><listitem><content><xref linkend="D1CHDDHIIA" browsertext="'Trapping System register accesses to OS-related debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1092</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1093</listitem></list> 1094<para><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1," filename="D_the_aarch64_system_level_programmers_model"/> describes configuration settings for generating exceptions that are reported using EC value <binarynumber>0b001000</binarynumber>.</para> 1095 1096 </text_after_fields> 1097 </fields> 1098 <reg_fieldset length="25"> 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 <fieldat id="CV_24_24" msb="24" lsb="24"/> 1118 <fieldat id="COND_23_20" msb="23" lsb="20"/> 1119 <fieldat id="Opc2_19_17" msb="19" lsb="17"/> 1120 <fieldat id="Opc1_16_14" msb="16" lsb="14"/> 1121 <fieldat id="CRn_13_10" msb="13" lsb="10"/> 1122 <fieldat id="Rt_9_5" msb="9" lsb="5"/> 1123 <fieldat id="CRm_4_1" msb="4" lsb="1"/> 1124 <fieldat id="Direction_0_0" msb="0" lsb="0"/> 1125 </reg_fieldset> 1126 </partial_fieldset> 1127 <partial_fieldset> 1128 <fields length="25"> 1129 <fields_instance>Exception from an MCRR or MRRC access</fields_instance> 1130 <text_before_fields> 1131 1132 1133 1134 </text_before_fields> 1135 1136 <field 1137 id="CV_24_24" 1138 is_variable_length="False" 1139 has_partial_fieldset="False" 1140 is_linked_to_partial_fieldset="False" 1141 is_access_restriction_possible="False" 1142 is_constant_value="False" 1143 > 1144 <field_name>CV</field_name> 1145 <field_msb>24</field_msb> 1146 <field_lsb>24</field_lsb> 1147 <field_description order="before"> 1148 1149 <para>Condition code valid. Possible values of this bit are:</para> 1150 1151 </field_description> 1152 <field_values> 1153 1154 1155 <field_value_instance> 1156 <field_value>0b0</field_value> 1157 <field_value_description> 1158 <para>The COND field is not valid.</para> 1159</field_value_description> 1160 </field_value_instance> 1161 <field_value_instance> 1162 <field_value>0b1</field_value> 1163 <field_value_description> 1164 <para>The COND field is valid.</para> 1165</field_value_description> 1166 </field_value_instance> 1167 </field_values> 1168 <field_description order="after"> 1169 1170 <para>For exceptions taken from AArch64, CV is set to 1.</para> 1171<para>For exceptions taken from AArch32:</para> 1172<list type="unordered"> 1173<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content> 1174</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content> 1175</listitem></list> 1176 1177 </field_description> 1178 <field_resets> 1179 1180 <field_reset> 1181 1182 <field_reset_standard_text>U</field_reset_standard_text> 1183 1184 </field_reset> 1185</field_resets> 1186 </field> 1187 <field 1188 id="COND_23_20" 1189 is_variable_length="False" 1190 has_partial_fieldset="False" 1191 is_linked_to_partial_fieldset="False" 1192 is_access_restriction_possible="False" 1193 is_constant_value="False" 1194 > 1195 <field_name>COND</field_name> 1196 <field_msb>23</field_msb> 1197 <field_lsb>20</field_lsb> 1198 <field_description order="before"> 1199 1200 <para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para> 1201<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para> 1202<para>For exceptions taken from AArch32:</para> 1203<list type="unordered"> 1204<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered"> 1205<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content> 1206</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content> 1207</listitem></list> 1208</content> 1209</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered"> 1210<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content> 1211</listitem><listitem><content>With the COND value held in the instruction.</content> 1212</listitem></list> 1213</content> 1214</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered"> 1215<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content> 1216</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content> 1217</listitem></list> 1218</content> 1219</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content> 1220</listitem></list> 1221 1222 </field_description> 1223 <field_values> 1224 1225 1226 </field_values> 1227 <field_resets> 1228 1229 <field_reset> 1230 1231 <field_reset_standard_text>U</field_reset_standard_text> 1232 1233 </field_reset> 1234</field_resets> 1235 </field> 1236 <field 1237 id="Opc1_19_16" 1238 is_variable_length="False" 1239 has_partial_fieldset="False" 1240 is_linked_to_partial_fieldset="False" 1241 is_access_restriction_possible="False" 1242 is_constant_value="False" 1243 > 1244 <field_name>Opc1</field_name> 1245 <field_msb>19</field_msb> 1246 <field_lsb>16</field_lsb> 1247 <field_description order="before"> 1248 1249 <para>The Opc1 value from the issued instruction.</para> 1250 1251 </field_description> 1252 <field_values> 1253 1254 1255 </field_values> 1256 <field_resets> 1257 1258 <field_reset> 1259 1260 <field_reset_standard_text>U</field_reset_standard_text> 1261 1262 </field_reset> 1263</field_resets> 1264 </field> 1265 <field 1266 id="0_15_15" 1267 is_variable_length="False" 1268 has_partial_fieldset="False" 1269 is_linked_to_partial_fieldset="False" 1270 is_access_restriction_possible="False" 1271 is_constant_value="False" 1272 rwtype="RES0" 1273 > 1274 <field_name>0</field_name> 1275 <field_msb>15</field_msb> 1276 <field_lsb>15</field_lsb> 1277 <field_description order="before"> 1278 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 1279 </field_description> 1280 <field_values> 1281 </field_values> 1282 </field> 1283 <field 1284 id="Rt2_14_10" 1285 is_variable_length="False" 1286 has_partial_fieldset="False" 1287 is_linked_to_partial_fieldset="False" 1288 is_access_restriction_possible="False" 1289 is_constant_value="False" 1290 > 1291 <field_name>Rt2</field_name> 1292 <field_msb>14</field_msb> 1293 <field_lsb>10</field_lsb> 1294 <field_description order="before"> 1295 1296 <para>The Rt2 value from the issued instruction, the second general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para> 1297 1298 </field_description> 1299 <field_values> 1300 1301 1302 </field_values> 1303 <field_resets> 1304 1305 <field_reset> 1306 1307 <field_reset_standard_text>U</field_reset_standard_text> 1308 1309 </field_reset> 1310</field_resets> 1311 </field> 1312 <field 1313 id="Rt_9_5" 1314 is_variable_length="False" 1315 has_partial_fieldset="False" 1316 is_linked_to_partial_fieldset="False" 1317 is_access_restriction_possible="False" 1318 is_constant_value="False" 1319 > 1320 <field_name>Rt</field_name> 1321 <field_msb>9</field_msb> 1322 <field_lsb>5</field_lsb> 1323 <field_description order="before"> 1324 1325 <para>The Rt value from the issued instruction, the first general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para> 1326 1327 </field_description> 1328 <field_values> 1329 1330 1331 </field_values> 1332 <field_resets> 1333 1334 <field_reset> 1335 1336 <field_reset_standard_text>U</field_reset_standard_text> 1337 1338 </field_reset> 1339</field_resets> 1340 </field> 1341 <field 1342 id="CRm_4_1" 1343 is_variable_length="False" 1344 has_partial_fieldset="False" 1345 is_linked_to_partial_fieldset="False" 1346 is_access_restriction_possible="False" 1347 is_constant_value="False" 1348 > 1349 <field_name>CRm</field_name> 1350 <field_msb>4</field_msb> 1351 <field_lsb>1</field_lsb> 1352 <field_description order="before"> 1353 1354 <para>The CRm value from the issued instruction.</para> 1355 1356 </field_description> 1357 <field_values> 1358 1359 1360 </field_values> 1361 <field_resets> 1362 1363 <field_reset> 1364 1365 <field_reset_standard_text>U</field_reset_standard_text> 1366 1367 </field_reset> 1368</field_resets> 1369 </field> 1370 <field 1371 id="Direction_0_0" 1372 is_variable_length="False" 1373 has_partial_fieldset="False" 1374 is_linked_to_partial_fieldset="False" 1375 is_access_restriction_possible="False" 1376 is_constant_value="False" 1377 > 1378 <field_name>Direction</field_name> 1379 <field_msb>0</field_msb> 1380 <field_lsb>0</field_lsb> 1381 <field_description order="before"> 1382 1383 <para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para> 1384 1385 </field_description> 1386 <field_values> 1387 1388 1389 <field_value_instance> 1390 <field_value>0b0</field_value> 1391 <field_value_description> 1392 <para>Write to System register space. MCRR instruction.</para> 1393</field_value_description> 1394 </field_value_instance> 1395 <field_value_instance> 1396 <field_value>0b1</field_value> 1397 <field_value_description> 1398 <para>Read from System register space. MRRC instruction.</para> 1399</field_value_description> 1400 </field_value_instance> 1401 </field_values> 1402 <field_resets> 1403 1404 <field_reset> 1405 1406 <field_reset_standard_text>U</field_reset_standard_text> 1407 1408 </field_reset> 1409</field_resets> 1410 </field> 1411 <text_after_fields> 1412 1413 <para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b000100</binarynumber>:</para> 1414<list type="unordered"> 1415<listitem><content><xref linkend="CHDJFHAI" browsertext="'Traps to EL1 of EL0 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1416</listitem><listitem><content><xref linkend="D1CHDGDIEA" browsertext="'Traps to EL1 of EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1417</listitem><listitem><content><xref linkend="BEICGACA" browsertext="'Traps to EL1 of EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1418</listitem><listitem><content><xref linkend="D1BEIGHBDF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1419</listitem><listitem><content><xref linkend="D1BEIDJJAH" browsertext="'General trapping to EL2 of Non-secure EL0 and EL1 accesses to System registers, from AArch32 state only' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1420</listitem><listitem><content><xref linkend="CHDFFCIB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1421</listitem><listitem><content><xref linkend="D1BEICIHGI" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1422</listitem><listitem><content><xref linkend="BEIGCEGJ" browsertext="'Traps to EL2 of EL1 and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1423</listitem><listitem><content><xref linkend="D1CHDGGBGH" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1424</listitem><listitem><content><xref linkend="BEIHHEIC" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1425</listitem></list> 1426<para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b001100</binarynumber>:</para> 1427<list type="unordered"> 1428<listitem><content><xref linkend="D1CHDBAICA" browsertext="'Traps to EL1 of EL0 and EL1 System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1429</listitem><listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1430</listitem><listitem><content><xref linkend="D1BEIIHJHA" browsertext="'Traps to EL2 of Non-secure system register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1431</listitem><listitem><content><xref linkend="D1BEIHBBIC" browsertext="'Trapping System register accesses to Debug ROM registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1432</listitem><listitem><content><xref linkend="D1CHDJICAB" browsertext="'Traps to EL3 of all System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1433</listitem><listitem><content><xref linkend="D1CHDDHIIA" browsertext="'Trapping System register accesses to powerdown debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1434</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1435</listitem></list> 1436 1437 </text_after_fields> 1438 </fields> 1439 <reg_fieldset length="25"> 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 <fieldat id="CV_24_24" msb="24" lsb="24"/> 1459 <fieldat id="COND_23_20" msb="23" lsb="20"/> 1460 <fieldat id="Opc1_19_16" msb="19" lsb="16"/> 1461 <fieldat id="0_15_15" msb="15" lsb="15"/> 1462 <fieldat id="Rt2_14_10" msb="14" lsb="10"/> 1463 <fieldat id="Rt_9_5" msb="9" lsb="5"/> 1464 <fieldat id="CRm_4_1" msb="4" lsb="1"/> 1465 <fieldat id="Direction_0_0" msb="0" lsb="0"/> 1466 </reg_fieldset> 1467 </partial_fieldset> 1468 <partial_fieldset> 1469 <fields length="25"> 1470 <fields_instance>Exception from an LDC or STC instruction</fields_instance> 1471 <text_before_fields> 1472 1473 1474 1475 </text_before_fields> 1476 1477 <field 1478 id="CV_24_24" 1479 is_variable_length="False" 1480 has_partial_fieldset="False" 1481 is_linked_to_partial_fieldset="False" 1482 is_access_restriction_possible="False" 1483 is_constant_value="False" 1484 > 1485 <field_name>CV</field_name> 1486 <field_msb>24</field_msb> 1487 <field_lsb>24</field_lsb> 1488 <field_description order="before"> 1489 1490 <para>Condition code valid. Possible values of this bit are:</para> 1491 1492 </field_description> 1493 <field_values> 1494 1495 1496 <field_value_instance> 1497 <field_value>0b0</field_value> 1498 <field_value_description> 1499 <para>The COND field is not valid.</para> 1500</field_value_description> 1501 </field_value_instance> 1502 <field_value_instance> 1503 <field_value>0b1</field_value> 1504 <field_value_description> 1505 <para>The COND field is valid.</para> 1506</field_value_description> 1507 </field_value_instance> 1508 </field_values> 1509 <field_description order="after"> 1510 1511 <para>For exceptions taken from AArch64, CV is set to 1.</para> 1512<para>For exceptions taken from AArch32:</para> 1513<list type="unordered"> 1514<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content> 1515</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content> 1516</listitem></list> 1517 1518 </field_description> 1519 <field_resets> 1520 1521 <field_reset> 1522 1523 <field_reset_standard_text>U</field_reset_standard_text> 1524 1525 </field_reset> 1526</field_resets> 1527 </field> 1528 <field 1529 id="COND_23_20" 1530 is_variable_length="False" 1531 has_partial_fieldset="False" 1532 is_linked_to_partial_fieldset="False" 1533 is_access_restriction_possible="False" 1534 is_constant_value="False" 1535 > 1536 <field_name>COND</field_name> 1537 <field_msb>23</field_msb> 1538 <field_lsb>20</field_lsb> 1539 <field_description order="before"> 1540 1541 <para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para> 1542<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para> 1543<para>For exceptions taken from AArch32:</para> 1544<list type="unordered"> 1545<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered"> 1546<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content> 1547</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content> 1548</listitem></list> 1549</content> 1550</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered"> 1551<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content> 1552</listitem><listitem><content>With the COND value held in the instruction.</content> 1553</listitem></list> 1554</content> 1555</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered"> 1556<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content> 1557</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content> 1558</listitem></list> 1559</content> 1560</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content> 1561</listitem></list> 1562 1563 </field_description> 1564 <field_values> 1565 1566 1567 </field_values> 1568 <field_resets> 1569 1570 <field_reset> 1571 1572 <field_reset_standard_text>U</field_reset_standard_text> 1573 1574 </field_reset> 1575</field_resets> 1576 </field> 1577 <field 1578 id="imm8_19_12" 1579 is_variable_length="False" 1580 has_partial_fieldset="False" 1581 is_linked_to_partial_fieldset="False" 1582 is_access_restriction_possible="False" 1583 is_constant_value="False" 1584 > 1585 <field_name>imm8</field_name> 1586 <field_msb>19</field_msb> 1587 <field_lsb>12</field_lsb> 1588 <field_description order="before"> 1589 1590 <para>The immediate value from the issued instruction.</para> 1591 1592 </field_description> 1593 <field_values> 1594 1595 1596 </field_values> 1597 <field_resets> 1598 1599 <field_reset> 1600 1601 <field_reset_standard_text>U</field_reset_standard_text> 1602 1603 </field_reset> 1604</field_resets> 1605 </field> 1606 <field 1607 id="0_11_10" 1608 is_variable_length="False" 1609 has_partial_fieldset="False" 1610 is_linked_to_partial_fieldset="False" 1611 is_access_restriction_possible="False" 1612 is_constant_value="False" 1613 rwtype="RES0" 1614 > 1615 <field_name>0</field_name> 1616 <field_msb>11</field_msb> 1617 <field_lsb>10</field_lsb> 1618 <field_description order="before"> 1619 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 1620 </field_description> 1621 <field_values> 1622 </field_values> 1623 </field> 1624 <field 1625 id="Rn_9_5" 1626 is_variable_length="False" 1627 has_partial_fieldset="False" 1628 is_linked_to_partial_fieldset="False" 1629 is_access_restriction_possible="False" 1630 is_constant_value="False" 1631 > 1632 <field_name>Rn</field_name> 1633 <field_msb>9</field_msb> 1634 <field_lsb>5</field_lsb> 1635 <field_description order="before"> 1636 1637 <para>The Rn value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para> 1638<para>This field is valid only when AM[2] is 0, indicating an immediate form of the LDC or STC instruction. When AM[2] is 1, indicating a literal form of the LDC or STC instruction, this field is <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 1639 1640 </field_description> 1641 <field_values> 1642 1643 1644 </field_values> 1645 <field_resets> 1646 1647 <field_reset> 1648 1649 <field_reset_standard_text>U</field_reset_standard_text> 1650 1651 </field_reset> 1652</field_resets> 1653 </field> 1654 <field 1655 id="Offset_4_4" 1656 is_variable_length="False" 1657 has_partial_fieldset="False" 1658 is_linked_to_partial_fieldset="False" 1659 is_access_restriction_possible="False" 1660 is_constant_value="False" 1661 > 1662 <field_name>Offset</field_name> 1663 <field_msb>4</field_msb> 1664 <field_lsb>4</field_lsb> 1665 <field_description order="before"> 1666 1667 <para>Indicates whether the offset is added or subtracted:</para> 1668 1669 </field_description> 1670 <field_values> 1671 1672 1673 <field_value_instance> 1674 <field_value>0b0</field_value> 1675 <field_value_description> 1676 <para>Subtract offset.</para> 1677</field_value_description> 1678 </field_value_instance> 1679 <field_value_instance> 1680 <field_value>0b1</field_value> 1681 <field_value_description> 1682 <para>Add offset.</para> 1683</field_value_description> 1684 </field_value_instance> 1685 </field_values> 1686 <field_description order="after"> 1687 1688 <para>This bit corresponds to the U bit in the instruction encoding.</para> 1689 1690 </field_description> 1691 <field_resets> 1692 1693 <field_reset> 1694 1695 <field_reset_standard_text>U</field_reset_standard_text> 1696 1697 </field_reset> 1698</field_resets> 1699 </field> 1700 <field 1701 id="AM_3_1" 1702 is_variable_length="False" 1703 has_partial_fieldset="False" 1704 is_linked_to_partial_fieldset="False" 1705 is_access_restriction_possible="False" 1706 is_constant_value="False" 1707 > 1708 <field_name>AM</field_name> 1709 <field_msb>3</field_msb> 1710 <field_lsb>1</field_lsb> 1711 <field_description order="before"> 1712 1713 <para>Addressing mode. The permitted values of this field are:</para> 1714 1715 </field_description> 1716 <field_values> 1717 1718 1719 <field_value_instance> 1720 <field_value>0b000</field_value> 1721 <field_value_description> 1722 <para>Immediate unindexed.</para> 1723</field_value_description> 1724 </field_value_instance> 1725 <field_value_instance> 1726 <field_value>0b001</field_value> 1727 <field_value_description> 1728 <para>Immediate post-indexed.</para> 1729</field_value_description> 1730 </field_value_instance> 1731 <field_value_instance> 1732 <field_value>0b010</field_value> 1733 <field_value_description> 1734 <para>Immediate offset.</para> 1735</field_value_description> 1736 </field_value_instance> 1737 <field_value_instance> 1738 <field_value>0b011</field_value> 1739 <field_value_description> 1740 <para>Immediate pre-indexed.</para> 1741</field_value_description> 1742 </field_value_instance> 1743 <field_value_instance> 1744 <field_value>0b100</field_value> 1745 <field_value_description> 1746 <para>For a trapped STC instruction or a trapped T32 LDC instruction this encoding is reserved.</para> 1747</field_value_description> 1748 </field_value_instance> 1749 <field_value_instance> 1750 <field_value>0b110</field_value> 1751 <field_value_description> 1752 <para>For a trapped STC instruction, this encoding is reserved.</para> 1753</field_value_description> 1754 </field_value_instance> 1755 </field_values> 1756 <field_description order="after"> 1757 1758 <para>The values <binarynumber>0b101</binarynumber> and <binarynumber>0b111</binarynumber> are reserved. The effect of programming this field to a reserved value is that behavior is <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word>, as described in <xref linkend="CEGFJDFD" browsertext="'Reserved values in AArch64 System registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.2.2"/>.</para> 1759<para>Bit [2] in this subfield indicates the instruction form, immediate or literal.</para> 1760<para>Bits [1:0] in this subfield correspond to the bits {P, W} in the instruction encoding.</para> 1761 1762 </field_description> 1763 <field_resets> 1764 1765 <field_reset> 1766 1767 <field_reset_standard_text>U</field_reset_standard_text> 1768 1769 </field_reset> 1770</field_resets> 1771 </field> 1772 <field 1773 id="Direction_0_0" 1774 is_variable_length="False" 1775 has_partial_fieldset="False" 1776 is_linked_to_partial_fieldset="False" 1777 is_access_restriction_possible="False" 1778 is_constant_value="False" 1779 > 1780 <field_name>Direction</field_name> 1781 <field_msb>0</field_msb> 1782 <field_lsb>0</field_lsb> 1783 <field_description order="before"> 1784 1785 <para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para> 1786 1787 </field_description> 1788 <field_values> 1789 1790 1791 <field_value_instance> 1792 <field_value>0b0</field_value> 1793 <field_value_description> 1794 <para>Write to memory. STC instruction.</para> 1795</field_value_description> 1796 </field_value_instance> 1797 <field_value_instance> 1798 <field_value>0b1</field_value> 1799 <field_value_description> 1800 <para>Read from memory. LDC instruction.</para> 1801</field_value_description> 1802 </field_value_instance> 1803 </field_values> 1804 <field_resets> 1805 1806 <field_reset> 1807 1808 <field_reset_standard_text>U</field_reset_standard_text> 1809 1810 </field_reset> 1811</field_resets> 1812 </field> 1813 <text_after_fields> 1814 1815 <para>The following sections describe the configuration settings for the traps that are reported using EC value <binarynumber>0b000110</binarynumber>:</para> 1816<list type="unordered"> 1817<listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1818</listitem><listitem><content><xref linkend="D1BEICAABI" browsertext="'Trapping general System register accesses to debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1819</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1820</listitem></list> 1821 1822 </text_after_fields> 1823 </fields> 1824 <reg_fieldset length="25"> 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 <fieldat id="CV_24_24" msb="24" lsb="24"/> 1844 <fieldat id="COND_23_20" msb="23" lsb="20"/> 1845 <fieldat id="imm8_19_12" msb="19" lsb="12"/> 1846 <fieldat id="0_11_10" msb="11" lsb="10"/> 1847 <fieldat id="Rn_9_5" msb="9" lsb="5"/> 1848 <fieldat id="Offset_4_4" msb="4" lsb="4"/> 1849 <fieldat id="AM_3_1" msb="3" lsb="1"/> 1850 <fieldat id="Direction_0_0" msb="0" lsb="0"/> 1851 </reg_fieldset> 1852 </partial_fieldset> 1853 <partial_fieldset> 1854 <fields length="25"> 1855 <fields_instance>Exception from an access to SVE, Advanced SIMD or floating-point functionality, resulting from CPACR_EL1.FPEN, CPTR_EL2.FPEN or CPTR_ELx.TFP</fields_instance> 1856 <text_before_fields> 1857 1858 <para>The accesses covered by this trap include:</para> 1859<list type="unordered"> 1860<listitem><content>Execution of SVE or Advanced SIMD and floating-point instructions.</content> 1861</listitem><listitem><content>Accesses to the Advanced SIMD and floating-point System registers.</content> 1862</listitem></list> 1863<para>For an implementation that does not include either SVE or support for floating-point and Advanced SIMD, the exception is reported using the EC value <binarynumber>0b000000</binarynumber>.</para> 1864 1865 </text_before_fields> 1866 1867 <field 1868 id="CV_24_24" 1869 is_variable_length="False" 1870 has_partial_fieldset="False" 1871 is_linked_to_partial_fieldset="False" 1872 is_access_restriction_possible="False" 1873 is_constant_value="False" 1874 > 1875 <field_name>CV</field_name> 1876 <field_msb>24</field_msb> 1877 <field_lsb>24</field_lsb> 1878 <field_description order="before"> 1879 1880 <para>Condition code valid. Possible values of this bit are:</para> 1881 1882 </field_description> 1883 <field_values> 1884 1885 1886 <field_value_instance> 1887 <field_value>0b0</field_value> 1888 <field_value_description> 1889 <para>The COND field is not valid.</para> 1890</field_value_description> 1891 </field_value_instance> 1892 <field_value_instance> 1893 <field_value>0b1</field_value> 1894 <field_value_description> 1895 <para>The COND field is valid.</para> 1896</field_value_description> 1897 </field_value_instance> 1898 </field_values> 1899 <field_description order="after"> 1900 1901 <para>For exceptions taken from AArch64, CV is set to 1.</para> 1902<para>For exceptions taken from AArch32:</para> 1903<list type="unordered"> 1904<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content> 1905</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content> 1906</listitem></list> 1907 1908 </field_description> 1909 <field_resets> 1910 1911 <field_reset> 1912 1913 <field_reset_standard_text>U</field_reset_standard_text> 1914 1915 </field_reset> 1916</field_resets> 1917 </field> 1918 <field 1919 id="COND_23_20" 1920 is_variable_length="False" 1921 has_partial_fieldset="False" 1922 is_linked_to_partial_fieldset="False" 1923 is_access_restriction_possible="False" 1924 is_constant_value="False" 1925 > 1926 <field_name>COND</field_name> 1927 <field_msb>23</field_msb> 1928 <field_lsb>20</field_lsb> 1929 <field_description order="before"> 1930 1931 <para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para> 1932<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para> 1933<para>For exceptions taken from AArch32:</para> 1934<list type="unordered"> 1935<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered"> 1936<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content> 1937</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content> 1938</listitem></list> 1939</content> 1940</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered"> 1941<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content> 1942</listitem><listitem><content>With the COND value held in the instruction.</content> 1943</listitem></list> 1944</content> 1945</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered"> 1946<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content> 1947</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content> 1948</listitem></list> 1949</content> 1950</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content> 1951</listitem></list> 1952 1953 </field_description> 1954 <field_values> 1955 1956 1957 </field_values> 1958 <field_resets> 1959 1960 <field_reset> 1961 1962 <field_reset_standard_text>U</field_reset_standard_text> 1963 1964 </field_reset> 1965</field_resets> 1966 </field> 1967 <field 1968 id="0_19_0" 1969 is_variable_length="False" 1970 has_partial_fieldset="False" 1971 is_linked_to_partial_fieldset="False" 1972 is_access_restriction_possible="False" 1973 is_constant_value="False" 1974 rwtype="RES0" 1975 > 1976 <field_name>0</field_name> 1977 <field_msb>19</field_msb> 1978 <field_lsb>0</field_lsb> 1979 <field_description order="before"> 1980 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 1981 </field_description> 1982 <field_values> 1983 </field_values> 1984 </field> 1985 <text_after_fields> 1986 1987 <para>The following sections describe the configuration settings for the traps that are reported using EC value <binarynumber>0b000111</binarynumber>:</para> 1988<list type="unordered"> 1989<listitem><content><xref linkend="D1CHDIAIGC" browsertext="'Traps to EL1 of EL0 and EL1 accesses to SIMD and floating-point functionality' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1990</listitem><listitem><content><xref linkend="D1BEIBCFGC" browsertext="'General trapping to EL2 of Non-secure accesses to the SIMD and floating-point registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 1991</listitem><listitem><content><xref linkend="D1CHDDGEFI" browsertext="'Traps to EL3 of all accesses to the SIMD and floating-point registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/></content> 1992</listitem></list> 1993 1994 </text_after_fields> 1995 </fields> 1996 <reg_fieldset length="25"> 1997 1998 1999 2000 2001 2002 2003 2004 2005 <fieldat id="CV_24_24" msb="24" lsb="24"/> 2006 <fieldat id="COND_23_20" msb="23" lsb="20"/> 2007 <fieldat id="0_19_0" msb="19" lsb="0"/> 2008 </reg_fieldset> 2009 </partial_fieldset> 2010 <partial_fieldset> 2011 <fields length="25"> 2012 <fields_instance>Exception from an access to SVE functionality, resulting from CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ</fields_instance> 2013 <text_before_fields> 2014 2015 2016 2017 </text_before_fields> 2018 2019 <field 2020 id="0_24_0_1" 2021 is_variable_length="False" 2022 has_partial_fieldset="False" 2023 is_linked_to_partial_fieldset="False" 2024 is_access_restriction_possible="False" 2025 is_constant_value="False" 2026 rwtype="RES0" 2027 > 2028 <field_name>0</field_name> 2029 <field_msb>24</field_msb> 2030 <field_lsb>0</field_lsb> 2031 <field_description order="before"> 2032 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2033 </field_description> 2034 <field_values> 2035 </field_values> 2036 <fields_condition>When SVE is implemented</fields_condition> 2037 </field> 2038 <field 2039 id="0_24_0_2" 2040 is_variable_length="False" 2041 has_partial_fieldset="False" 2042 is_linked_to_partial_fieldset="False" 2043 is_access_restriction_possible="False" 2044 is_constant_value="False" 2045 rwtype="RES0" 2046 > 2047 <field_name>0</field_name> 2048 <field_msb>24</field_msb> 2049 <field_lsb>0</field_lsb> 2050 <field_description order="before"> 2051 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2052 </field_description> 2053 <field_values> 2054 </field_values> 2055 </field> 2056 <text_after_fields> 2057 2058 <para>The accesses covered by this trap include:</para> 2059<list type="unordered"> 2060<listitem><content>Execution of SVE instructions.</content> 2061</listitem><listitem><content>Accesses to the SVE system registers, ZCR_ELx and ID_AA64ZFR0_EL1.</content> 2062</listitem></list> 2063<para>For an implementation that does not include SVE, the exception is reported using the EC value <binarynumber>0b000000</binarynumber>.</para> 2064 2065 </text_after_fields> 2066 </fields> 2067 <reg_fieldset length="25"> 2068 2069 2070 2071 2072 <fieldat id="0_24_0_1" msb="24" lsb="0"/> 2073 </reg_fieldset> 2074 </partial_fieldset> 2075 <partial_fieldset> 2076 <fields length="25"> 2077 <fields_instance>Exception from an Illegal Execution state, or a PC or SP alignment fault</fields_instance> 2078 <text_before_fields> 2079 2080 2081 2082 </text_before_fields> 2083 2084 <field 2085 id="0_24_0" 2086 is_variable_length="False" 2087 has_partial_fieldset="False" 2088 is_linked_to_partial_fieldset="False" 2089 is_access_restriction_possible="False" 2090 is_constant_value="False" 2091 rwtype="RES0" 2092 > 2093 <field_name>0</field_name> 2094 <field_msb>24</field_msb> 2095 <field_lsb>0</field_lsb> 2096 <field_description order="before"> 2097 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2098 </field_description> 2099 <field_values> 2100 </field_values> 2101 </field> 2102 <text_after_fields> 2103 2104 <para>There are no configuration settings for generating Illegal Execution state exceptions and PC alignment fault exceptions. For more information about these exceptions see <xref linkend="CHDGFFFA" browsertext="'The Illegal Execution state exception' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/> and <xref linkend="BEIFHIFH" browsertext="'PC alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</para> 2105<para><xref linkend="BEIHDCIE" browsertext="'Stack pointer alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/> describes the configuration settings for generating SP alignment fault exceptions.</para> 2106 2107 </text_after_fields> 2108 </fields> 2109 <reg_fieldset length="25"> 2110 2111 2112 2113 2114 <fieldat id="0_24_0" msb="24" lsb="0"/> 2115 </reg_fieldset> 2116 </partial_fieldset> 2117 <partial_fieldset> 2118 <fields length="25"> 2119 <fields_instance>Exception from HVC or SVC instruction execution</fields_instance> 2120 <text_before_fields> 2121 2122 2123 2124 </text_before_fields> 2125 2126 <field 2127 id="0_24_16" 2128 is_variable_length="False" 2129 has_partial_fieldset="False" 2130 is_linked_to_partial_fieldset="False" 2131 is_access_restriction_possible="False" 2132 is_constant_value="False" 2133 rwtype="RES0" 2134 > 2135 <field_name>0</field_name> 2136 <field_msb>24</field_msb> 2137 <field_lsb>16</field_lsb> 2138 <field_description order="before"> 2139 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2140 </field_description> 2141 <field_values> 2142 </field_values> 2143 </field> 2144 <field 2145 id="imm16_15_0" 2146 is_variable_length="False" 2147 has_partial_fieldset="False" 2148 is_linked_to_partial_fieldset="False" 2149 is_access_restriction_possible="False" 2150 is_constant_value="False" 2151 > 2152 <field_name>imm16</field_name> 2153 <field_msb>15</field_msb> 2154 <field_lsb>0</field_lsb> 2155 <field_description order="before"> 2156 2157 <para>The value of the immediate field from the HVC or SVC instruction.</para> 2158<para>For an HVC instruction, and for an A64 SVC instruction, this is the value of the imm16 field of the issued instruction.</para> 2159<para>For an A32 or T32 SVC instruction:</para> 2160<list type="unordered"> 2161<listitem><content>If the instruction is unconditional, then:<list type="unordered"> 2162<listitem><content>For the T32 instruction, this field is zero-extended from the imm8 field of the instruction.</content> 2163</listitem><listitem><content>For the A32 instruction, this field is the bottom 16 bits of the imm24 field of the instruction.</content> 2164</listitem></list> 2165</content> 2166</listitem><listitem><content>If the instruction is conditional, this field is <arm-defined-word>UNKNOWN</arm-defined-word>.</content> 2167</listitem></list> 2168 2169 </field_description> 2170 <field_values> 2171 2172 2173 </field_values> 2174 <field_resets> 2175 2176 <field_reset> 2177 2178 <field_reset_standard_text>U</field_reset_standard_text> 2179 2180 </field_reset> 2181</field_resets> 2182 </field> 2183 <text_after_fields> 2184 2185 <para>In AArch32 state, the HVC instruction is unconditional, and a conditional SVC instruction generates an exception only if it passes its condition code check. Therefore, the syndrome information for these exceptions does not require conditionality information.</para> 2186<para>For T32 and A32 instructions, see <xref linkend="A32T32-base.instructions.SVC" browsertext="'SVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section F7 (T32 and A32 Base Instruction Set Instruction Descriptions)" filename="F_t32_a32_base_instruction_descriptions"/> and <xref linkend="A32T32-base.instructions.HVC" browsertext="'HVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section F7" filename="F_t32_a32_base_instruction_descriptions"/>.</para> 2187<para>For A64 instructions, see <xref linkend="A64.instructions.SVC" browsertext="'SVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C5 (A64 Base Instruction Descriptions)," filename="C_a64_base_instruction_descriptions"/> and <xref linkend="A64.instructions.HVC" browsertext="'HVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C5" filename="C_a64_base_instruction_descriptions"/>.</para> 2188 2189 </text_after_fields> 2190 </fields> 2191 <reg_fieldset length="25"> 2192 2193 2194 2195 2196 2197 2198 <fieldat id="0_24_16" msb="24" lsb="16"/> 2199 <fieldat id="imm16_15_0" msb="15" lsb="0"/> 2200 </reg_fieldset> 2201 </partial_fieldset> 2202 <partial_fieldset> 2203 <fields length="25"> 2204 <fields_instance>Exception from SMC instruction execution in AArch32 state</fields_instance> 2205 <text_before_fields> 2206 2207 <para>For an SMC instruction that completes normally and generates an exception that is taken to EL3, the ISS encoding is <arm-defined-word>RES0</arm-defined-word>.</para> 2208<para>For an SMC instruction that is trapped to EL2 from EL1 because <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TSC is 1, the ISS encoding is as shown in the diagram.</para> 2209 2210 </text_before_fields> 2211 2212 <field 2213 id="CV_24_24" 2214 is_variable_length="False" 2215 has_partial_fieldset="False" 2216 is_linked_to_partial_fieldset="False" 2217 is_access_restriction_possible="False" 2218 is_constant_value="False" 2219 > 2220 <field_name>CV</field_name> 2221 <field_msb>24</field_msb> 2222 <field_lsb>24</field_lsb> 2223 <field_description order="before"> 2224 2225 <para>Condition code valid. Possible values of this bit are:</para> 2226 2227 </field_description> 2228 <field_values> 2229 2230 2231 <field_value_instance> 2232 <field_value>0b0</field_value> 2233 <field_value_description> 2234 <para>The COND field is not valid.</para> 2235</field_value_description> 2236 </field_value_instance> 2237 <field_value_instance> 2238 <field_value>0b1</field_value> 2239 <field_value_description> 2240 <para>The COND field is valid.</para> 2241</field_value_description> 2242 </field_value_instance> 2243 </field_values> 2244 <field_description order="after"> 2245 2246 <para>For exceptions taken from AArch64, CV is set to 1.</para> 2247<para>For exceptions taken from AArch32:</para> 2248<list type="unordered"> 2249<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content> 2250</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content> 2251</listitem></list> 2252<para>This field is only valid if CCKNOWNPASS is 1, otherwise it is <arm-defined-word>RES0</arm-defined-word>.</para> 2253 2254 </field_description> 2255 <field_resets> 2256 2257 <field_reset> 2258 2259 <field_reset_standard_text>U</field_reset_standard_text> 2260 2261 </field_reset> 2262</field_resets> 2263 </field> 2264 <field 2265 id="COND_23_20" 2266 is_variable_length="False" 2267 has_partial_fieldset="False" 2268 is_linked_to_partial_fieldset="False" 2269 is_access_restriction_possible="False" 2270 is_constant_value="False" 2271 > 2272 <field_name>COND</field_name> 2273 <field_msb>23</field_msb> 2274 <field_lsb>20</field_lsb> 2275 <field_description order="before"> 2276 2277 <para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para> 2278<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para> 2279<para>For exceptions taken from AArch32:</para> 2280<list type="unordered"> 2281<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered"> 2282<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content> 2283</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content> 2284</listitem></list> 2285</content> 2286</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered"> 2287<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content> 2288</listitem><listitem><content>With the COND value held in the instruction.</content> 2289</listitem></list> 2290</content> 2291</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered"> 2292<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content> 2293</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content> 2294</listitem></list> 2295</content> 2296</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content> 2297</listitem></list> 2298<para>This field is only valid if CCKNOWNPASS is 1, otherwise it is <arm-defined-word>RES0</arm-defined-word>.</para> 2299 2300 </field_description> 2301 <field_values> 2302 2303 2304 </field_values> 2305 <field_resets> 2306 2307 <field_reset> 2308 2309 <field_reset_standard_text>U</field_reset_standard_text> 2310 2311 </field_reset> 2312</field_resets> 2313 </field> 2314 <field 2315 id="CCKNOWNPASS_19_19" 2316 is_variable_length="False" 2317 has_partial_fieldset="False" 2318 is_linked_to_partial_fieldset="False" 2319 is_access_restriction_possible="False" 2320 is_constant_value="False" 2321 > 2322 <field_name>CCKNOWNPASS</field_name> 2323 <field_msb>19</field_msb> 2324 <field_lsb>19</field_lsb> 2325 <field_description order="before"> 2326 2327 <para>Indicates whether the instruction might have failed its condition code check.</para> 2328 2329 </field_description> 2330 <field_values> 2331 2332 2333 <field_value_instance> 2334 <field_value>0b0</field_value> 2335 <field_value_description> 2336 <para>The instruction was unconditional, or was conditional and passed its condition code check.</para> 2337</field_value_description> 2338 </field_value_instance> 2339 <field_value_instance> 2340 <field_value>0b1</field_value> 2341 <field_value_description> 2342 <para>The instruction was conditional, and might have failed its condition code check.</para> 2343</field_value_description> 2344 </field_value_instance> 2345 </field_values> 2346 <field_description order="after"> 2347 2348 <note><para>In an implementation in which an SMC instruction that fails it code check is not trapped, this field can always return the value 0.</para></note> 2349 2350 </field_description> 2351 <field_resets> 2352 2353 <field_reset> 2354 2355 <field_reset_standard_text>U</field_reset_standard_text> 2356 2357 </field_reset> 2358</field_resets> 2359 </field> 2360 <field 2361 id="0_18_0" 2362 is_variable_length="False" 2363 has_partial_fieldset="False" 2364 is_linked_to_partial_fieldset="False" 2365 is_access_restriction_possible="False" 2366 is_constant_value="False" 2367 rwtype="RES0" 2368 > 2369 <field_name>0</field_name> 2370 <field_msb>18</field_msb> 2371 <field_lsb>0</field_lsb> 2372 <field_description order="before"> 2373 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2374 </field_description> 2375 <field_values> 2376 </field_values> 2377 </field> 2378 <text_after_fields> 2379 2380 <para><xref linkend="BEIGGFEI" browsertext="'Traps to EL2 of Non-secure EL1 execution of SMC instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)," filename="D_the_aarch64_system_level_programmers_model"/> describes the configuration settings for trapping SMC instructions from EL1 modes, and <xref linkend="BEIBEAGE" browsertext="'System calls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.16," filename="D_the_aarch64_system_level_programmers_model"/> describes the case where these exceptions are trapped to EL3.</para> 2381 2382 </text_after_fields> 2383 </fields> 2384 <reg_fieldset length="25"> 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 <fieldat id="CV_24_24" msb="24" lsb="24"/> 2396 <fieldat id="COND_23_20" msb="23" lsb="20"/> 2397 <fieldat id="CCKNOWNPASS_19_19" msb="19" lsb="19"/> 2398 <fieldat id="0_18_0" msb="18" lsb="0"/> 2399 </reg_fieldset> 2400 </partial_fieldset> 2401 <partial_fieldset> 2402 <fields length="25"> 2403 <fields_instance>Exception from SMC instruction execution in AArch64 state</fields_instance> 2404 <text_before_fields> 2405 2406 2407 2408 </text_before_fields> 2409 2410 <field 2411 id="0_24_16" 2412 is_variable_length="False" 2413 has_partial_fieldset="False" 2414 is_linked_to_partial_fieldset="False" 2415 is_access_restriction_possible="False" 2416 is_constant_value="False" 2417 rwtype="RES0" 2418 > 2419 <field_name>0</field_name> 2420 <field_msb>24</field_msb> 2421 <field_lsb>16</field_lsb> 2422 <field_description order="before"> 2423 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2424 </field_description> 2425 <field_values> 2426 </field_values> 2427 </field> 2428 <field 2429 id="imm16_15_0" 2430 is_variable_length="False" 2431 has_partial_fieldset="False" 2432 is_linked_to_partial_fieldset="False" 2433 is_access_restriction_possible="False" 2434 is_constant_value="False" 2435 > 2436 <field_name>imm16</field_name> 2437 <field_msb>15</field_msb> 2438 <field_lsb>0</field_lsb> 2439 <field_description order="before"> 2440 2441 <para>The value of the immediate field from the issued SMC instruction.</para> 2442 2443 </field_description> 2444 <field_values> 2445 2446 2447 </field_values> 2448 <field_resets> 2449 2450 <field_reset> 2451 2452 <field_reset_standard_text>U</field_reset_standard_text> 2453 2454 </field_reset> 2455</field_resets> 2456 </field> 2457 <text_after_fields> 2458 2459 <para>The value of ISS[24:0] described here is used both:</para> 2460<list type="unordered"> 2461<listitem><content>When an SMC instruction is trapped from EL1 modes.</content> 2462</listitem><listitem><content>When an SMC instruction is not trapped, so completes normally and generates an exception that is taken to EL3.</content> 2463</listitem></list> 2464<para><xref linkend="BEIGGFEI" browsertext="'Traps to EL2 of Non-secure EL1 execution of SMC instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)," filename="D_the_aarch64_system_level_programmers_model"/> describes the configuration settings for trapping SMC instructions from Non-secure EL1 modes, and <xref linkend="BEIBEAGE" browsertext="'System calls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.16," filename="D_the_aarch64_system_level_programmers_model"/> describes the case where these exceptions are trapped to EL3.</para> 2465 2466 </text_after_fields> 2467 </fields> 2468 <reg_fieldset length="25"> 2469 2470 2471 2472 2473 2474 2475 <fieldat id="0_24_16" msb="24" lsb="16"/> 2476 <fieldat id="imm16_15_0" msb="15" lsb="0"/> 2477 </reg_fieldset> 2478 </partial_fieldset> 2479 <partial_fieldset> 2480 <fields length="25"> 2481 <fields_instance>Exception from MSR, MRS, or System instruction execution in AArch64 state</fields_instance> 2482 <text_before_fields> 2483 2484 2485 2486 </text_before_fields> 2487 2488 <field 2489 id="0_24_22" 2490 is_variable_length="False" 2491 has_partial_fieldset="False" 2492 is_linked_to_partial_fieldset="False" 2493 is_access_restriction_possible="False" 2494 is_constant_value="False" 2495 rwtype="RES0" 2496 > 2497 <field_name>0</field_name> 2498 <field_msb>24</field_msb> 2499 <field_lsb>22</field_lsb> 2500 <field_description order="before"> 2501 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2502 </field_description> 2503 <field_values> 2504 </field_values> 2505 </field> 2506 <field 2507 id="Op0_21_20" 2508 is_variable_length="False" 2509 has_partial_fieldset="False" 2510 is_linked_to_partial_fieldset="False" 2511 is_access_restriction_possible="False" 2512 is_constant_value="False" 2513 > 2514 <field_name>Op0</field_name> 2515 <field_msb>21</field_msb> 2516 <field_lsb>20</field_lsb> 2517 <field_description order="before"> 2518 2519 <para>The Op0 value from the issued instruction.</para> 2520 2521 </field_description> 2522 <field_values> 2523 2524 2525 </field_values> 2526 <field_resets> 2527 2528 <field_reset> 2529 2530 <field_reset_standard_text>U</field_reset_standard_text> 2531 2532 </field_reset> 2533</field_resets> 2534 </field> 2535 <field 2536 id="Op2_19_17" 2537 is_variable_length="False" 2538 has_partial_fieldset="False" 2539 is_linked_to_partial_fieldset="False" 2540 is_access_restriction_possible="False" 2541 is_constant_value="False" 2542 > 2543 <field_name>Op2</field_name> 2544 <field_msb>19</field_msb> 2545 <field_lsb>17</field_lsb> 2546 <field_description order="before"> 2547 2548 <para>The Op2 value from the issued instruction.</para> 2549 2550 </field_description> 2551 <field_values> 2552 2553 2554 </field_values> 2555 <field_resets> 2556 2557 <field_reset> 2558 2559 <field_reset_standard_text>U</field_reset_standard_text> 2560 2561 </field_reset> 2562</field_resets> 2563 </field> 2564 <field 2565 id="Op1_16_14" 2566 is_variable_length="False" 2567 has_partial_fieldset="False" 2568 is_linked_to_partial_fieldset="False" 2569 is_access_restriction_possible="False" 2570 is_constant_value="False" 2571 > 2572 <field_name>Op1</field_name> 2573 <field_msb>16</field_msb> 2574 <field_lsb>14</field_lsb> 2575 <field_description order="before"> 2576 2577 <para>The Op1 value from the issued instruction.</para> 2578 2579 </field_description> 2580 <field_values> 2581 2582 2583 </field_values> 2584 <field_resets> 2585 2586 <field_reset> 2587 2588 <field_reset_standard_text>U</field_reset_standard_text> 2589 2590 </field_reset> 2591</field_resets> 2592 </field> 2593 <field 2594 id="CRn_13_10" 2595 is_variable_length="False" 2596 has_partial_fieldset="False" 2597 is_linked_to_partial_fieldset="False" 2598 is_access_restriction_possible="False" 2599 is_constant_value="False" 2600 > 2601 <field_name>CRn</field_name> 2602 <field_msb>13</field_msb> 2603 <field_lsb>10</field_lsb> 2604 <field_description order="before"> 2605 2606 <para>The CRn value from the issued instruction.</para> 2607 2608 </field_description> 2609 <field_values> 2610 2611 2612 </field_values> 2613 <field_resets> 2614 2615 <field_reset> 2616 2617 <field_reset_standard_text>U</field_reset_standard_text> 2618 2619 </field_reset> 2620</field_resets> 2621 </field> 2622 <field 2623 id="Rt_9_5" 2624 is_variable_length="False" 2625 has_partial_fieldset="False" 2626 is_linked_to_partial_fieldset="False" 2627 is_access_restriction_possible="False" 2628 is_constant_value="False" 2629 > 2630 <field_name>Rt</field_name> 2631 <field_msb>9</field_msb> 2632 <field_lsb>5</field_lsb> 2633 <field_description order="before"> 2634 2635 <para>The Rt value from the issued instruction, the general-purpose register used for the transfer.</para> 2636 2637 </field_description> 2638 <field_values> 2639 2640 2641 </field_values> 2642 <field_resets> 2643 2644 <field_reset> 2645 2646 <field_reset_standard_text>U</field_reset_standard_text> 2647 2648 </field_reset> 2649</field_resets> 2650 </field> 2651 <field 2652 id="CRm_4_1" 2653 is_variable_length="False" 2654 has_partial_fieldset="False" 2655 is_linked_to_partial_fieldset="False" 2656 is_access_restriction_possible="False" 2657 is_constant_value="False" 2658 > 2659 <field_name>CRm</field_name> 2660 <field_msb>4</field_msb> 2661 <field_lsb>1</field_lsb> 2662 <field_description order="before"> 2663 2664 <para>The CRm value from the issued instruction.</para> 2665 2666 </field_description> 2667 <field_values> 2668 2669 2670 </field_values> 2671 <field_resets> 2672 2673 <field_reset> 2674 2675 <field_reset_standard_text>U</field_reset_standard_text> 2676 2677 </field_reset> 2678</field_resets> 2679 </field> 2680 <field 2681 id="Direction_0_0" 2682 is_variable_length="False" 2683 has_partial_fieldset="False" 2684 is_linked_to_partial_fieldset="False" 2685 is_access_restriction_possible="False" 2686 is_constant_value="False" 2687 > 2688 <field_name>Direction</field_name> 2689 <field_msb>0</field_msb> 2690 <field_lsb>0</field_lsb> 2691 <field_description order="before"> 2692 2693 <para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para> 2694 2695 </field_description> 2696 <field_values> 2697 2698 2699 <field_value_instance> 2700 <field_value>0b0</field_value> 2701 <field_value_description> 2702 <para>Write access, including MSR instructions.</para> 2703</field_value_description> 2704 </field_value_instance> 2705 <field_value_instance> 2706 <field_value>0b1</field_value> 2707 <field_value_description> 2708 <para>Read access, including MRS instructions.</para> 2709</field_value_description> 2710 </field_value_instance> 2711 </field_values> 2712 <field_resets> 2713 2714 <field_reset> 2715 2716 <field_reset_standard_text>U</field_reset_standard_text> 2717 2718 </field_reset> 2719</field_resets> 2720 </field> 2721 <text_after_fields> 2722 2723 <para>For exceptions caused by System instructions, see <xref linkend="A64.encoding_index.system" browsertext="the 'System' subsection of 'Branches, exception generating and System instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C3 (A64 Instruction Set Encoding)," filename="C_a64_instruction_set_encoding"/> for the encoding values returned by an instruction.</para> 2724<para>The following sections describe configuration settings for generating the exception that is reported using EC value <binarynumber>0b011000</binarynumber>:</para> 2725<list type="unordered"> 2726<listitem><content>In <xref linkend="D1BABDIIDI" browsertext="'EL1 configurable controls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.<list type="unordered"> 2727<listitem><content><xref linkend="CHDCDIIJ" browsertext="'Traps to EL1 of EL0 execution of cache maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2728</listitem><listitem><content><xref linkend="D1CHDEIDGH" browsertext="'Traps to EL1 of EL0 accesses to the CTR_EL0' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2729</listitem><listitem><content><xref linkend="D1CHDCDHJA" browsertext="'Traps to EL1 of EL0 execution of DC ZVA instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2730</listitem><listitem><content><xref linkend="D1CHDHABAB" browsertext="'Traps to EL1 of EL0 accesses to the PSTATE.{D, A, I, F} interrupt masks' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1(The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2731</listitem><listitem><content><xref linkend="D1CHDBAICA" browsertext="'Traps to EL1 of EL0 and EL1 System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2732</listitem><listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2733</listitem><listitem><content><xref linkend="CHDJFHAI" browsertext="'Traps to EL1 of EL0 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2734</listitem><listitem><content><xref linkend="D1CHDGDIEA" browsertext="'Traps to EL1 of EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2735</listitem><listitem><content><xref linkend="BEICGACA" browsertext="'Traps to EL1 of EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2736</listitem></list> 2737</content> 2738</listitem><listitem><content>In <xref linkend="D1BABBABAG" browsertext="'EL2 configurable controls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.<list type="unordered"> 2739<listitem><content><xref linkend="D1BEIGHBDF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2740</listitem><listitem><content><xref linkend="CHDEHBGG" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 execution of DC ZVA instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2741</listitem><listitem><content><xref linkend="D1BEICAEBH" browsertext="'Traps to EL2 of Non-secure EL1 execution of TLB maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2742</listitem><listitem><content><xref linkend="D1BEICHIHA" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 execution of cache maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2743</listitem><listitem><content><xref linkend="D1BEIFCHFF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to the Auxiliary Control Register' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2744</listitem><listitem><content><xref linkend="BEIDHFBB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to lockdown, DMA, and TCM operations' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2745</listitem><listitem><content><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2746</listitem><listitem><content><xref linkend="D1BEIFFJII" browsertext="'Trapping to EL2 of Non-secure EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2747</listitem><listitem><content><xref linkend="D1BEIIHJHA" browsertext="'Traps to EL2 of Non-secure system register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2748</listitem><listitem><content><xref linkend="D1BEIHBBIC" browsertext="'Trapping System register accesses to Debug ROM registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2749</listitem><listitem><content><xref linkend="D1BEIECEGJ" browsertext="'Trapping System register accesses to OS-related debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2750</listitem><listitem><content><xref linkend="CHDFFCIB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2751</listitem><listitem><content><xref linkend="D1BEICAABI" browsertext="'Trapping general System register accesses to debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2752</listitem><listitem><content><xref linkend="D1BEICIHGI" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2753</listitem><listitem><content><xref linkend="BEIGCEGJ" browsertext="'Traps to EL2 of EL1 and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2754</listitem><listitem><content><xref linkend="CHDIAGCG" browsertext="'Trap to EL2 Non-secure EL1 accesses to Pointer authentication key registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2755</listitem><listitem><content><xref linkend="CHDCFJDF" browsertext="'Traps to EL2 for Nested virtualization' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2756</listitem><listitem><content><xref linkend="CHDIJFAH" browsertext="'Trap to EL2 Non-secure EL1 accesses to AT S1E* instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2757</listitem><listitem><content><xref linkend="CHDFBJDH" browsertext="'Trap to EL3 accesses to Pointer authentication key registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2758</listitem></list> 2759</content> 2760</listitem><listitem><content>In <xref linkend="D1BABCFDGA" browsertext="'EL3 configurable controls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.<list type="unordered"> 2761<listitem><content><xref linkend="CHDHAJBA" browsertext="'Traps to EL3 of Secure EL1 accesses to the Counter-timer Physical Secure timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2762</listitem><listitem><content><xref linkend="D1CHDJACCE" browsertext="'Trapping to EL3 of EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2763</listitem><listitem><content><xref linkend="D1CHDJICAB" browsertext="'Traps to EL3 of all System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2764</listitem><listitem><content><xref linkend="D1CHDDHIIA" browsertext="'Trapping System register accesses to OS-related debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2765</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2766</listitem><listitem><content><xref linkend="D1CHDGGBGH" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2767</listitem><listitem><content><xref linkend="BEIHHEIC" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 2768</listitem></list> 2769</content> 2770</listitem></list> 2771 2772 </text_after_fields> 2773 </fields> 2774 <reg_fieldset length="25"> 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 <fieldat id="0_24_22" msb="24" lsb="22"/> 2794 <fieldat id="Op0_21_20" msb="21" lsb="20"/> 2795 <fieldat id="Op2_19_17" msb="19" lsb="17"/> 2796 <fieldat id="Op1_16_14" msb="16" lsb="14"/> 2797 <fieldat id="CRn_13_10" msb="13" lsb="10"/> 2798 <fieldat id="Rt_9_5" msb="9" lsb="5"/> 2799 <fieldat id="CRm_4_1" msb="4" lsb="1"/> 2800 <fieldat id="Direction_0_0" msb="0" lsb="0"/> 2801 </reg_fieldset> 2802 </partial_fieldset> 2803 <partial_fieldset> 2804 <fields length="25"> 2805 <fields_instance>IMPLEMENTATION DEFINED exception to EL3</fields_instance> 2806 <text_before_fields> 2807 2808 2809 2810 </text_before_fields> 2811 2812 <field 2813 id="IMPLEMENTATION DEFINED_24_0" 2814 is_variable_length="False" 2815 has_partial_fieldset="False" 2816 is_linked_to_partial_fieldset="False" 2817 is_access_restriction_possible="False" 2818 is_constant_value="False" 2819 > 2820 <field_name>IMPLEMENTATION DEFINED</field_name> 2821 <field_msb>24</field_msb> 2822 <field_lsb>0</field_lsb> 2823 <field_description order="before"> 2824 <para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para> 2825 2826 2827 2828 </field_description> 2829 <field_values> 2830 2831 <field_value_name>I</field_value_name> 2832 </field_values> 2833 <field_resets> 2834 2835 <field_reset> 2836 2837 <field_reset_standard_text>U</field_reset_standard_text> 2838 2839 </field_reset> 2840</field_resets> 2841 </field> 2842 <text_after_fields> 2843 2844 2845 2846 </text_after_fields> 2847 </fields> 2848 <reg_fieldset length="25"> 2849 2850 2851 2852 2853 <fieldat id="IMPLEMENTATION DEFINED_24_0" msb="24" lsb="0"/> 2854 </reg_fieldset> 2855 </partial_fieldset> 2856 <partial_fieldset> 2857 <fields length="25"> 2858 <fields_instance>Exception from an Instruction Abort</fields_instance> 2859 <text_before_fields> 2860 2861 2862 2863 </text_before_fields> 2864 2865 <field 2866 id="0_24_13" 2867 is_variable_length="False" 2868 has_partial_fieldset="False" 2869 is_linked_to_partial_fieldset="False" 2870 is_access_restriction_possible="False" 2871 is_constant_value="False" 2872 rwtype="RES0" 2873 > 2874 <field_name>0</field_name> 2875 <field_msb>24</field_msb> 2876 <field_lsb>13</field_lsb> 2877 <field_description order="before"> 2878 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 2879 </field_description> 2880 <field_values> 2881 </field_values> 2882 </field> 2883 <field 2884 id="SET_12_11" 2885 is_variable_length="False" 2886 has_partial_fieldset="False" 2887 is_linked_to_partial_fieldset="False" 2888 is_access_restriction_possible="False" 2889 is_constant_value="False" 2890 > 2891 <field_name>SET</field_name> 2892 <field_msb>12</field_msb> 2893 <field_lsb>11</field_lsb> 2894 <field_description order="before"> 2895 2896 <para>Synchronous Error Type. When the RAS Extension is implemented and IFSC is <binarynumber>0b010000</binarynumber>, describes the state of the PE after taking the Instruction Abort exception. The possible values of this field are:</para> 2897 2898 </field_description> 2899 <field_values> 2900 2901 2902 <field_value_instance> 2903 <field_value>0b00</field_value> 2904 <field_value_description> 2905 <para>Recoverable error (UER).</para> 2906</field_value_description> 2907 </field_value_instance> 2908 <field_value_instance> 2909 <field_value>0b10</field_value> 2910 <field_value_description> 2911 <para>Uncontainable error (UC).</para> 2912</field_value_description> 2913 </field_value_instance> 2914 <field_value_instance> 2915 <field_value>0b11</field_value> 2916 <field_value_description> 2917 <para>Restartable error (UEO) or Corrected error (CE).</para> 2918</field_value_description> 2919 </field_value_instance> 2920 </field_values> 2921 <field_description order="after"> 2922 2923 <para>All other values are reserved.</para> 2924<note><para>Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in an unrecoverable PE state.</para></note><para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para> 2925<list type="unordered"> 2926<listitem><content>The RAS Extension is not implemented.</content> 2927</listitem><listitem><content>The value returned in the IFSC field is not <binarynumber>0b010000</binarynumber>.</content> 2928</listitem></list> 2929 2930 </field_description> 2931 <field_resets> 2932 2933 <field_reset> 2934 2935 <field_reset_standard_text>U</field_reset_standard_text> 2936 2937 </field_reset> 2938</field_resets> 2939 </field> 2940 <field 2941 id="FnV_10_10" 2942 is_variable_length="False" 2943 has_partial_fieldset="False" 2944 is_linked_to_partial_fieldset="False" 2945 is_access_restriction_possible="False" 2946 is_constant_value="False" 2947 > 2948 <field_name>FnV</field_name> 2949 <field_msb>10</field_msb> 2950 <field_lsb>10</field_lsb> 2951 <field_description order="before"> 2952 2953 <para>FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.</para> 2954 2955 </field_description> 2956 <field_values> 2957 2958 2959 <field_value_instance> 2960 <field_value>0b0</field_value> 2961 <field_value_description> 2962 <para>FAR is valid.</para> 2963</field_value_description> 2964 </field_value_instance> 2965 <field_value_instance> 2966 <field_value>0b1</field_value> 2967 <field_value_description> 2968 <para>FAR is not valid, and holds an <arm-defined-word>UNKNOWN</arm-defined-word> value.</para> 2969</field_value_description> 2970 </field_value_instance> 2971 </field_values> 2972 <field_description order="after"> 2973 2974 <para>This field is only valid if the IFSC code is <binarynumber>0b010000</binarynumber>. It is <arm-defined-word>RES0</arm-defined-word> for all other aborts.</para> 2975 2976 </field_description> 2977 <field_resets> 2978 2979 <field_reset> 2980 2981 <field_reset_standard_text>U</field_reset_standard_text> 2982 2983 </field_reset> 2984</field_resets> 2985 </field> 2986 <field 2987 id="EA_9_9" 2988 is_variable_length="False" 2989 has_partial_fieldset="False" 2990 is_linked_to_partial_fieldset="False" 2991 is_access_restriction_possible="False" 2992 is_constant_value="False" 2993 > 2994 <field_name>EA</field_name> 2995 <field_msb>9</field_msb> 2996 <field_lsb>9</field_lsb> 2997 <field_description order="before"> 2998 2999 <para>External abort type. This bit can provide an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> classification of External aborts.</para> 3000<para>For any abort other than an External abort this bit returns a value of 0.</para> 3001 3002 </field_description> 3003 <field_values> 3004 3005 3006 </field_values> 3007 <field_resets> 3008 3009 <field_reset> 3010 3011 <field_reset_standard_text>U</field_reset_standard_text> 3012 3013 </field_reset> 3014</field_resets> 3015 </field> 3016 <field 3017 id="0_8_8" 3018 is_variable_length="False" 3019 has_partial_fieldset="False" 3020 is_linked_to_partial_fieldset="False" 3021 is_access_restriction_possible="False" 3022 is_constant_value="False" 3023 rwtype="RES0" 3024 > 3025 <field_name>0</field_name> 3026 <field_msb>8</field_msb> 3027 <field_lsb>8</field_lsb> 3028 <field_description order="before"> 3029 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 3030 </field_description> 3031 <field_values> 3032 </field_values> 3033 </field> 3034 <field 3035 id="S1PTW_7_7" 3036 is_variable_length="False" 3037 has_partial_fieldset="False" 3038 is_linked_to_partial_fieldset="False" 3039 is_access_restriction_possible="False" 3040 is_constant_value="False" 3041 > 3042 <field_name>S1PTW</field_name> 3043 <field_msb>7</field_msb> 3044 <field_lsb>7</field_lsb> 3045 <field_description order="before"> 3046 3047 <para>For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:</para> 3048 3049 </field_description> 3050 <field_values> 3051 3052 3053 <field_value_instance> 3054 <field_value>0b0</field_value> 3055 <field_value_description> 3056 <para>Fault not on a stage 2 translation for a stage 1 translation table walk.</para> 3057</field_value_description> 3058 </field_value_instance> 3059 <field_value_instance> 3060 <field_value>0b1</field_value> 3061 <field_value_description> 3062 <para>Fault on the stage 2 translation of an access for a stage 1 translation table walk.</para> 3063</field_value_description> 3064 </field_value_instance> 3065 </field_values> 3066 <field_description order="after"> 3067 3068 <para>For any abort other than a stage 2 fault this bit is <arm-defined-word>RES0</arm-defined-word>.</para> 3069 3070 </field_description> 3071 <field_resets> 3072 3073 <field_reset> 3074 3075 <field_reset_standard_text>U</field_reset_standard_text> 3076 3077 </field_reset> 3078</field_resets> 3079 </field> 3080 <field 3081 id="0_6_6" 3082 is_variable_length="False" 3083 has_partial_fieldset="False" 3084 is_linked_to_partial_fieldset="False" 3085 is_access_restriction_possible="False" 3086 is_constant_value="False" 3087 rwtype="RES0" 3088 > 3089 <field_name>0</field_name> 3090 <field_msb>6</field_msb> 3091 <field_lsb>6</field_lsb> 3092 <field_description order="before"> 3093 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 3094 </field_description> 3095 <field_values> 3096 </field_values> 3097 </field> 3098 <field 3099 id="IFSC_5_0" 3100 is_variable_length="False" 3101 has_partial_fieldset="False" 3102 is_linked_to_partial_fieldset="False" 3103 is_access_restriction_possible="False" 3104 is_constant_value="False" 3105 > 3106 <field_name>IFSC</field_name> 3107 <field_msb>5</field_msb> 3108 <field_lsb>0</field_lsb> 3109 <field_description order="before"> 3110 3111 <para>Instruction Fault Status Code. Possible values of this field are:</para> 3112 3113 </field_description> 3114 <field_values> 3115 3116 3117 <field_value_instance> 3118 <field_value>0b000000</field_value> 3119 <field_value_description> 3120 <para>Address size fault, level 0 of translation or translation table base register</para> 3121</field_value_description> 3122 </field_value_instance> 3123 <field_value_instance> 3124 <field_value>0b000001</field_value> 3125 <field_value_description> 3126 <para>Address size fault, level 1</para> 3127</field_value_description> 3128 </field_value_instance> 3129 <field_value_instance> 3130 <field_value>0b000010</field_value> 3131 <field_value_description> 3132 <para>Address size fault, level 2</para> 3133</field_value_description> 3134 </field_value_instance> 3135 <field_value_instance> 3136 <field_value>0b000011</field_value> 3137 <field_value_description> 3138 <para>Address size fault, level 3</para> 3139</field_value_description> 3140 </field_value_instance> 3141 <field_value_instance> 3142 <field_value>0b000100</field_value> 3143 <field_value_description> 3144 <para>Translation fault, level 0</para> 3145</field_value_description> 3146 </field_value_instance> 3147 <field_value_instance> 3148 <field_value>0b000101</field_value> 3149 <field_value_description> 3150 <para>Translation fault, level 1</para> 3151</field_value_description> 3152 </field_value_instance> 3153 <field_value_instance> 3154 <field_value>0b000110</field_value> 3155 <field_value_description> 3156 <para>Translation fault, level 2</para> 3157</field_value_description> 3158 </field_value_instance> 3159 <field_value_instance> 3160 <field_value>0b000111</field_value> 3161 <field_value_description> 3162 <para>Translation fault, level 3</para> 3163</field_value_description> 3164 </field_value_instance> 3165 <field_value_instance> 3166 <field_value>0b001001</field_value> 3167 <field_value_description> 3168 <para>Access flag fault, level 1</para> 3169</field_value_description> 3170 </field_value_instance> 3171 <field_value_instance> 3172 <field_value>0b001010</field_value> 3173 <field_value_description> 3174 <para>Access flag fault, level 2</para> 3175</field_value_description> 3176 </field_value_instance> 3177 <field_value_instance> 3178 <field_value>0b001011</field_value> 3179 <field_value_description> 3180 <para>Access flag fault, level 3</para> 3181</field_value_description> 3182 </field_value_instance> 3183 <field_value_instance> 3184 <field_value>0b001101</field_value> 3185 <field_value_description> 3186 <para>Permission fault, level 1</para> 3187</field_value_description> 3188 </field_value_instance> 3189 <field_value_instance> 3190 <field_value>0b001110</field_value> 3191 <field_value_description> 3192 <para>Permission fault, level 2</para> 3193</field_value_description> 3194 </field_value_instance> 3195 <field_value_instance> 3196 <field_value>0b001111</field_value> 3197 <field_value_description> 3198 <para>Permission fault, level 3</para> 3199</field_value_description> 3200 </field_value_instance> 3201 <field_value_instance> 3202 <field_value>0b010000</field_value> 3203 <field_value_description> 3204 <para>Synchronous External abort, not on translation table walk</para> 3205</field_value_description> 3206 </field_value_instance> 3207 <field_value_instance> 3208 <field_value>0b010100</field_value> 3209 <field_value_description> 3210 <para>Synchronous External abort, on translation table walk, level 0</para> 3211</field_value_description> 3212 </field_value_instance> 3213 <field_value_instance> 3214 <field_value>0b010101</field_value> 3215 <field_value_description> 3216 <para>Synchronous External abort, on translation table walk, level 1</para> 3217</field_value_description> 3218 </field_value_instance> 3219 <field_value_instance> 3220 <field_value>0b010110</field_value> 3221 <field_value_description> 3222 <para>Synchronous External abort, on translation table walk, level 2</para> 3223</field_value_description> 3224 </field_value_instance> 3225 <field_value_instance> 3226 <field_value>0b010111</field_value> 3227 <field_value_description> 3228 <para>Synchronous External abort, on translation table walk, level 3</para> 3229</field_value_description> 3230 </field_value_instance> 3231 <field_value_instance> 3232 <field_value>0b011000</field_value> 3233 <field_value_description> 3234 <para>Synchronous parity or ECC error on memory access, not on translation table walk</para> 3235</field_value_description> 3236 </field_value_instance> 3237 <field_value_instance> 3238 <field_value>0b011100</field_value> 3239 <field_value_description> 3240 <para>Synchronous parity or ECC error on memory access on translation table walk, level 0</para> 3241</field_value_description> 3242 </field_value_instance> 3243 <field_value_instance> 3244 <field_value>0b011101</field_value> 3245 <field_value_description> 3246 <para>Synchronous parity or ECC error on memory access on translation table walk, level 1</para> 3247</field_value_description> 3248 </field_value_instance> 3249 <field_value_instance> 3250 <field_value>0b011110</field_value> 3251 <field_value_description> 3252 <para>Synchronous parity or ECC error on memory access on translation table walk, level 2</para> 3253</field_value_description> 3254 </field_value_instance> 3255 <field_value_instance> 3256 <field_value>0b011111</field_value> 3257 <field_value_description> 3258 <para>Synchronous parity or ECC error on memory access on translation table walk, level 3</para> 3259</field_value_description> 3260 </field_value_instance> 3261 <field_value_instance> 3262 <field_value>0b110000</field_value> 3263 <field_value_description> 3264 <para>TLB conflict abort</para> 3265</field_value_description> 3266 </field_value_instance> 3267 <field_value_instance> 3268 <field_value>0b110001</field_value> 3269 <field_value_description> 3270 <para>Unsupported atomic hardware update fault, if the implementation includes <xref browsertext="ARMv8.1-TTHM]" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.1.TTHM"></xref>. Otherwise reserved.</para> 3271</field_value_description> 3272 </field_value_instance> 3273 </field_values> 3274 <field_description order="after"> 3275 3276 <para>All other values are reserved.</para> 3277<para>When the RAS Extension is implemented, <binarynumber>0b011000</binarynumber>, <binarynumber>0b011100</binarynumber>, <binarynumber>0b011101</binarynumber>, <binarynumber>0b011110</binarynumber>, and <binarynumber>0b011111</binarynumber>, are reserved.</para> 3278<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note><para>For more information about the lookup level associated with a fault, see <xref linkend="CACDHEEH" browsertext="'The level associated with MMU faults' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile"/>.</para> 3279<note><para>Because Access flag faults and Permission faults can only result from a Block or Page translation table descriptor, they cannot occur at level 0.</para></note><para>If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.</para> 3280 3281 </field_description> 3282 <field_resets> 3283 3284 <field_reset> 3285 3286 <field_reset_standard_text>U</field_reset_standard_text> 3287 3288 </field_reset> 3289</field_resets> 3290 </field> 3291 <text_after_fields> 3292 3293 3294 3295 </text_after_fields> 3296 </fields> 3297 <reg_fieldset length="25"> 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 <fieldat id="0_24_13" msb="24" lsb="13"/> 3317 <fieldat id="SET_12_11" msb="12" lsb="11"/> 3318 <fieldat id="FnV_10_10" msb="10" lsb="10"/> 3319 <fieldat id="EA_9_9" msb="9" lsb="9"/> 3320 <fieldat id="0_8_8" msb="8" lsb="8"/> 3321 <fieldat id="S1PTW_7_7" msb="7" lsb="7"/> 3322 <fieldat id="0_6_6" msb="6" lsb="6"/> 3323 <fieldat id="IFSC_5_0" msb="5" lsb="0"/> 3324 </reg_fieldset> 3325 </partial_fieldset> 3326 <partial_fieldset> 3327 <fields length="25"> 3328 <fields_instance>Exception from a Data Abort</fields_instance> 3329 <text_before_fields> 3330 3331 3332 3333 </text_before_fields> 3334 3335 <field 3336 id="ISV_24_24" 3337 is_variable_length="False" 3338 has_partial_fieldset="False" 3339 is_linked_to_partial_fieldset="False" 3340 is_access_restriction_possible="False" 3341 is_constant_value="False" 3342 > 3343 <field_name>ISV</field_name> 3344 <field_msb>24</field_msb> 3345 <field_lsb>24</field_lsb> 3346 <field_description order="before"> 3347 3348 <para>Instruction syndrome valid. Indicates whether the syndrome information in ISS[23:0] is valid.</para> 3349 3350 </field_description> 3351 <field_values> 3352 3353 3354 <field_value_instance> 3355 <field_value>0b0</field_value> 3356 <field_value_description> 3357 <para>No valid instruction syndrome. ISS[23:14] are <arm-defined-word>RES0</arm-defined-word>.</para> 3358</field_value_description> 3359 </field_value_instance> 3360 <field_value_instance> 3361 <field_value>0b1</field_value> 3362 <field_value_description> 3363 <para>ISS[23:14] hold a valid instruction syndrome.</para> 3364</field_value_description> 3365 </field_value_instance> 3366 </field_values> 3367 <field_description order="after"> 3368 3369 <para>This bit is 0 for all faults reported in ESR_EL2 except the following stage 2 aborts:</para> 3370<list type="unordered"> 3371<listitem><content>AArch64 loads and stores of a single general-purpose register (including the register specified with <binarynumber>0b11111</binarynumber>, including those with Acquire/Release semantics, but excluding Load Exclusive or Store Exclusive and excluding those with writeback.</content> 3372</listitem><listitem><content>AArch32 instructions where the instruction:<list type="unordered"> 3373<listitem><content>Is an LDR, LDA, LDRT, LDRSH, LDRSHT, LDRH, LDAH, LDRHT, LDRSB, LDRSBT, LDRB, LDAB, LDRBT, STR, STL, STRT, STRH, STLH, STRHT, STRB, STLB, or STRBT instruction.</content> 3374</listitem><listitem><content>Is not performing register writeback.</content> 3375</listitem><listitem><content>Is not using R15 as a source or destination register.</content> 3376</listitem></list> 3377</content> 3378</listitem></list> 3379<para>For these cases, ISV is <arm-defined-word>UNKNOWN</arm-defined-word> if the exception was generated in Debug state in memory access mode, and otherwise indicates whether ISS[23:14] hold a valid syndrome.</para> 3380<para>ISV is 0 for all faults reported in ESR_EL1 or ESR_EL3.</para> 3381<para>When the RAS Extension is implemented, ISV is 0 for any synchronous External abort.</para> 3382<para>For ISS reporting, a stage 2 abort on a stage 1 translation table walk does not return a valid instruction syndrome, and therefore ISV is 0 for these aborts.</para> 3383<para>When the RAS Extension is not implemented, the value of ISV on a synchronous External abort on a stage 2 translation table walk is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para> 3384 3385 </field_description> 3386 <field_resets> 3387 3388 <field_reset> 3389 3390 <field_reset_standard_text>U</field_reset_standard_text> 3391 3392 </field_reset> 3393</field_resets> 3394 </field> 3395 <field 3396 id="SAS_23_22" 3397 is_variable_length="False" 3398 has_partial_fieldset="False" 3399 is_linked_to_partial_fieldset="False" 3400 is_access_restriction_possible="False" 3401 is_constant_value="False" 3402 > 3403 <field_name>SAS</field_name> 3404 <field_msb>23</field_msb> 3405 <field_lsb>22</field_lsb> 3406 <field_description order="before"> 3407 3408 <para>Syndrome Access Size. When ISV is 1, indicates the size of the access attempted by the faulting operation.</para> 3409 3410 </field_description> 3411 <field_values> 3412 3413 3414 <field_value_instance> 3415 <field_value>0b00</field_value> 3416 <field_value_description> 3417 <para>Byte</para> 3418</field_value_description> 3419 </field_value_instance> 3420 <field_value_instance> 3421 <field_value>0b01</field_value> 3422 <field_value_description> 3423 <para>Halfword</para> 3424</field_value_description> 3425 </field_value_instance> 3426 <field_value_instance> 3427 <field_value>0b10</field_value> 3428 <field_value_description> 3429 <para>Word</para> 3430</field_value_description> 3431 </field_value_instance> 3432 <field_value_instance> 3433 <field_value>0b11</field_value> 3434 <field_value_description> 3435 <para>Doubleword</para> 3436</field_value_description> 3437 </field_value_instance> 3438 </field_values> 3439 <field_description order="after"> 3440 3441 <para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 3442<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para> 3443 3444 </field_description> 3445 <field_resets> 3446 3447 <field_reset> 3448 3449 <field_reset_standard_text>U</field_reset_standard_text> 3450 3451 </field_reset> 3452</field_resets> 3453 </field> 3454 <field 3455 id="SSE_21_21" 3456 is_variable_length="False" 3457 has_partial_fieldset="False" 3458 is_linked_to_partial_fieldset="False" 3459 is_access_restriction_possible="False" 3460 is_constant_value="False" 3461 > 3462 <field_name>SSE</field_name> 3463 <field_msb>21</field_msb> 3464 <field_lsb>21</field_lsb> 3465 <field_description order="before"> 3466 3467 <para>Syndrome Sign Extend. When ISV is 1, for a byte, halfword, or word load operation, indicates whether the data item must be sign extended. For these cases, the possible values of this bit are:</para> 3468 3469 </field_description> 3470 <field_values> 3471 3472 3473 <field_value_instance> 3474 <field_value>0b0</field_value> 3475 <field_value_description> 3476 <para>Sign-extension not required.</para> 3477</field_value_description> 3478 </field_value_instance> 3479 <field_value_instance> 3480 <field_value>0b1</field_value> 3481 <field_value_description> 3482 <para>Data item must be sign-extended.</para> 3483</field_value_description> 3484 </field_value_instance> 3485 </field_values> 3486 <field_description order="after"> 3487 3488 <para>For all other operations this bit is 0.</para> 3489<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 3490<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para> 3491 3492 </field_description> 3493 <field_resets> 3494 3495 <field_reset> 3496 3497 <field_reset_standard_text>U</field_reset_standard_text> 3498 3499 </field_reset> 3500</field_resets> 3501 </field> 3502 <field 3503 id="SRT_20_16" 3504 is_variable_length="False" 3505 has_partial_fieldset="False" 3506 is_linked_to_partial_fieldset="False" 3507 is_access_restriction_possible="False" 3508 is_constant_value="False" 3509 > 3510 <field_name>SRT</field_name> 3511 <field_msb>20</field_msb> 3512 <field_lsb>16</field_lsb> 3513 <field_description order="before"> 3514 3515 <para>Syndrome Register transfer. When ISV is 1, the register number of the Rt operand of the faulting instruction. If the exception was taken from an Exception level that is using AArch32 then this is the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para> 3516<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 3517<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para> 3518 3519 </field_description> 3520 <field_values> 3521 3522 3523 </field_values> 3524 <field_resets> 3525 3526 <field_reset> 3527 3528 <field_reset_standard_text>U</field_reset_standard_text> 3529 3530 </field_reset> 3531</field_resets> 3532 </field> 3533 <field 3534 id="SF_15_15" 3535 is_variable_length="False" 3536 has_partial_fieldset="False" 3537 is_linked_to_partial_fieldset="False" 3538 is_access_restriction_possible="False" 3539 is_constant_value="False" 3540 > 3541 <field_name>SF</field_name> 3542 <field_msb>15</field_msb> 3543 <field_lsb>15</field_lsb> 3544 <field_description order="before"> 3545 3546 <para>Width of the register accessed by the instruction is Sixty-Four. When ISV is 1, the possible values of this bit are:</para> 3547 3548 </field_description> 3549 <field_values> 3550 3551 3552 <field_value_instance> 3553 <field_value>0b0</field_value> 3554 <field_value_description> 3555 <para>Instruction loads/stores a 32-bit wide register.</para> 3556</field_value_description> 3557 </field_value_instance> 3558 <field_value_instance> 3559 <field_value>0b1</field_value> 3560 <field_value_description> 3561 <para>Instruction loads/stores a 64-bit wide register.</para> 3562</field_value_description> 3563 </field_value_instance> 3564 </field_values> 3565 <field_description order="after"> 3566 3567 <note><para>This field specifies the register width identified by the instruction, not the Execution state.</para></note><para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 3568<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para> 3569 3570 </field_description> 3571 <field_resets> 3572 3573 <field_reset> 3574 3575 <field_reset_standard_text>U</field_reset_standard_text> 3576 3577 </field_reset> 3578</field_resets> 3579 </field> 3580 <field 3581 id="AR_14_14" 3582 is_variable_length="False" 3583 has_partial_fieldset="False" 3584 is_linked_to_partial_fieldset="False" 3585 is_access_restriction_possible="False" 3586 is_constant_value="False" 3587 > 3588 <field_name>AR</field_name> 3589 <field_msb>14</field_msb> 3590 <field_lsb>14</field_lsb> 3591 <field_description order="before"> 3592 3593 <para>Acquire/Release. When ISV is 1, the possible values of this bit are:</para> 3594 3595 </field_description> 3596 <field_values> 3597 3598 3599 <field_value_instance> 3600 <field_value>0b0</field_value> 3601 <field_value_description> 3602 <para>Instruction did not have acquire/release semantics.</para> 3603</field_value_description> 3604 </field_value_instance> 3605 <field_value_instance> 3606 <field_value>0b1</field_value> 3607 <field_value_description> 3608 <para>Instruction did have acquire/release semantics.</para> 3609</field_value_description> 3610 </field_value_instance> 3611 </field_values> 3612 <field_description order="after"> 3613 3614 <para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 3615<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para> 3616 3617 </field_description> 3618 <field_resets> 3619 3620 <field_reset> 3621 3622 <field_reset_standard_text>U</field_reset_standard_text> 3623 3624 </field_reset> 3625</field_resets> 3626 </field> 3627 <field 3628 id="VNCR_13_13_1" 3629 is_variable_length="False" 3630 has_partial_fieldset="False" 3631 is_linked_to_partial_fieldset="False" 3632 is_access_restriction_possible="False" 3633 is_constant_value="False" 3634 > 3635 <field_name>VNCR</field_name> 3636 <field_msb>13</field_msb> 3637 <field_lsb>13</field_lsb> 3638 <field_description order="before"> 3639 3640 <para>Indicates that the fault came from use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> register by EL1 code.</para> 3641 3642 </field_description> 3643 <field_values> 3644 3645 3646 <field_value_instance> 3647 <field_value>0b0</field_value> 3648 <field_value_description> 3649 <para>The fault was not generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link>, by an MRS or MSR instruction executed at EL1.</para> 3650</field_value_description> 3651 </field_value_instance> 3652 <field_value_instance> 3653 <field_value>0b1</field_value> 3654 <field_value_description> 3655 <para>The fault was generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link>, by an MRS or MSR instruction executed at EL1.</para> 3656</field_value_description> 3657 </field_value_instance> 3658 </field_values> 3659 <field_description order="after"> 3660 3661 <para>This field is 0 in ESR_EL1.</para> 3662 3663 </field_description> 3664 <field_resets> 3665 3666 <field_reset> 3667 3668 <field_reset_standard_text>U</field_reset_standard_text> 3669 3670 </field_reset> 3671</field_resets> 3672 <fields_condition>When ARMv8.4-NV is implemented</fields_condition> 3673 </field> 3674 <field 3675 id="0_13_13_2" 3676 is_variable_length="False" 3677 has_partial_fieldset="False" 3678 is_linked_to_partial_fieldset="False" 3679 is_access_restriction_possible="False" 3680 is_constant_value="False" 3681 rwtype="RES0" 3682 > 3683 <field_name>0</field_name> 3684 <field_msb>13</field_msb> 3685 <field_lsb>13</field_lsb> 3686 <field_description order="before"> 3687 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 3688 </field_description> 3689 <field_values> 3690 </field_values> 3691 </field> 3692 <field 3693 id="SET_12_11" 3694 is_variable_length="False" 3695 has_partial_fieldset="False" 3696 is_linked_to_partial_fieldset="False" 3697 is_access_restriction_possible="False" 3698 is_constant_value="False" 3699 > 3700 <field_name>SET</field_name> 3701 <field_msb>12</field_msb> 3702 <field_lsb>11</field_lsb> 3703 <field_description order="before"> 3704 3705 <para>Synchronous Error Type. When the RAS Extension is implemented and DFSC is <binarynumber>0b010000</binarynumber>, describes the state of the PE after taking the Data Abort exception. The possible values of this field are:</para> 3706 3707 </field_description> 3708 <field_values> 3709 3710 3711 <field_value_instance> 3712 <field_value>0b00</field_value> 3713 <field_value_description> 3714 <para>Recoverable error (UER).</para> 3715</field_value_description> 3716 </field_value_instance> 3717 <field_value_instance> 3718 <field_value>0b10</field_value> 3719 <field_value_description> 3720 <para>Uncontainable error (UC).</para> 3721</field_value_description> 3722 </field_value_instance> 3723 <field_value_instance> 3724 <field_value>0b11</field_value> 3725 <field_value_description> 3726 <para>Restartable error (UEO) or Corrected error (CE).</para> 3727</field_value_description> 3728 </field_value_instance> 3729 </field_values> 3730 <field_description order="after"> 3731 3732 <para>All other values are reserved.</para> 3733<note><para>Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in an unrecoverable PE state.</para></note><para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para> 3734<list type="unordered"> 3735<listitem><content>The RAS Extension is not implemented.</content> 3736</listitem><listitem><content>The value returned in the DFSC field is not <binarynumber>0b010000</binarynumber>.</content> 3737</listitem></list> 3738 3739 </field_description> 3740 <field_resets> 3741 3742 <field_reset> 3743 3744 <field_reset_standard_text>U</field_reset_standard_text> 3745 3746 </field_reset> 3747</field_resets> 3748 </field> 3749 <field 3750 id="FnV_10_10" 3751 is_variable_length="False" 3752 has_partial_fieldset="False" 3753 is_linked_to_partial_fieldset="False" 3754 is_access_restriction_possible="False" 3755 is_constant_value="False" 3756 > 3757 <field_name>FnV</field_name> 3758 <field_msb>10</field_msb> 3759 <field_lsb>10</field_lsb> 3760 <field_description order="before"> 3761 3762 <para>FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.</para> 3763 3764 </field_description> 3765 <field_values> 3766 3767 3768 <field_value_instance> 3769 <field_value>0b0</field_value> 3770 <field_value_description> 3771 <para>FAR is valid.</para> 3772</field_value_description> 3773 </field_value_instance> 3774 <field_value_instance> 3775 <field_value>0b1</field_value> 3776 <field_value_description> 3777 <para>FAR is not valid, and holds an <arm-defined-word>UNKNOWN</arm-defined-word> value.</para> 3778</field_value_description> 3779 </field_value_instance> 3780 </field_values> 3781 <field_description order="after"> 3782 3783 <para>This field is valid only if the DFSC code is <binarynumber>0b010000</binarynumber>. It is <arm-defined-word>RES0</arm-defined-word> for all other aborts.</para> 3784 3785 </field_description> 3786 <field_resets> 3787 3788 <field_reset> 3789 3790 <field_reset_standard_text>U</field_reset_standard_text> 3791 3792 </field_reset> 3793</field_resets> 3794 </field> 3795 <field 3796 id="EA_9_9" 3797 is_variable_length="False" 3798 has_partial_fieldset="False" 3799 is_linked_to_partial_fieldset="False" 3800 is_access_restriction_possible="False" 3801 is_constant_value="False" 3802 > 3803 <field_name>EA</field_name> 3804 <field_msb>9</field_msb> 3805 <field_lsb>9</field_lsb> 3806 <field_description order="before"> 3807 3808 <para>External abort type. This bit can provide an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> classification of External aborts.</para> 3809<para>For any abort other than an External abort this bit returns a value of 0.</para> 3810 3811 </field_description> 3812 <field_values> 3813 3814 3815 </field_values> 3816 <field_resets> 3817 3818 <field_reset> 3819 3820 <field_reset_standard_text>U</field_reset_standard_text> 3821 3822 </field_reset> 3823</field_resets> 3824 </field> 3825 <field 3826 id="CM_8_8" 3827 is_variable_length="False" 3828 has_partial_fieldset="False" 3829 is_linked_to_partial_fieldset="False" 3830 is_access_restriction_possible="False" 3831 is_constant_value="False" 3832 > 3833 <field_name>CM</field_name> 3834 <field_msb>8</field_msb> 3835 <field_lsb>8</field_lsb> 3836 <field_description order="before"> 3837 3838 <para>Cache maintenance. Indicates whether the Data Abort came from a cache maintenance or address translation instruction:</para> 3839 3840 </field_description> 3841 <field_values> 3842 3843 3844 <field_value_instance> 3845 <field_value>0b0</field_value> 3846 <field_value_description> 3847 <para>The Data Abort was not generated by the execution of one of the System instructions identified in the description of value 1.</para> 3848</field_value_description> 3849 </field_value_instance> 3850 <field_value_instance> 3851 <field_value>0b1</field_value> 3852 <field_value_description> 3853 <para>The Data Abort was generated by either the execution of a cache maintenance instruction or by a synchronous fault on the execution of an address translation instruction. The <register_link id="AArch64-dc-zva.xml" state="AArch64">DC ZVA</register_link> instruction is not classified as a cache maintenance instruction, and therefore its execution cannot cause this field to be set to 1.</para> 3854</field_value_description> 3855 </field_value_instance> 3856 </field_values> 3857 <field_resets> 3858 3859 <field_reset> 3860 3861 <field_reset_standard_text>U</field_reset_standard_text> 3862 3863 </field_reset> 3864</field_resets> 3865 </field> 3866 <field 3867 id="S1PTW_7_7" 3868 is_variable_length="False" 3869 has_partial_fieldset="False" 3870 is_linked_to_partial_fieldset="False" 3871 is_access_restriction_possible="False" 3872 is_constant_value="False" 3873 > 3874 <field_name>S1PTW</field_name> 3875 <field_msb>7</field_msb> 3876 <field_lsb>7</field_lsb> 3877 <field_description order="before"> 3878 3879 <para>For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:</para> 3880 3881 </field_description> 3882 <field_values> 3883 3884 3885 <field_value_instance> 3886 <field_value>0b0</field_value> 3887 <field_value_description> 3888 <para>Fault not on a stage 2 translation for a stage 1 translation table walk.</para> 3889</field_value_description> 3890 </field_value_instance> 3891 <field_value_instance> 3892 <field_value>0b1</field_value> 3893 <field_value_description> 3894 <para>Fault on the stage 2 translation of an access for a stage 1 translation table walk.</para> 3895</field_value_description> 3896 </field_value_instance> 3897 </field_values> 3898 <field_description order="after"> 3899 3900 <para>For any abort other than a stage 2 fault this bit is <arm-defined-word>RES0</arm-defined-word>.</para> 3901 3902 </field_description> 3903 <field_resets> 3904 3905 <field_reset> 3906 3907 <field_reset_standard_text>U</field_reset_standard_text> 3908 3909 </field_reset> 3910</field_resets> 3911 </field> 3912 <field 3913 id="WnR_6_6" 3914 is_variable_length="False" 3915 has_partial_fieldset="False" 3916 is_linked_to_partial_fieldset="False" 3917 is_access_restriction_possible="False" 3918 is_constant_value="False" 3919 > 3920 <field_name>WnR</field_name> 3921 <field_msb>6</field_msb> 3922 <field_lsb>6</field_lsb> 3923 <field_description order="before"> 3924 3925 <para>Write not Read. Indicates whether a synchronous abort was caused by an instruction writing to a memory location, or by an instruction reading from a memory location. The possible values of this bit are:</para> 3926 3927 </field_description> 3928 <field_values> 3929 3930 3931 <field_value_instance> 3932 <field_value>0b0</field_value> 3933 <field_value_description> 3934 <para>Abort caused by an instruction reading from a memory location.</para> 3935</field_value_description> 3936 </field_value_instance> 3937 <field_value_instance> 3938 <field_value>0b1</field_value> 3939 <field_value_description> 3940 <para>Abort caused by an instruction writing to a memory location.</para> 3941</field_value_description> 3942 </field_value_instance> 3943 </field_values> 3944 <field_description order="after"> 3945 3946 <para>For faults on cache maintenance and address translation instructions, this bit always returns a value of 1.</para> 3947<para>For faults from an atomic instruction that both reads and writes from a memory location, this bit is set to 0 if a read of the address specified by the instruction would have generated the fault which is being reported, otherwise it is set to 1. The architecture permits, but does not require, a relaxation of this requirement such that for all stage 2 aborts on stage 1 translation table walks for atomic instructions, the WnR bit is always 0.</para> 3948<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> for:</para> 3949<list type="unordered"> 3950<listitem><content>An External abort on an Atomic access.</content> 3951</listitem><listitem><content>A fault reported using a DFSC value of <binarynumber>0b110101</binarynumber> or <binarynumber>0b110001</binarynumber>, indicating an unsupported Exclusive or atomic access.</content> 3952</listitem></list> 3953 3954 </field_description> 3955 <field_resets> 3956 3957 <field_reset> 3958 3959 <field_reset_standard_text>U</field_reset_standard_text> 3960 3961 </field_reset> 3962</field_resets> 3963 </field> 3964 <field 3965 id="DFSC_5_0" 3966 is_variable_length="False" 3967 has_partial_fieldset="False" 3968 is_linked_to_partial_fieldset="False" 3969 is_access_restriction_possible="False" 3970 is_constant_value="False" 3971 > 3972 <field_name>DFSC</field_name> 3973 <field_msb>5</field_msb> 3974 <field_lsb>0</field_lsb> 3975 <field_description order="before"> 3976 3977 <para>Data Fault Status Code. Possible values of this field are:</para> 3978 3979 </field_description> 3980 <field_values> 3981 3982 3983 <field_value_instance> 3984 <field_value>0b000000</field_value> 3985 <field_value_description> 3986 <para>Address size fault, level 0 of translation or translation table base register.</para> 3987</field_value_description> 3988 </field_value_instance> 3989 <field_value_instance> 3990 <field_value>0b000001</field_value> 3991 <field_value_description> 3992 <para>Address size fault, level 1.</para> 3993</field_value_description> 3994 </field_value_instance> 3995 <field_value_instance> 3996 <field_value>0b000010</field_value> 3997 <field_value_description> 3998 <para>Address size fault, level 2.</para> 3999</field_value_description> 4000 </field_value_instance> 4001 <field_value_instance> 4002 <field_value>0b000011</field_value> 4003 <field_value_description> 4004 <para>Address size fault, level 3.</para> 4005</field_value_description> 4006 </field_value_instance> 4007 <field_value_instance> 4008 <field_value>0b000100</field_value> 4009 <field_value_description> 4010 <para>Translation fault, level 0.</para> 4011</field_value_description> 4012 </field_value_instance> 4013 <field_value_instance> 4014 <field_value>0b000101</field_value> 4015 <field_value_description> 4016 <para>Translation fault, level 1.</para> 4017</field_value_description> 4018 </field_value_instance> 4019 <field_value_instance> 4020 <field_value>0b000110</field_value> 4021 <field_value_description> 4022 <para>Translation fault, level 2.</para> 4023</field_value_description> 4024 </field_value_instance> 4025 <field_value_instance> 4026 <field_value>0b000111</field_value> 4027 <field_value_description> 4028 <para>Translation fault, level 3.</para> 4029</field_value_description> 4030 </field_value_instance> 4031 <field_value_instance> 4032 <field_value>0b001001</field_value> 4033 <field_value_description> 4034 <para>Access flag fault, level 1.</para> 4035</field_value_description> 4036 </field_value_instance> 4037 <field_value_instance> 4038 <field_value>0b001010</field_value> 4039 <field_value_description> 4040 <para>Access flag fault, level 2.</para> 4041</field_value_description> 4042 </field_value_instance> 4043 <field_value_instance> 4044 <field_value>0b001011</field_value> 4045 <field_value_description> 4046 <para>Access flag fault, level 3.</para> 4047</field_value_description> 4048 </field_value_instance> 4049 <field_value_instance> 4050 <field_value>0b001101</field_value> 4051 <field_value_description> 4052 <para>Permission fault, level 1.</para> 4053</field_value_description> 4054 </field_value_instance> 4055 <field_value_instance> 4056 <field_value>0b001110</field_value> 4057 <field_value_description> 4058 <para>Permission fault, level 2.</para> 4059</field_value_description> 4060 </field_value_instance> 4061 <field_value_instance> 4062 <field_value>0b001111</field_value> 4063 <field_value_description> 4064 <para>Permission fault, level 3.</para> 4065</field_value_description> 4066 </field_value_instance> 4067 <field_value_instance> 4068 <field_value>0b010000</field_value> 4069 <field_value_description> 4070 <para>Synchronous External abort, not on translation table walk.</para> 4071</field_value_description> 4072 </field_value_instance> 4073 <field_value_instance> 4074 <field_value>0b010001</field_value> 4075 <field_value_description> 4076 <para>Synchronous Tag Check fail</para> 4077</field_value_description> 4078 </field_value_instance> 4079 <field_value_instance> 4080 <field_value>0b010100</field_value> 4081 <field_value_description> 4082 <para>Synchronous External abort, on translation table walk, level 0.</para> 4083</field_value_description> 4084 </field_value_instance> 4085 <field_value_instance> 4086 <field_value>0b010101</field_value> 4087 <field_value_description> 4088 <para>Synchronous External abort, on translation table walk, level 1.</para> 4089</field_value_description> 4090 </field_value_instance> 4091 <field_value_instance> 4092 <field_value>0b010110</field_value> 4093 <field_value_description> 4094 <para>Synchronous External abort, on translation table walk, level 2.</para> 4095</field_value_description> 4096 </field_value_instance> 4097 <field_value_instance> 4098 <field_value>0b010111</field_value> 4099 <field_value_description> 4100 <para>Synchronous External abort, on translation table walk, level 3.</para> 4101</field_value_description> 4102 </field_value_instance> 4103 <field_value_instance> 4104 <field_value>0b011000</field_value> 4105 <field_value_description> 4106 <para>Synchronous parity or ECC error on memory access, not on translation table walk.</para> 4107</field_value_description> 4108 </field_value_instance> 4109 <field_value_instance> 4110 <field_value>0b011100</field_value> 4111 <field_value_description> 4112 <para>Synchronous parity or ECC error on memory access on translation table walk, level 0.</para> 4113</field_value_description> 4114 </field_value_instance> 4115 <field_value_instance> 4116 <field_value>0b011101</field_value> 4117 <field_value_description> 4118 <para>Synchronous parity or ECC error on memory access on translation table walk, level 1.</para> 4119</field_value_description> 4120 </field_value_instance> 4121 <field_value_instance> 4122 <field_value>0b011110</field_value> 4123 <field_value_description> 4124 <para>Synchronous parity or ECC error on memory access on translation table walk, level 2.</para> 4125</field_value_description> 4126 </field_value_instance> 4127 <field_value_instance> 4128 <field_value>0b011111</field_value> 4129 <field_value_description> 4130 <para>Synchronous parity or ECC error on memory access on translation table walk, level 3.</para> 4131</field_value_description> 4132 </field_value_instance> 4133 <field_value_instance> 4134 <field_value>0b100001</field_value> 4135 <field_value_description> 4136 <para>Alignment fault.</para> 4137</field_value_description> 4138 </field_value_instance> 4139 <field_value_instance> 4140 <field_value>0b110000</field_value> 4141 <field_value_description> 4142 <para>TLB conflict abort.</para> 4143</field_value_description> 4144 </field_value_instance> 4145 <field_value_instance> 4146 <field_value>0b110001</field_value> 4147 <field_value_description> 4148 <para>Unsupported atomic hardware update fault, if the implementation includes <xref browsertext="ARMv8.1-TTHM]" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.1.TTHM"></xref>. Otherwise reserved.</para> 4149</field_value_description> 4150 </field_value_instance> 4151 <field_value_instance> 4152 <field_value>0b110100</field_value> 4153 <field_value_description> 4154 <para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> fault (Lockdown).</para> 4155</field_value_description> 4156 </field_value_instance> 4157 <field_value_instance> 4158 <field_value>0b110101</field_value> 4159 <field_value_description> 4160 <para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> fault (Unsupported Exclusive or Atomic access).</para> 4161</field_value_description> 4162 </field_value_instance> 4163 <field_value_instance> 4164 <field_value>0b111101</field_value> 4165 <field_value_description> 4166 <para>Section Domain Fault, used only for faults reported in the <register_link state="AArch64" id="AArch64-par_el1.xml">PAR_EL1</register_link>.</para> 4167</field_value_description> 4168 </field_value_instance> 4169 <field_value_instance> 4170 <field_value>0b111110</field_value> 4171 <field_value_description> 4172 <para>Page Domain Fault, used only for faults reported in the <register_link state="AArch64" id="AArch64-par_el1.xml">PAR_EL1</register_link>.</para> 4173</field_value_description> 4174 </field_value_instance> 4175 </field_values> 4176 <field_description order="after"> 4177 4178 <para>All other values are reserved.</para> 4179<para>When the RAS Extension is implemented, <binarynumber>0b011000</binarynumber>, <binarynumber>0b011100</binarynumber>, <binarynumber>0b011101</binarynumber>, <binarynumber>0b011110</binarynumber>, and <binarynumber>0b011111</binarynumber>, are reserved.</para> 4180<para>For more information about the lookup level associated with a fault, see <xref linkend="CACDHEEH" browsertext="'The level associated with MMU faults' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile"/>.</para> 4181<note><para>Because Access flag faults and Permission faults can only result from a Block or Page translation table descriptor, they cannot occur at level 0.</para></note><para>If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.</para> 4182 4183 </field_description> 4184 <field_resets> 4185 4186 <field_reset> 4187 4188 <field_reset_standard_text>U</field_reset_standard_text> 4189 4190 </field_reset> 4191</field_resets> 4192 </field> 4193 <text_after_fields> 4194 4195 4196 4197 </text_after_fields> 4198 </fields> 4199 <reg_fieldset length="25"> 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 <fieldat id="ISV_24_24" msb="24" lsb="24"/> 4231 <fieldat id="SAS_23_22" msb="23" lsb="22"/> 4232 <fieldat id="SSE_21_21" msb="21" lsb="21"/> 4233 <fieldat id="SRT_20_16" msb="20" lsb="16"/> 4234 <fieldat id="SF_15_15" msb="15" lsb="15"/> 4235 <fieldat id="AR_14_14" msb="14" lsb="14"/> 4236 <fieldat id="VNCR_13_13_1" msb="13" lsb="13"/> 4237 <fieldat id="SET_12_11" msb="12" lsb="11"/> 4238 <fieldat id="FnV_10_10" msb="10" lsb="10"/> 4239 <fieldat id="EA_9_9" msb="9" lsb="9"/> 4240 <fieldat id="CM_8_8" msb="8" lsb="8"/> 4241 <fieldat id="S1PTW_7_7" msb="7" lsb="7"/> 4242 <fieldat id="WnR_6_6" msb="6" lsb="6"/> 4243 <fieldat id="DFSC_5_0" msb="5" lsb="0"/> 4244 </reg_fieldset> 4245 </partial_fieldset> 4246 <partial_fieldset> 4247 <fields length="25"> 4248 <fields_instance>Exception from a trapped floating-point exception</fields_instance> 4249 <text_before_fields> 4250 4251 4252 4253 </text_before_fields> 4254 4255 <field 4256 id="0_24_24" 4257 is_variable_length="False" 4258 has_partial_fieldset="False" 4259 is_linked_to_partial_fieldset="False" 4260 is_access_restriction_possible="False" 4261 is_constant_value="False" 4262 rwtype="RES0" 4263 > 4264 <field_name>0</field_name> 4265 <field_msb>24</field_msb> 4266 <field_lsb>24</field_lsb> 4267 <field_description order="before"> 4268 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 4269 </field_description> 4270 <field_values> 4271 </field_values> 4272 </field> 4273 <field 4274 id="TFV_23_23" 4275 is_variable_length="False" 4276 has_partial_fieldset="False" 4277 is_linked_to_partial_fieldset="False" 4278 is_access_restriction_possible="False" 4279 is_constant_value="False" 4280 > 4281 <field_name>TFV</field_name> 4282 <field_msb>23</field_msb> 4283 <field_lsb>23</field_lsb> 4284 <field_description order="before"> 4285 4286 <para>Trapped Fault Valid bit. Indicates whether the IDF, IXF, UFF, OFF, DZF, and IOF bits hold valid information about trapped floating-point exceptions. The possible values of this bit are:</para> 4287 4288 </field_description> 4289 <field_values> 4290 4291 4292 <field_value_instance> 4293 <field_value>0b0</field_value> 4294 <field_value_description> 4295 <para>The IDF, IXF, UFF, OFF, DZF, and IOF bits do not hold valid information about trapped floating-point exceptions and are <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 4296</field_value_description> 4297 </field_value_instance> 4298 <field_value_instance> 4299 <field_value>0b1</field_value> 4300 <field_value_description> 4301 <para>One or more floating-point exceptions occurred during an operation performed while executing the reported instruction. The IDF, IXF, UFF, OFF, DZF, and IOF bits indicate trapped floating-point exceptions that occurred. For more information see <xref linkend="BEIJDDAG" browsertext="'Floating-point exception traps' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.13.4"/>.</para> 4302</field_value_description> 4303 </field_value_instance> 4304 </field_values> 4305 <field_description order="after"> 4306 4307 <para>It is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether this field is set to 0 on an exception generated by a trapped floating point exception from a vector instruction.</para> 4308<note><para>This is not a requirement. Implementations can set this field to 1 on a trapped floating-point exception from a vector instruction and return valid information in the {IDF, IXF, UFF, OFF, DZF, IOF} fields.</para></note> 4309 4310 </field_description> 4311 <field_resets> 4312 4313 <field_reset> 4314 4315 <field_reset_standard_text>U</field_reset_standard_text> 4316 4317 </field_reset> 4318</field_resets> 4319 </field> 4320 <field 4321 id="0_22_11" 4322 is_variable_length="False" 4323 has_partial_fieldset="False" 4324 is_linked_to_partial_fieldset="False" 4325 is_access_restriction_possible="False" 4326 is_constant_value="False" 4327 rwtype="RES0" 4328 > 4329 <field_name>0</field_name> 4330 <field_msb>22</field_msb> 4331 <field_lsb>11</field_lsb> 4332 <field_description order="before"> 4333 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 4334 </field_description> 4335 <field_values> 4336 </field_values> 4337 </field> 4338 <field 4339 id="VECITR_10_8" 4340 is_variable_length="False" 4341 has_partial_fieldset="False" 4342 is_linked_to_partial_fieldset="False" 4343 is_access_restriction_possible="False" 4344 is_constant_value="False" 4345 > 4346 <field_name>VECITR</field_name> 4347 <field_msb>10</field_msb> 4348 <field_lsb>8</field_lsb> 4349 <field_description order="before"> 4350 4351 <para>For a trapped floating-point exception from an instruction executed in AArch32 state this field is <arm-defined-word>RES1</arm-defined-word>.</para> 4352<para>For a trapped floating-point exception from an instruction executed in AArch64 state this field is <arm-defined-word>UNKNOWN</arm-defined-word>.</para> 4353 4354 </field_description> 4355 <field_values> 4356 4357 4358 </field_values> 4359 <field_resets> 4360 4361 <field_reset> 4362 4363 <field_reset_standard_text>U</field_reset_standard_text> 4364 4365 </field_reset> 4366</field_resets> 4367 </field> 4368 <field 4369 id="IDF_7_7" 4370 is_variable_length="False" 4371 has_partial_fieldset="False" 4372 is_linked_to_partial_fieldset="False" 4373 is_access_restriction_possible="False" 4374 is_constant_value="False" 4375 > 4376 <field_name>IDF</field_name> 4377 <field_msb>7</field_msb> 4378 <field_lsb>7</field_lsb> 4379 <field_description order="before"> 4380 4381 <para>Input Denormal floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para> 4382 4383 </field_description> 4384 <field_values> 4385 4386 4387 <field_value_instance> 4388 <field_value>0b0</field_value> 4389 <field_value_description> 4390 <para>Input denormal floating-point exception has not occurred.</para> 4391</field_value_description> 4392 </field_value_instance> 4393 <field_value_instance> 4394 <field_value>0b1</field_value> 4395 <field_value_description> 4396 <para>Input denormal floating-point exception occurred during execution of the reported instruction.</para> 4397</field_value_description> 4398 </field_value_instance> 4399 </field_values> 4400 <field_resets> 4401 4402 <field_reset> 4403 4404 <field_reset_standard_text>U</field_reset_standard_text> 4405 4406 </field_reset> 4407</field_resets> 4408 </field> 4409 <field 4410 id="0_6_5" 4411 is_variable_length="False" 4412 has_partial_fieldset="False" 4413 is_linked_to_partial_fieldset="False" 4414 is_access_restriction_possible="False" 4415 is_constant_value="False" 4416 rwtype="RES0" 4417 > 4418 <field_name>0</field_name> 4419 <field_msb>6</field_msb> 4420 <field_lsb>5</field_lsb> 4421 <field_description order="before"> 4422 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 4423 </field_description> 4424 <field_values> 4425 </field_values> 4426 </field> 4427 <field 4428 id="IXF_4_4" 4429 is_variable_length="False" 4430 has_partial_fieldset="False" 4431 is_linked_to_partial_fieldset="False" 4432 is_access_restriction_possible="False" 4433 is_constant_value="False" 4434 > 4435 <field_name>IXF</field_name> 4436 <field_msb>4</field_msb> 4437 <field_lsb>4</field_lsb> 4438 <field_description order="before"> 4439 4440 <para>Inexact floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para> 4441 4442 </field_description> 4443 <field_values> 4444 4445 4446 <field_value_instance> 4447 <field_value>0b0</field_value> 4448 <field_value_description> 4449 <para>Inexact floating-point exception has not occurred.</para> 4450</field_value_description> 4451 </field_value_instance> 4452 <field_value_instance> 4453 <field_value>0b1</field_value> 4454 <field_value_description> 4455 <para>Inexact floating-point exception occurred during execution of the reported instruction.</para> 4456</field_value_description> 4457 </field_value_instance> 4458 </field_values> 4459 <field_resets> 4460 4461 <field_reset> 4462 4463 <field_reset_standard_text>U</field_reset_standard_text> 4464 4465 </field_reset> 4466</field_resets> 4467 </field> 4468 <field 4469 id="UFF_3_3" 4470 is_variable_length="False" 4471 has_partial_fieldset="False" 4472 is_linked_to_partial_fieldset="False" 4473 is_access_restriction_possible="False" 4474 is_constant_value="False" 4475 > 4476 <field_name>UFF</field_name> 4477 <field_msb>3</field_msb> 4478 <field_lsb>3</field_lsb> 4479 <field_description order="before"> 4480 4481 <para>Underflow floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para> 4482 4483 </field_description> 4484 <field_values> 4485 4486 4487 <field_value_instance> 4488 <field_value>0b0</field_value> 4489 <field_value_description> 4490 <para>Underflow floating-point exception has not occurred.</para> 4491</field_value_description> 4492 </field_value_instance> 4493 <field_value_instance> 4494 <field_value>0b1</field_value> 4495 <field_value_description> 4496 <para>Underflow floating-point exception occurred during execution of the reported instruction.</para> 4497</field_value_description> 4498 </field_value_instance> 4499 </field_values> 4500 <field_resets> 4501 4502 <field_reset> 4503 4504 <field_reset_standard_text>U</field_reset_standard_text> 4505 4506 </field_reset> 4507</field_resets> 4508 </field> 4509 <field 4510 id="OFF_2_2" 4511 is_variable_length="False" 4512 has_partial_fieldset="False" 4513 is_linked_to_partial_fieldset="False" 4514 is_access_restriction_possible="False" 4515 is_constant_value="False" 4516 > 4517 <field_name>OFF</field_name> 4518 <field_msb>2</field_msb> 4519 <field_lsb>2</field_lsb> 4520 <field_description order="before"> 4521 4522 <para>Overflow floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para> 4523 4524 </field_description> 4525 <field_values> 4526 4527 4528 <field_value_instance> 4529 <field_value>0b0</field_value> 4530 <field_value_description> 4531 <para>Overflow floating-point exception has not occurred.</para> 4532</field_value_description> 4533 </field_value_instance> 4534 <field_value_instance> 4535 <field_value>0b1</field_value> 4536 <field_value_description> 4537 <para>Overflow floating-point exception occurred during execution of the reported instruction.</para> 4538</field_value_description> 4539 </field_value_instance> 4540 </field_values> 4541 <field_resets> 4542 4543 <field_reset> 4544 4545 <field_reset_standard_text>U</field_reset_standard_text> 4546 4547 </field_reset> 4548</field_resets> 4549 </field> 4550 <field 4551 id="DZF_1_1" 4552 is_variable_length="False" 4553 has_partial_fieldset="False" 4554 is_linked_to_partial_fieldset="False" 4555 is_access_restriction_possible="False" 4556 is_constant_value="False" 4557 > 4558 <field_name>DZF</field_name> 4559 <field_msb>1</field_msb> 4560 <field_lsb>1</field_lsb> 4561 <field_description order="before"> 4562 4563 <para>Divide by Zero floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para> 4564 4565 </field_description> 4566 <field_values> 4567 4568 4569 <field_value_instance> 4570 <field_value>0b0</field_value> 4571 <field_value_description> 4572 <para>Divide by Zero floating-point exception has not occurred.</para> 4573</field_value_description> 4574 </field_value_instance> 4575 <field_value_instance> 4576 <field_value>0b1</field_value> 4577 <field_value_description> 4578 <para>Divide by Zero floating-point exception occurred during execution of the reported instruction.</para> 4579</field_value_description> 4580 </field_value_instance> 4581 </field_values> 4582 <field_resets> 4583 4584 <field_reset> 4585 4586 <field_reset_standard_text>U</field_reset_standard_text> 4587 4588 </field_reset> 4589</field_resets> 4590 </field> 4591 <field 4592 id="IOF_0_0" 4593 is_variable_length="False" 4594 has_partial_fieldset="False" 4595 is_linked_to_partial_fieldset="False" 4596 is_access_restriction_possible="False" 4597 is_constant_value="False" 4598 > 4599 <field_name>IOF</field_name> 4600 <field_msb>0</field_msb> 4601 <field_lsb>0</field_lsb> 4602 <field_description order="before"> 4603 4604 <para>Invalid Operation floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para> 4605 4606 </field_description> 4607 <field_values> 4608 4609 4610 <field_value_instance> 4611 <field_value>0b0</field_value> 4612 <field_value_description> 4613 <para>Invalid Operation floating-point exception has not occurred.</para> 4614</field_value_description> 4615 </field_value_instance> 4616 <field_value_instance> 4617 <field_value>0b1</field_value> 4618 <field_value_description> 4619 <para>Invalid Operation floating-point exception occurred during execution of the reported instruction.</para> 4620</field_value_description> 4621 </field_value_instance> 4622 </field_values> 4623 <field_resets> 4624 4625 <field_reset> 4626 4627 <field_reset_standard_text>U</field_reset_standard_text> 4628 4629 </field_reset> 4630</field_resets> 4631 </field> 4632 <text_after_fields> 4633 4634 <para>In an implementation that supports the trapping of floating-point exceptions:</para> 4635<list type="unordered"> 4636<listitem><content>From an Exception level using AArch64, the <register_link state="AArch64" id="AArch64-fpcr.xml">FPCR</register_link>.{IDE, IXE, UFE, OFE, DZE, IOE} bits enable each of the floating-point exception traps.</content> 4637</listitem><listitem><content>From an Exception level using AArch32, the <register_link state="AArch32" id="AArch32-fpscr.xml">FPSCR</register_link>.{IDE, IXE, UFE, OFE, DZE, IOE} bits enable each of the floating-point exception traps.</content> 4638</listitem></list> 4639 4640 </text_after_fields> 4641 </fields> 4642 <reg_fieldset length="25"> 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 <fieldat id="0_24_24" msb="24" lsb="24"/> 4668 <fieldat id="TFV_23_23" msb="23" lsb="23"/> 4669 <fieldat id="0_22_11" msb="22" lsb="11"/> 4670 <fieldat id="VECITR_10_8" msb="10" lsb="8"/> 4671 <fieldat id="IDF_7_7" msb="7" lsb="7"/> 4672 <fieldat id="0_6_5" msb="6" lsb="5"/> 4673 <fieldat id="IXF_4_4" msb="4" lsb="4"/> 4674 <fieldat id="UFF_3_3" msb="3" lsb="3"/> 4675 <fieldat id="OFF_2_2" msb="2" lsb="2"/> 4676 <fieldat id="DZF_1_1" msb="1" lsb="1"/> 4677 <fieldat id="IOF_0_0" msb="0" lsb="0"/> 4678 </reg_fieldset> 4679 </partial_fieldset> 4680 <partial_fieldset> 4681 <fields length="25"> 4682 <fields_instance>SError interrupt</fields_instance> 4683 <text_before_fields> 4684 4685 4686 4687 </text_before_fields> 4688 4689 <field 4690 id="IDS_24_24" 4691 is_variable_length="False" 4692 has_partial_fieldset="False" 4693 is_linked_to_partial_fieldset="False" 4694 is_access_restriction_possible="False" 4695 is_constant_value="False" 4696 > 4697 <field_name>IDS</field_name> 4698 <field_msb>24</field_msb> 4699 <field_lsb>24</field_lsb> 4700 <field_description order="before"> 4701 4702 <para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> syndrome. Possible values of this bit are:</para> 4703 4704 </field_description> 4705 <field_values> 4706 4707 4708 <field_value_instance> 4709 <field_value>0b0</field_value> 4710 <field_value_description> 4711 <para>Bits[23:0] of the ISS field holds the fields described in this encoding.</para> 4712<note><para>If the RAS Extension is not implemented, this means that bits[23:0] of the ISS field are <arm-defined-word>RES0</arm-defined-word>.</para></note> 4713</field_value_description> 4714 </field_value_instance> 4715 <field_value_instance> 4716 <field_value>0b1</field_value> 4717 <field_value_description> 4718 <para>Bits[23:0] of the ISS field holds <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> syndrome information that can be used to provide additional information about the SError interrupt.</para> 4719</field_value_description> 4720 </field_value_instance> 4721 </field_values> 4722 <field_description order="after"> 4723 4724 <note><para>This field was previously called ISV.</para></note> 4725 4726 </field_description> 4727 <field_resets> 4728 4729 <field_reset> 4730 4731 <field_reset_standard_text>U</field_reset_standard_text> 4732 4733 </field_reset> 4734</field_resets> 4735 </field> 4736 <field 4737 id="0_23_14" 4738 is_variable_length="False" 4739 has_partial_fieldset="False" 4740 is_linked_to_partial_fieldset="False" 4741 is_access_restriction_possible="False" 4742 is_constant_value="False" 4743 rwtype="RES0" 4744 > 4745 <field_name>0</field_name> 4746 <field_msb>23</field_msb> 4747 <field_lsb>14</field_lsb> 4748 <field_description order="before"> 4749 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 4750 </field_description> 4751 <field_values> 4752 </field_values> 4753 </field> 4754 <field 4755 id="IESB_13_13_1" 4756 is_variable_length="False" 4757 has_partial_fieldset="False" 4758 is_linked_to_partial_fieldset="False" 4759 is_access_restriction_possible="False" 4760 is_constant_value="False" 4761 > 4762 <field_name>IESB</field_name> 4763 <field_msb>13</field_msb> 4764 <field_lsb>13</field_lsb> 4765 <field_description order="before"> 4766 4767 <para>Implicit error synchronization event.</para> 4768 4769 </field_description> 4770 <field_values> 4771 4772 4773 <field_value_instance> 4774 <field_value>0b0</field_value> 4775 <field_value_description> 4776 <para>The SError interrupt was either not synchronized by the implicit error synchronization event or not taken immediately.</para> 4777</field_value_description> 4778 </field_value_instance> 4779 <field_value_instance> 4780 <field_value>0b1</field_value> 4781 <field_value_description> 4782 <para>The SError interrupt was synchronized by the implicit error synchronization event and taken immediately.</para> 4783</field_value_description> 4784 </field_value_instance> 4785 </field_values> 4786 <field_description order="after"> 4787 4788 <para>This field is <arm-defined-word>RES0</arm-defined-word> if the value returned in the DFSC field is not <binarynumber>0b010001</binarynumber>.</para> 4789<note><para>Armv8.2 requires the implementation of the RAS Extension and <xref linkend="v8.2.IESB" browsertext="ARMv8.2-IESB" filename="A_introduction_to_the_armv8_architecture.fm"/>.</para></note> 4790 4791 </field_description> 4792 <field_resets> 4793 4794 <field_reset> 4795 4796 <field_reset_standard_text>U</field_reset_standard_text> 4797 4798 </field_reset> 4799</field_resets> 4800 <fields_condition>When ARMv8.2-IESB is implemented</fields_condition> 4801 </field> 4802 <field 4803 id="0_13_13_2" 4804 is_variable_length="False" 4805 has_partial_fieldset="False" 4806 is_linked_to_partial_fieldset="False" 4807 is_access_restriction_possible="False" 4808 is_constant_value="False" 4809 rwtype="RES0" 4810 > 4811 <field_name>0</field_name> 4812 <field_msb>13</field_msb> 4813 <field_lsb>13</field_lsb> 4814 <field_description order="before"> 4815 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 4816 </field_description> 4817 <field_values> 4818 </field_values> 4819 </field> 4820 <field 4821 id="AET_12_10" 4822 is_variable_length="False" 4823 has_partial_fieldset="False" 4824 is_linked_to_partial_fieldset="False" 4825 is_access_restriction_possible="False" 4826 is_constant_value="False" 4827 > 4828 <field_name>AET</field_name> 4829 <field_msb>12</field_msb> 4830 <field_lsb>10</field_lsb> 4831 <field_description order="before"> 4832 4833 <para>Asynchronous Error Type.</para> 4834<para>When the RAS Extension is implemented and DFSC is <binarynumber>0b010001</binarynumber>, describes the state of the PE after taking the SError interrupt exception. The possible values of this field are:</para> 4835 4836 </field_description> 4837 <field_values> 4838 4839 4840 <field_value_instance> 4841 <field_value>0b000</field_value> 4842 <field_value_description> 4843 <para>Uncontainable error (UC).</para> 4844</field_value_description> 4845 </field_value_instance> 4846 <field_value_instance> 4847 <field_value>0b001</field_value> 4848 <field_value_description> 4849 <para>Unrecoverable error (UEU).</para> 4850</field_value_description> 4851 </field_value_instance> 4852 <field_value_instance> 4853 <field_value>0b010</field_value> 4854 <field_value_description> 4855 <para>Restartable error (UEO).</para> 4856</field_value_description> 4857 </field_value_instance> 4858 <field_value_instance> 4859 <field_value>0b011</field_value> 4860 <field_value_description> 4861 <para>Recoverable error (UER).</para> 4862</field_value_description> 4863 </field_value_instance> 4864 <field_value_instance> 4865 <field_value>0b110</field_value> 4866 <field_value_description> 4867 <para>Corrected error (CE).</para> 4868</field_value_description> 4869 </field_value_instance> 4870 </field_values> 4871 <field_description order="after"> 4872 4873 <para>All other values are reserved.</para> 4874<para>If multiple errors are taken as a single SError interrupt exception, the overall state of the PE is reported. For example, if both a Recoverable and Unrecoverable error occurred, the state is Unrecoverable.</para> 4875<note><para>Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.</para></note><para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para> 4876<list type="unordered"> 4877<listitem><content>The RAS Extension is not implemented.</content> 4878</listitem><listitem><content>The value returned in the DFSC field is not <binarynumber>0b010001</binarynumber>.</content> 4879</listitem></list> 4880<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note> 4881 4882 </field_description> 4883 <field_resets> 4884 4885 <field_reset> 4886 4887 <field_reset_standard_text>U</field_reset_standard_text> 4888 4889 </field_reset> 4890</field_resets> 4891 </field> 4892 <field 4893 id="EA_9_9" 4894 is_variable_length="False" 4895 has_partial_fieldset="False" 4896 is_linked_to_partial_fieldset="False" 4897 is_access_restriction_possible="False" 4898 is_constant_value="False" 4899 > 4900 <field_name>EA</field_name> 4901 <field_msb>9</field_msb> 4902 <field_lsb>9</field_lsb> 4903 <field_description order="before"> 4904 4905 <para>External abort type. When the RAS Extension is implemented, this bit can provide an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> classification of External aborts.</para> 4906<para>For any abort other than an External abort this bit returns a value of 0.</para> 4907<para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para> 4908<list type="unordered"> 4909<listitem><content>The RAS Extension is not implemented.</content> 4910</listitem><listitem><content>The value returned in the DFSC field is not <binarynumber>0b010001</binarynumber>.</content> 4911</listitem></list> 4912<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note> 4913 4914 </field_description> 4915 <field_values> 4916 4917 4918 </field_values> 4919 <field_resets> 4920 4921 <field_reset> 4922 4923 <field_reset_standard_text>U</field_reset_standard_text> 4924 4925 </field_reset> 4926</field_resets> 4927 </field> 4928 <field 4929 id="0_8_6" 4930 is_variable_length="False" 4931 has_partial_fieldset="False" 4932 is_linked_to_partial_fieldset="False" 4933 is_access_restriction_possible="False" 4934 is_constant_value="False" 4935 rwtype="RES0" 4936 > 4937 <field_name>0</field_name> 4938 <field_msb>8</field_msb> 4939 <field_lsb>6</field_lsb> 4940 <field_description order="before"> 4941 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 4942 </field_description> 4943 <field_values> 4944 </field_values> 4945 </field> 4946 <field 4947 id="DFSC_5_0" 4948 is_variable_length="False" 4949 has_partial_fieldset="False" 4950 is_linked_to_partial_fieldset="False" 4951 is_access_restriction_possible="False" 4952 is_constant_value="False" 4953 > 4954 <field_name>DFSC</field_name> 4955 <field_msb>5</field_msb> 4956 <field_lsb>0</field_lsb> 4957 <field_description order="before"> 4958 4959 <para>Data Fault Status Code. When the RAS Extension is implemented, possible values of this field are:</para> 4960 4961 </field_description> 4962 <field_values> 4963 4964 4965 <field_value_instance> 4966 <field_value>0b000000</field_value> 4967 <field_value_description> 4968 <para>Uncategorized.</para> 4969</field_value_description> 4970 </field_value_instance> 4971 <field_value_instance> 4972 <field_value>0b010001</field_value> 4973 <field_value_description> 4974 <para>Asynchronous SError interrupt.</para> 4975</field_value_description> 4976 </field_value_instance> 4977 </field_values> 4978 <field_description order="after"> 4979 4980 <para>All other values are reserved.</para> 4981<para>If the RAS Extension is not implemented, this field is <arm-defined-word>RES0</arm-defined-word>.</para> 4982<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note> 4983 4984 </field_description> 4985 <field_resets> 4986 4987 <field_reset> 4988 4989 <field_reset_standard_text>U</field_reset_standard_text> 4990 4991 </field_reset> 4992</field_resets> 4993 </field> 4994 <text_after_fields> 4995 4996 4997 4998 </text_after_fields> 4999 </fields> 5000 <reg_fieldset length="25"> 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 <fieldat id="IDS_24_24" msb="24" lsb="24"/> 5018 <fieldat id="0_23_14" msb="23" lsb="14"/> 5019 <fieldat id="IESB_13_13_1" msb="13" lsb="13"/> 5020 <fieldat id="AET_12_10" msb="12" lsb="10"/> 5021 <fieldat id="EA_9_9" msb="9" lsb="9"/> 5022 <fieldat id="0_8_6" msb="8" lsb="6"/> 5023 <fieldat id="DFSC_5_0" msb="5" lsb="0"/> 5024 </reg_fieldset> 5025 </partial_fieldset> 5026 <partial_fieldset> 5027 <fields length="25"> 5028 <fields_instance>Exception from a Breakpoint or Vector Catch debug exception</fields_instance> 5029 <text_before_fields> 5030 5031 5032 5033 </text_before_fields> 5034 5035 <field 5036 id="0_24_6" 5037 is_variable_length="False" 5038 has_partial_fieldset="False" 5039 is_linked_to_partial_fieldset="False" 5040 is_access_restriction_possible="False" 5041 is_constant_value="False" 5042 rwtype="RES0" 5043 > 5044 <field_name>0</field_name> 5045 <field_msb>24</field_msb> 5046 <field_lsb>6</field_lsb> 5047 <field_description order="before"> 5048 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5049 </field_description> 5050 <field_values> 5051 </field_values> 5052 </field> 5053 <field 5054 id="IFSC_5_0" 5055 is_variable_length="False" 5056 has_partial_fieldset="False" 5057 is_linked_to_partial_fieldset="False" 5058 is_access_restriction_possible="False" 5059 is_constant_value="False" 5060 > 5061 <field_name>IFSC</field_name> 5062 <field_msb>5</field_msb> 5063 <field_lsb>0</field_lsb> 5064 <field_description order="before"> 5065 5066 <para>Instruction Fault Status Code. This field is set to <binarynumber>0b100010</binarynumber>, to indicate a Debug exception.</para> 5067 5068 </field_description> 5069 <field_values> 5070 5071 5072 </field_values> 5073 <field_resets> 5074 5075 <field_reset> 5076 5077 <field_reset_standard_text>U</field_reset_standard_text> 5078 5079 </field_reset> 5080</field_resets> 5081 </field> 5082 <text_after_fields> 5083 5084 <para>For more information about generating these exceptions:</para> 5085<list type="unordered"> 5086<listitem><content>For exceptions from AArch64, see <xref linkend="BCGGEABJ" browsertext="'Breakpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</content> 5087</listitem><listitem><content>For exceptions from AArch32, see <xref linkend="BGBDJAJB" browsertext="'Breakpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G2 (AArch32 Self-hosted Debug)" filename="G_aarch32_self_hosted_debug"/> and <xref linkend="G2BCGJGBCC" browsertext="'Vector Catch exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G2" filename="G_aarch32_self_hosted_debug"/>.</content> 5088</listitem></list> 5089 5090 </text_after_fields> 5091 </fields> 5092 <reg_fieldset length="25"> 5093 5094 5095 5096 5097 5098 5099 <fieldat id="0_24_6" msb="24" lsb="6"/> 5100 <fieldat id="IFSC_5_0" msb="5" lsb="0"/> 5101 </reg_fieldset> 5102 </partial_fieldset> 5103 <partial_fieldset> 5104 <fields length="25"> 5105 <fields_instance>Exception from a Software Step exception</fields_instance> 5106 <text_before_fields> 5107 5108 5109 5110 </text_before_fields> 5111 5112 <field 5113 id="ISV_24_24" 5114 is_variable_length="False" 5115 has_partial_fieldset="False" 5116 is_linked_to_partial_fieldset="False" 5117 is_access_restriction_possible="False" 5118 is_constant_value="False" 5119 > 5120 <field_name>ISV</field_name> 5121 <field_msb>24</field_msb> 5122 <field_lsb>24</field_lsb> 5123 <field_description order="before"> 5124 5125 <para>Instruction syndrome valid. Indicates whether the EX bit, ISS[6], is valid, as follows:</para> 5126 5127 </field_description> 5128 <field_values> 5129 5130 5131 <field_value_instance> 5132 <field_value>0b0</field_value> 5133 <field_value_description> 5134 <para>EX bit is <arm-defined-word>RES0</arm-defined-word>.</para> 5135</field_value_description> 5136 </field_value_instance> 5137 <field_value_instance> 5138 <field_value>0b1</field_value> 5139 <field_value_description> 5140 <para>EX bit is valid.</para> 5141</field_value_description> 5142 </field_value_instance> 5143 </field_values> 5144 <field_description order="after"> 5145 5146 <para>See the EX bit description for more information.</para> 5147 5148 </field_description> 5149 <field_resets> 5150 5151 <field_reset> 5152 5153 <field_reset_standard_text>U</field_reset_standard_text> 5154 5155 </field_reset> 5156</field_resets> 5157 </field> 5158 <field 5159 id="0_23_7" 5160 is_variable_length="False" 5161 has_partial_fieldset="False" 5162 is_linked_to_partial_fieldset="False" 5163 is_access_restriction_possible="False" 5164 is_constant_value="False" 5165 rwtype="RES0" 5166 > 5167 <field_name>0</field_name> 5168 <field_msb>23</field_msb> 5169 <field_lsb>7</field_lsb> 5170 <field_description order="before"> 5171 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5172 </field_description> 5173 <field_values> 5174 </field_values> 5175 </field> 5176 <field 5177 id="EX_6_6" 5178 is_variable_length="False" 5179 has_partial_fieldset="False" 5180 is_linked_to_partial_fieldset="False" 5181 is_access_restriction_possible="False" 5182 is_constant_value="False" 5183 > 5184 <field_name>EX</field_name> 5185 <field_msb>6</field_msb> 5186 <field_lsb>6</field_lsb> 5187 <field_description order="before"> 5188 5189 <para>Exclusive operation. If the ISV bit is set to 1, this bit indicates whether a Load-Exclusive instruction was stepped.</para> 5190 5191 </field_description> 5192 <field_values> 5193 5194 5195 <field_value_instance> 5196 <field_value>0b0</field_value> 5197 <field_value_description> 5198 <para>An instruction other than a Load-Exclusive instruction was stepped.</para> 5199</field_value_description> 5200 </field_value_instance> 5201 <field_value_instance> 5202 <field_value>0b1</field_value> 5203 <field_value_description> 5204 <para>A Load-Exclusive instruction was stepped.</para> 5205</field_value_description> 5206 </field_value_instance> 5207 </field_values> 5208 <field_description order="after"> 5209 5210 <para>If the ISV bit is set to 0, this bit is <arm-defined-word>RES0</arm-defined-word>, indicating no syndrome data is available.</para> 5211 5212 </field_description> 5213 <field_resets> 5214 5215 <field_reset> 5216 5217 <field_reset_standard_text>U</field_reset_standard_text> 5218 5219 </field_reset> 5220</field_resets> 5221 </field> 5222 <field 5223 id="IFSC_5_0" 5224 is_variable_length="False" 5225 has_partial_fieldset="False" 5226 is_linked_to_partial_fieldset="False" 5227 is_access_restriction_possible="False" 5228 is_constant_value="False" 5229 > 5230 <field_name>IFSC</field_name> 5231 <field_msb>5</field_msb> 5232 <field_lsb>0</field_lsb> 5233 <field_description order="before"> 5234 5235 <para>Instruction Fault Status Code. This field is set to <binarynumber>0b100010</binarynumber>, to indicate a Debug exception.</para> 5236 5237 </field_description> 5238 <field_values> 5239 5240 5241 </field_values> 5242 <field_resets> 5243 5244 <field_reset> 5245 5246 <field_reset_standard_text>U</field_reset_standard_text> 5247 5248 </field_reset> 5249</field_resets> 5250 </field> 5251 <text_after_fields> 5252 5253 <para>For more information about generating these exceptions, see <xref linkend="BCGIIDAJ" browsertext="'Software Step exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</para> 5254 5255 </text_after_fields> 5256 </fields> 5257 <reg_fieldset length="25"> 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 <fieldat id="ISV_24_24" msb="24" lsb="24"/> 5269 <fieldat id="0_23_7" msb="23" lsb="7"/> 5270 <fieldat id="EX_6_6" msb="6" lsb="6"/> 5271 <fieldat id="IFSC_5_0" msb="5" lsb="0"/> 5272 </reg_fieldset> 5273 </partial_fieldset> 5274 <partial_fieldset> 5275 <fields length="25"> 5276 <fields_instance>Exception from a Watchpoint exception</fields_instance> 5277 <text_before_fields> 5278 5279 5280 5281 </text_before_fields> 5282 5283 <field 5284 id="0_24_14" 5285 is_variable_length="False" 5286 has_partial_fieldset="False" 5287 is_linked_to_partial_fieldset="False" 5288 is_access_restriction_possible="False" 5289 is_constant_value="False" 5290 rwtype="RES0" 5291 > 5292 <field_name>0</field_name> 5293 <field_msb>24</field_msb> 5294 <field_lsb>14</field_lsb> 5295 <field_description order="before"> 5296 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5297 </field_description> 5298 <field_values> 5299 </field_values> 5300 </field> 5301 <field 5302 id="VNCR_13_13_1" 5303 is_variable_length="False" 5304 has_partial_fieldset="False" 5305 is_linked_to_partial_fieldset="False" 5306 is_access_restriction_possible="False" 5307 is_constant_value="False" 5308 > 5309 <field_name>VNCR</field_name> 5310 <field_msb>13</field_msb> 5311 <field_lsb>13</field_lsb> 5312 <field_description order="before"> 5313 5314 <para>Indicates that the watchpoint came from use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> register by EL1 code.</para> 5315 5316 </field_description> 5317 <field_values> 5318 5319 5320 <field_value_instance> 5321 <field_value>0b0</field_value> 5322 <field_value_description> 5323 <para>The watchpoint was not generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> by EL1 code.</para> 5324</field_value_description> 5325 </field_value_instance> 5326 <field_value_instance> 5327 <field_value>0b1</field_value> 5328 <field_value_description> 5329 <para>The watchpoint was generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> by EL1 code.</para> 5330</field_value_description> 5331 </field_value_instance> 5332 </field_values> 5333 <field_description order="after"> 5334 5335 <para>This field is 0 in ESR_EL1.</para> 5336 5337 </field_description> 5338 <field_resets> 5339 5340 <field_reset> 5341 5342 <field_reset_standard_text>U</field_reset_standard_text> 5343 5344 </field_reset> 5345</field_resets> 5346 <fields_condition>When ARMv8.4-NV is implemented</fields_condition> 5347 </field> 5348 <field 5349 id="0_13_13_2" 5350 is_variable_length="False" 5351 has_partial_fieldset="False" 5352 is_linked_to_partial_fieldset="False" 5353 is_access_restriction_possible="False" 5354 is_constant_value="False" 5355 rwtype="RES0" 5356 > 5357 <field_name>0</field_name> 5358 <field_msb>13</field_msb> 5359 <field_lsb>13</field_lsb> 5360 <field_description order="before"> 5361 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5362 </field_description> 5363 <field_values> 5364 </field_values> 5365 </field> 5366 <field 5367 id="0_12_9" 5368 is_variable_length="False" 5369 has_partial_fieldset="False" 5370 is_linked_to_partial_fieldset="False" 5371 is_access_restriction_possible="False" 5372 is_constant_value="False" 5373 rwtype="RES0" 5374 > 5375 <field_name>0</field_name> 5376 <field_msb>12</field_msb> 5377 <field_lsb>9</field_lsb> 5378 <field_description order="before"> 5379 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5380 </field_description> 5381 <field_values> 5382 </field_values> 5383 </field> 5384 <field 5385 id="CM_8_8" 5386 is_variable_length="False" 5387 has_partial_fieldset="False" 5388 is_linked_to_partial_fieldset="False" 5389 is_access_restriction_possible="False" 5390 is_constant_value="False" 5391 > 5392 <field_name>CM</field_name> 5393 <field_msb>8</field_msb> 5394 <field_lsb>8</field_lsb> 5395 <field_description order="before"> 5396 5397 <para>Cache maintenance. Indicates whether the Watchpoint exception came from a cache maintenance or address translation instruction:</para> 5398 5399 </field_description> 5400 <field_values> 5401 5402 5403 <field_value_instance> 5404 <field_value>0b0</field_value> 5405 <field_value_description> 5406 <para>The Watchpoint exception was not generated by the execution of one of the System instructions identified in the description of value 1.</para> 5407</field_value_description> 5408 </field_value_instance> 5409 <field_value_instance> 5410 <field_value>0b1</field_value> 5411 <field_value_description> 5412 <para>The Watchpoint exception was generated by either the execution of a cache maintenance instruction or by a synchronous Watchpoint exception on the execution of an address translation instruction. The <register_link id="AArch64-dc-zva.xml" state="AArch64">DC ZVA</register_link> instruction is not classified as a cache maintenance instruction, and therefore its execution cannot cause this field to be set to 1.</para> 5413</field_value_description> 5414 </field_value_instance> 5415 </field_values> 5416 <field_resets> 5417 5418 <field_reset> 5419 5420 <field_reset_standard_text>U</field_reset_standard_text> 5421 5422 </field_reset> 5423</field_resets> 5424 </field> 5425 <field 5426 id="0_7_7" 5427 is_variable_length="False" 5428 has_partial_fieldset="False" 5429 is_linked_to_partial_fieldset="False" 5430 is_access_restriction_possible="False" 5431 is_constant_value="False" 5432 rwtype="RES0" 5433 > 5434 <field_name>0</field_name> 5435 <field_msb>7</field_msb> 5436 <field_lsb>7</field_lsb> 5437 <field_description order="before"> 5438 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5439 </field_description> 5440 <field_values> 5441 </field_values> 5442 </field> 5443 <field 5444 id="WnR_6_6" 5445 is_variable_length="False" 5446 has_partial_fieldset="False" 5447 is_linked_to_partial_fieldset="False" 5448 is_access_restriction_possible="False" 5449 is_constant_value="False" 5450 > 5451 <field_name>WnR</field_name> 5452 <field_msb>6</field_msb> 5453 <field_lsb>6</field_lsb> 5454 <field_description order="before"> 5455 5456 <para>Write not Read. Indicates whether the Watchpoint exception was caused by an instruction writing to a memory location, or by an instruction reading from a memory location. The possible values of this bit are:</para> 5457 5458 </field_description> 5459 <field_values> 5460 5461 5462 <field_value_instance> 5463 <field_value>0b0</field_value> 5464 <field_value_description> 5465 <para>Watchpoint exception caused by an instruction reading from a memory location.</para> 5466</field_value_description> 5467 </field_value_instance> 5468 <field_value_instance> 5469 <field_value>0b1</field_value> 5470 <field_value_description> 5471 <para>Watchpoint exception caused by an instruction writing to a memory location.</para> 5472</field_value_description> 5473 </field_value_instance> 5474 </field_values> 5475 <field_description order="after"> 5476 5477 <para>For Watchpoint exceptions on cache maintenance and address translation instructions, this bit always returns a value of 1.</para> 5478<para>For Watchpoint exceptions from an atomic instruction, this field is set to 0 if a read of the location would have generated the Watchpoint exception, otherwise it is set to 1.</para> 5479<para>If multiple watchpoints match on the same access, it is <arm-defined-word>UNPREDICTABLE</arm-defined-word> which watchpoint generates the Watchpoint exception.</para> 5480 5481 </field_description> 5482 <field_resets> 5483 5484 <field_reset> 5485 5486 <field_reset_standard_text>U</field_reset_standard_text> 5487 5488 </field_reset> 5489</field_resets> 5490 </field> 5491 <field 5492 id="DFSC_5_0" 5493 is_variable_length="False" 5494 has_partial_fieldset="False" 5495 is_linked_to_partial_fieldset="False" 5496 is_access_restriction_possible="False" 5497 is_constant_value="False" 5498 > 5499 <field_name>DFSC</field_name> 5500 <field_msb>5</field_msb> 5501 <field_lsb>0</field_lsb> 5502 <field_description order="before"> 5503 5504 <para>Data Fault Status Code. This field is set to <binarynumber>0b100010</binarynumber>, to indicate a Debug exception.</para> 5505 5506 </field_description> 5507 <field_values> 5508 5509 5510 </field_values> 5511 <field_resets> 5512 5513 <field_reset> 5514 5515 <field_reset_standard_text>U</field_reset_standard_text> 5516 5517 </field_reset> 5518</field_resets> 5519 </field> 5520 <text_after_fields> 5521 5522 <para>For more information about generating these exceptions, see <xref linkend="BCGGECBJ" browsertext="'Watchpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</para> 5523 5524 </text_after_fields> 5525 </fields> 5526 <reg_fieldset length="25"> 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 <fieldat id="0_24_14" msb="24" lsb="14"/> 5544 <fieldat id="VNCR_13_13_1" msb="13" lsb="13"/> 5545 <fieldat id="0_12_9" msb="12" lsb="9"/> 5546 <fieldat id="CM_8_8" msb="8" lsb="8"/> 5547 <fieldat id="0_7_7" msb="7" lsb="7"/> 5548 <fieldat id="WnR_6_6" msb="6" lsb="6"/> 5549 <fieldat id="DFSC_5_0" msb="5" lsb="0"/> 5550 </reg_fieldset> 5551 </partial_fieldset> 5552 <partial_fieldset> 5553 <fields length="25"> 5554 <fields_instance>Exception from execution of a Breakpoint instruction</fields_instance> 5555 <text_before_fields> 5556 5557 5558 5559 </text_before_fields> 5560 5561 <field 5562 id="0_24_16" 5563 is_variable_length="False" 5564 has_partial_fieldset="False" 5565 is_linked_to_partial_fieldset="False" 5566 is_access_restriction_possible="False" 5567 is_constant_value="False" 5568 rwtype="RES0" 5569 > 5570 <field_name>0</field_name> 5571 <field_msb>24</field_msb> 5572 <field_lsb>16</field_lsb> 5573 <field_description order="before"> 5574 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5575 </field_description> 5576 <field_values> 5577 </field_values> 5578 </field> 5579 <field 5580 id="Comment_15_0" 5581 is_variable_length="False" 5582 has_partial_fieldset="False" 5583 is_linked_to_partial_fieldset="False" 5584 is_access_restriction_possible="False" 5585 is_constant_value="False" 5586 > 5587 <field_name>Comment</field_name> 5588 <field_msb>15</field_msb> 5589 <field_lsb>0</field_lsb> 5590 <field_description order="before"> 5591 5592 <para>Set to the instruction comment field value, zero extended as necessary. For the AArch32 BKPT instructions, the comment field is described as the immediate field.</para> 5593 5594 </field_description> 5595 <field_values> 5596 5597 5598 </field_values> 5599 <field_resets> 5600 5601 <field_reset> 5602 5603 <field_reset_standard_text>U</field_reset_standard_text> 5604 5605 </field_reset> 5606</field_resets> 5607 </field> 5608 <text_after_fields> 5609 5610 <para>For more information about generating these exceptions, see <xref linkend="BCGIEHAG" browsertext="'Breakpoint instruction exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</para> 5611 5612 </text_after_fields> 5613 </fields> 5614 <reg_fieldset length="25"> 5615 5616 5617 5618 5619 5620 5621 <fieldat id="0_24_16" msb="24" lsb="16"/> 5622 <fieldat id="Comment_15_0" msb="15" lsb="0"/> 5623 </reg_fieldset> 5624 </partial_fieldset> 5625 <partial_fieldset> 5626 <fields length="25"> 5627 <fields_condition>When ARMv8.3-NV is implemented</fields_condition> 5628 <fields_instance>Exception from ERET, ERETAA or ERETAB instruction</fields_instance> 5629 <text_before_fields> 5630 5631 <para>This EC value only applies when <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.NV is 1.</para> 5632 5633 </text_before_fields> 5634 5635 <field 5636 id="0_24_2" 5637 is_variable_length="False" 5638 has_partial_fieldset="False" 5639 is_linked_to_partial_fieldset="False" 5640 is_access_restriction_possible="False" 5641 is_constant_value="False" 5642 rwtype="RES0" 5643 > 5644 <field_name>0</field_name> 5645 <field_msb>24</field_msb> 5646 <field_lsb>2</field_lsb> 5647 <field_description order="before"> 5648 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5649 </field_description> 5650 <field_values> 5651 </field_values> 5652 </field> 5653 <field 5654 id="ERET_1_1" 5655 is_variable_length="False" 5656 has_partial_fieldset="False" 5657 is_linked_to_partial_fieldset="False" 5658 is_access_restriction_possible="False" 5659 is_constant_value="False" 5660 > 5661 <field_name>ERET</field_name> 5662 <field_msb>1</field_msb> 5663 <field_lsb>1</field_lsb> 5664 <field_description order="before"> 5665 5666 <para>Indicates whether an ERET or ERETA* instruction was trapped to EL2. Possible values are:</para> 5667 5668 </field_description> 5669 <field_values> 5670 5671 5672 <field_value_instance> 5673 <field_value>0b0</field_value> 5674 <field_value_description> 5675 <para>ERET instruction trapped to EL2.</para> 5676</field_value_description> 5677 </field_value_instance> 5678 <field_value_instance> 5679 <field_value>0b1</field_value> 5680 <field_value_description> 5681 <para>ERETAA or ERETAB instruction trapped to EL2.</para> 5682</field_value_description> 5683 </field_value_instance> 5684 </field_values> 5685 <field_description order="after"> 5686 5687 <para>If this bit is 0, the ERETA field is <arm-defined-word>RES0</arm-defined-word>.</para> 5688 5689 </field_description> 5690 <field_resets> 5691 5692 <field_reset> 5693 5694 <field_reset_standard_text>U</field_reset_standard_text> 5695 5696 </field_reset> 5697</field_resets> 5698 </field> 5699 <field 5700 id="ERETA_0_0" 5701 is_variable_length="False" 5702 has_partial_fieldset="False" 5703 is_linked_to_partial_fieldset="False" 5704 is_access_restriction_possible="False" 5705 is_constant_value="False" 5706 > 5707 <field_name>ERETA</field_name> 5708 <field_msb>0</field_msb> 5709 <field_lsb>0</field_lsb> 5710 <field_description order="before"> 5711 5712 <para>Indicates whether an ERETAA or ERETAB instruction was trapped to EL2. Possible values are:</para> 5713 5714 </field_description> 5715 <field_values> 5716 5717 5718 <field_value_instance> 5719 <field_value>0b0</field_value> 5720 <field_value_description> 5721 <para>ERETAA instruction trapped to EL2.</para> 5722</field_value_description> 5723 </field_value_instance> 5724 <field_value_instance> 5725 <field_value>0b1</field_value> 5726 <field_value_description> 5727 <para>ERETAB instruction trapped to EL2.</para> 5728</field_value_description> 5729 </field_value_instance> 5730 </field_values> 5731 <field_description order="after"> 5732 5733 <para>When the ERET field is 0, this bit is <arm-defined-word>RES0</arm-defined-word>.</para> 5734 5735 </field_description> 5736 <field_resets> 5737 5738 <field_reset> 5739 5740 <field_reset_standard_text>U</field_reset_standard_text> 5741 5742 </field_reset> 5743</field_resets> 5744 </field> 5745 <text_after_fields> 5746 5747 <para>For more information about generating these exceptions, see <xref linkend="CHDCFJDF" browsertext="'Traps to EL2 for Nested virtualization' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</para> 5748 5749 </text_after_fields> 5750 </fields> 5751 <reg_fieldset length="25"> 5752 <fields_condition>When ARMv8.3-NV is implemented</fields_condition> 5753 5754 5755 5756 5757 5758 5759 5760 5761 <fieldat id="0_24_2" msb="24" lsb="2"/> 5762 <fieldat id="ERET_1_1" msb="1" lsb="1"/> 5763 <fieldat id="ERETA_0_0" msb="0" lsb="0"/> 5764 </reg_fieldset> 5765 </partial_fieldset> 5766 <partial_fieldset> 5767 <fields length="25"> 5768 <fields_condition>When ARMv8.5-BTI is implemented</fields_condition> 5769 <fields_instance>Exception from Branch Target Identification instruction</fields_instance> 5770 <text_before_fields> 5771 5772 5773 5774 </text_before_fields> 5775 5776 <field 5777 id="0_24_2" 5778 is_variable_length="False" 5779 has_partial_fieldset="False" 5780 is_linked_to_partial_fieldset="False" 5781 is_access_restriction_possible="False" 5782 is_constant_value="False" 5783 rwtype="RES0" 5784 > 5785 <field_name>0</field_name> 5786 <field_msb>24</field_msb> 5787 <field_lsb>2</field_lsb> 5788 <field_description order="before"> 5789 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5790 </field_description> 5791 <field_values> 5792 </field_values> 5793 </field> 5794 <field 5795 id="BTYPE_1_0" 5796 is_variable_length="False" 5797 has_partial_fieldset="False" 5798 is_linked_to_partial_fieldset="False" 5799 is_access_restriction_possible="False" 5800 is_constant_value="False" 5801 > 5802 <field_name>BTYPE</field_name> 5803 <field_msb>1</field_msb> 5804 <field_lsb>0</field_lsb> 5805 <field_description order="before"> 5806 5807 <para>This field is set to the PSTATE.BTYPE value that generated the Branch Target Exception.</para> 5808 5809 </field_description> 5810 <field_values> 5811 5812 5813 </field_values> 5814 <field_resets> 5815 5816</field_resets> 5817 </field> 5818 <text_after_fields> 5819 5820 <para>For more information about generating these exceptions, see <xref browsertext="The AArch64 application level programmers' model' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section B1" filename="B_the_aarch64_application_level_programmers_model.fm" linkend="BEIBJCGI"></xref>.</para> 5821 5822 </text_after_fields> 5823 </fields> 5824 <reg_fieldset length="25"> 5825 <fields_condition>When ARMv8.5-BTI is implemented</fields_condition> 5826 5827 5828 5829 5830 5831 5832 <fieldat id="0_24_2" msb="24" lsb="2"/> 5833 <fieldat id="BTYPE_1_0" msb="1" lsb="0"/> 5834 </reg_fieldset> 5835 </partial_fieldset> 5836 <partial_fieldset> 5837 <fields length="25"> 5838 <fields_instance>Exception from a Pointer Authentication instruction when HCR_EL2.API == 0 || SCR_EL3.API == 0</fields_instance> 5839 <text_before_fields> 5840 5841 5842 5843 </text_before_fields> 5844 5845 <field 5846 id="0_24_0" 5847 is_variable_length="False" 5848 has_partial_fieldset="False" 5849 is_linked_to_partial_fieldset="False" 5850 is_access_restriction_possible="False" 5851 is_constant_value="False" 5852 rwtype="RES0" 5853 > 5854 <field_name>0</field_name> 5855 <field_msb>24</field_msb> 5856 <field_lsb>0</field_lsb> 5857 <field_description order="before"> 5858 <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para> 5859 </field_description> 5860 <field_values> 5861 </field_values> 5862 </field> 5863 <text_after_fields> 5864 5865 <para>For more information about generating these exceptions, see:</para> 5866<list type="unordered"> 5867<listitem><content><xref linkend="CHDGDDCJ" browsertext="'Trap to EL2 Non-secure EL0 accesses to Pointer authentication key registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 5868</listitem><listitem><content><xref linkend="CHDIGBED" browsertext="'Trap to EL3 accesses to Pointer authentication instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content> 5869</listitem></list> 5870 5871 </text_after_fields> 5872 </fields> 5873 <reg_fieldset length="25"> 5874 5875 5876 5877 5878 <fieldat id="0_24_0" msb="24" lsb="0"/> 5879 </reg_fieldset> 5880 </partial_fieldset> 5881 </field> 5882 <text_after_fields> 5883 5884 5885 5886 </text_after_fields> 5887 </fields> 5888 <reg_fieldset length="64"> 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 <fieldat id="0_63_32" msb="63" lsb="32"/> 5900 <fieldat id="EC_31_26" msb="31" lsb="26"/> 5901 <fieldat id="IL_25_25" msb="25" lsb="25"/> 5902 <fieldat id="ISS_24_0" msb="24" lsb="0"/> 5903 </reg_fieldset> 5904 5905 </reg_fieldsets> 5906 5907 5908 5909<access_mechanisms> 5910 5911 5912 <access_permission_text> 5913 <para>When <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ESR_EL1 or ESR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.</para> 5914 </access_permission_text> 5915 5916 5917 <access_mechanism accessor="MRS ESR_EL1"> 5918 <encoding> 5919 5920 <access_instruction>MRS <Xt>, ESR_EL1</access_instruction> 5921 5922 <enc n="op0" v="0b11"/> 5923 5924 <enc n="op1" v="0b000"/> 5925 5926 <enc n="CRn" v="0b0101"/> 5927 5928 <enc n="CRm" v="0b0010"/> 5929 5930 <enc n="op2" v="0b000"/> 5931 </encoding> 5932 <access_permission> 5933 <ps name="MRS" sections="1" secttype="access_permission"> 5934 <pstext> 5935if PSTATE.EL == EL0 then 5936 UNDEFINED; 5937elsif PSTATE.EL == EL1 then 5938 if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then 5939 AArch64.SystemAccessTrap(EL2, 0x18); 5940 elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then 5941 return NVMem[0x138]; 5942 else 5943 return ESR_EL1; 5944elsif PSTATE.EL == EL2 then 5945 if HCR_EL2.E2H == '1' then 5946 return ESR_EL2; 5947 else 5948 return ESR_EL1; 5949elsif PSTATE.EL == EL3 then 5950 return ESR_EL1; 5951 </pstext> 5952 </ps> 5953 </access_permission> 5954 </access_mechanism> 5955 <access_mechanism accessor="MSRregister ESR_EL1"> 5956 <encoding> 5957 5958 <access_instruction>MSR ESR_EL1, <Xt></access_instruction> 5959 5960 <enc n="op0" v="0b11"/> 5961 5962 <enc n="op1" v="0b000"/> 5963 5964 <enc n="CRn" v="0b0101"/> 5965 5966 <enc n="CRm" v="0b0010"/> 5967 5968 <enc n="op2" v="0b000"/> 5969 </encoding> 5970 <access_permission> 5971 <ps name="MSRregister" sections="1" secttype="access_permission"> 5972 <pstext> 5973if PSTATE.EL == EL0 then 5974 UNDEFINED; 5975elsif PSTATE.EL == EL1 then 5976 if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then 5977 AArch64.SystemAccessTrap(EL2, 0x18); 5978 elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then 5979 NVMem[0x138] = X[t]; 5980 else 5981 ESR_EL1 = X[t]; 5982elsif PSTATE.EL == EL2 then 5983 if HCR_EL2.E2H == '1' then 5984 ESR_EL2 = X[t]; 5985 else 5986 ESR_EL1 = X[t]; 5987elsif PSTATE.EL == EL3 then 5988 ESR_EL1 = X[t]; 5989 </pstext> 5990 </ps> 5991 </access_permission> 5992 </access_mechanism> 5993 <access_mechanism accessor="MRS ESR_EL12"> 5994 <encoding> 5995 5996 <access_instruction>MRS <Xt>, ESR_EL12</access_instruction> 5997 5998 <enc n="op0" v="0b11"/> 5999 6000 <enc n="op1" v="0b101"/> 6001 6002 <enc n="CRn" v="0b0101"/> 6003 6004 <enc n="CRm" v="0b0010"/> 6005 6006 <enc n="op2" v="0b000"/> 6007 </encoding> 6008 <access_permission> 6009 <ps name="MRS" sections="1" secttype="access_permission"> 6010 <pstext> 6011if PSTATE.EL == EL0 then 6012 UNDEFINED; 6013elsif PSTATE.EL == EL1 then 6014 if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then 6015 return NVMem[0x138]; 6016 elsif EL2Enabled() && HCR_EL2.NV == '1' then 6017 AArch64.SystemAccessTrap(EL2, 0x18); 6018 else 6019 UNDEFINED; 6020elsif PSTATE.EL == EL2 then 6021 if EL2Enabled() && HCR_EL2.E2H == '1' then 6022 return ESR_EL1; 6023 else 6024 UNDEFINED; 6025elsif PSTATE.EL == EL3 then 6026 if EL2Enabled() && HCR_EL2.E2H == '1' then 6027 return ESR_EL1; 6028 else 6029 UNDEFINED; 6030 </pstext> 6031 </ps> 6032 </access_permission> 6033 </access_mechanism> 6034 <access_mechanism accessor="MSRregister ESR_EL12"> 6035 <encoding> 6036 6037 <access_instruction>MSR ESR_EL12, <Xt></access_instruction> 6038 6039 <enc n="op0" v="0b11"/> 6040 6041 <enc n="op1" v="0b101"/> 6042 6043 <enc n="CRn" v="0b0101"/> 6044 6045 <enc n="CRm" v="0b0010"/> 6046 6047 <enc n="op2" v="0b000"/> 6048 </encoding> 6049 <access_permission> 6050 <ps name="MSRregister" sections="1" secttype="access_permission"> 6051 <pstext> 6052if PSTATE.EL == EL0 then 6053 UNDEFINED; 6054elsif PSTATE.EL == EL1 then 6055 if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then 6056 NVMem[0x138] = X[t]; 6057 elsif EL2Enabled() && HCR_EL2.NV == '1' then 6058 AArch64.SystemAccessTrap(EL2, 0x18); 6059 else 6060 UNDEFINED; 6061elsif PSTATE.EL == EL2 then 6062 if EL2Enabled() && HCR_EL2.E2H == '1' then 6063 ESR_EL1 = X[t]; 6064 else 6065 UNDEFINED; 6066elsif PSTATE.EL == EL3 then 6067 if EL2Enabled() && HCR_EL2.E2H == '1' then 6068 ESR_EL1 = X[t]; 6069 else 6070 UNDEFINED; 6071 </pstext> 6072 </ps> 6073 </access_permission> 6074 </access_mechanism> 6075 <access_mechanism accessor="MRS ESR_EL2"> 6076 <encoding> 6077 6078 <access_instruction>MRS <Xt>, ESR_EL2</access_instruction> 6079 6080 <enc n="op0" v="0b11"/> 6081 6082 <enc n="op1" v="0b100"/> 6083 6084 <enc n="CRn" v="0b0101"/> 6085 6086 <enc n="CRm" v="0b0010"/> 6087 6088 <enc n="op2" v="0b000"/> 6089 </encoding> 6090 <access_permission> 6091 <ps name="MRS" sections="1" secttype="access_permission"> 6092 <pstext> 6093if PSTATE.EL == EL0 then 6094 UNDEFINED; 6095elsif PSTATE.EL == EL1 then 6096 if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then 6097 return ESR_EL1; 6098 elsif EL2Enabled() && HCR_EL2.NV == '1' then 6099 AArch64.SystemAccessTrap(EL2, 0x18); 6100 else 6101 UNDEFINED; 6102elsif PSTATE.EL == EL2 then 6103 return ESR_EL2; 6104elsif PSTATE.EL == EL3 then 6105 return ESR_EL2; 6106 </pstext> 6107 </ps> 6108 </access_permission> 6109 </access_mechanism> 6110 <access_mechanism accessor="MSRregister ESR_EL2"> 6111 <encoding> 6112 6113 <access_instruction>MSR ESR_EL2, <Xt></access_instruction> 6114 6115 <enc n="op0" v="0b11"/> 6116 6117 <enc n="op1" v="0b100"/> 6118 6119 <enc n="CRn" v="0b0101"/> 6120 6121 <enc n="CRm" v="0b0010"/> 6122 6123 <enc n="op2" v="0b000"/> 6124 </encoding> 6125 <access_permission> 6126 <ps name="MSRregister" sections="1" secttype="access_permission"> 6127 <pstext> 6128if PSTATE.EL == EL0 then 6129 UNDEFINED; 6130elsif PSTATE.EL == EL1 then 6131 if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then 6132 ESR_EL1 = X[t]; 6133 elsif EL2Enabled() && HCR_EL2.NV == '1' then 6134 AArch64.SystemAccessTrap(EL2, 0x18); 6135 else 6136 UNDEFINED; 6137elsif PSTATE.EL == EL2 then 6138 ESR_EL2 = X[t]; 6139elsif PSTATE.EL == EL3 then 6140 ESR_EL2 = X[t]; 6141 </pstext> 6142 </ps> 6143 </access_permission> 6144 </access_mechanism> 6145</access_mechanisms> 6146 6147 <arch_variants> 6148 </arch_variants> 6149 </register> 6150</registers> 6151 6152 <timestamp>27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376</timestamp> 6153</register_page>