1*fdd8201dSApple OSS Distributions #pragma once 2*fdd8201dSApple OSS Distributions 3*fdd8201dSApple OSS Distributions #include <os/base.h> 4*fdd8201dSApple OSS Distributions #include <stdint.h> 5*fdd8201dSApple OSS Distributions 6*fdd8201dSApple OSS Distributions extern void save_restore_regs_entry(uint64_t arg) OS_NORETURN; 7*fdd8201dSApple OSS Distributions extern void save_restore_debug_regs_entry(uint64_t arg) OS_NORETURN; 8*fdd8201dSApple OSS Distributions extern void simple_real_mode_vcpu_entry(uint64_t arg) OS_NORETURN; 9*fdd8201dSApple OSS Distributions extern void simple_protected_mode_vcpu_entry(uint64_t arg) OS_NORETURN; 10*fdd8201dSApple OSS Distributions extern void simple_long_mode_vcpu_entry(uint64_t arg) OS_NORETURN; 11*fdd8201dSApple OSS Distributions extern void smp_vcpu_entry(uint64_t) OS_NORETURN; 12*fdd8201dSApple OSS Distributions extern void radar61961809_entry(uint64_t) OS_NORETURN; 13*fdd8201dSApple OSS Distributions extern void radar61961809_prepare(uint64_t) OS_NORETURN; 14*fdd8201dSApple OSS Distributions extern void radar61961809_loop64(uint64_t) OS_NORETURN; 15*fdd8201dSApple OSS Distributions extern void radar60691363_entry(uint64_t) OS_NORETURN; 16*fdd8201dSApple OSS Distributions extern void pio_entry(uint64_t) OS_NORETURN; 17*fdd8201dSApple OSS Distributions extern void pio_entry_basic(uint64_t) OS_NORETURN; 18*fdd8201dSApple OSS Distributions 19*fdd8201dSApple OSS Distributions #define MSR_IA32_STAR 0xc0000081 20*fdd8201dSApple OSS Distributions #define MSR_IA32_LSTAR 0xc0000082 21*fdd8201dSApple OSS Distributions #define MSR_IA32_CSTAR 0xc0000083 22*fdd8201dSApple OSS Distributions #define MSR_IA32_FMASK 0xc0000084 23*fdd8201dSApple OSS Distributions #define MSR_IA32_KERNEL_GS_BASE 0xc0000102 24*fdd8201dSApple OSS Distributions #define MSR_IA32_TSC 0x00000010 25*fdd8201dSApple OSS Distributions #define MSR_IA32_TSC_AUX 0xc0000103 26*fdd8201dSApple OSS Distributions 27*fdd8201dSApple OSS Distributions #define MSR_IA32_SYSENTER_CS 0x00000174 28*fdd8201dSApple OSS Distributions #define MSR_IA32_SYSENTER_ESP 0x00000175 29*fdd8201dSApple OSS Distributions #define MSR_IA32_SYSENTER_EIP 0x00000176 30*fdd8201dSApple OSS Distributions #define MSR_IA32_FS_BASE 0xc0000100 31*fdd8201dSApple OSS Distributions #define MSR_IA32_GS_BASE 0xc0000101 32*fdd8201dSApple OSS Distributions 33*fdd8201dSApple OSS Distributions extern void native_msr_vcpu_entry(uint64_t) OS_NORETURN; 34