1 /*
2 * Copyright (c) 2019 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /**
29 * On devices that support it, this test ensures that a mach exception is
30 * generated when an ARMv8 floating point exception is triggered.
31 * Also verifies that the main thread's FPCR value matches its expected default.
32 */
33 #include <darwintest.h>
34 #include <stdbool.h>
35 #include <stdint.h>
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <mach/mach.h>
39 #include <mach/thread_status.h>
40 #include <sys/sysctl.h>
41 #include <inttypes.h>
42
43 #include "exc_helpers.h"
44
45 T_GLOBAL_META(
46 T_META_RADAR_COMPONENT_NAME("xnu"),
47 T_META_RADAR_COMPONENT_VERSION("arm"),
48 T_META_OWNER("devon_andrade"),
49 T_META_RUN_CONCURRENTLY(true),
50 T_META_TAG_VM_NOT_ELIGIBLE);
51
52 #ifdef __arm64__
53
54 /* The bit to set in FPCR to enable the divide-by-zero floating point exception. */
55 #define FPCR_DIV_EXC 0x200
56 #define FPCR_INIT (0x0)
57
58 /* Whether we caught the EXC_ARITHMETIC mach exception or not. */
59 static volatile bool mach_exc_caught = false;
60
61 static size_t
exc_arithmetic_handler(__unused mach_port_t task,__unused mach_port_t thread,exception_type_t type,mach_exception_data_t codes_64,__unused uint64_t exception_pc)62 exc_arithmetic_handler(
63 __unused mach_port_t task,
64 __unused mach_port_t thread,
65 exception_type_t type,
66 mach_exception_data_t codes_64,
67 __unused uint64_t exception_pc)
68 {
69 /* Floating point divide by zero should cause an EXC_ARITHMETIC exception. */
70 T_ASSERT_EQ(type, EXC_ARITHMETIC, "Caught an EXC_ARITHMETIC exception");
71
72 /* Verify the exception is a floating point divide-by-zero exception. */
73 T_ASSERT_EQ(codes_64[0], (mach_exception_data_type_t)EXC_ARM_FP_DZ, "The subcode is EXC_ARM_FP_DZ (floating point divide-by-zero)");
74
75 mach_exc_caught = true;
76 return 4;
77 }
78
79 #define KERNEL_BOOTARGS_MAX_SIZE 1024
80 static char kernel_bootargs[KERNEL_BOOTARGS_MAX_SIZE];
81
82 #endif /* __arm64__ */
83
84 T_DECL(armv8_fp_exception,
85 "Test that ARMv8 floating point exceptions generate Mach exceptions, verify default FPCR value.")
86 {
87 #ifndef __arm64__
88 T_SKIP("Running on non-arm64 target, skipping...");
89 #else
90 mach_port_t exc_port = MACH_PORT_NULL;
91 size_t kernel_bootargs_len;
92
93 uint64_t fpcr = __builtin_arm_rsr64("FPCR");
94
95 if (fpcr != FPCR_INIT) {
96 T_FAIL("The floating point control register has a non-default value" "%" PRIx64, fpcr);
97 }
98
99 /* Attempt to enable Divide-by-Zero floating point exceptions in hardware. */
100 uint64_t fpcr_divexc = fpcr | FPCR_DIV_EXC;
101 __builtin_arm_wsr64("FPCR", fpcr_divexc);
102 #define DSB_ISH 0xb
103 __builtin_arm_dsb(DSB_ISH);
104
105 /* Devices that don't support floating point exceptions have FPCR as RAZ/WI. */
106 if (__builtin_arm_rsr64("FPCR") != fpcr_divexc) {
107 T_SKIP("Running on a device that doesn't support floating point exceptions, skipping...");
108 }
109
110 /* Check if floating-point exceptions are enabled */
111 kernel_bootargs_len = sizeof(kernel_bootargs);
112 kern_return_t kr = sysctlbyname("kern.bootargs", kernel_bootargs, &kernel_bootargs_len, NULL, 0);
113 if (kr != 0) {
114 T_SKIP("Could not get kernel bootargs, skipping...");
115 }
116
117 if (NULL == strstr(kernel_bootargs, "-fp_exceptions")) {
118 T_SKIP("Floating-point exceptions are disabled, skipping...");
119 }
120
121 /* Create the mach port the exception messages will be sent to. */
122 exc_port = create_exception_port(EXC_MASK_ARITHMETIC);
123 /* Spawn the exception server's thread. */
124 run_exception_handler(exc_port, exc_arithmetic_handler);
125
126 /**
127 * This should cause a floating point divide-by-zero exception to get triggered.
128 *
129 * The kernel shouldn't resume this thread until the mach exception is handled
130 * by the exception server that was just spawned. The exception handler will
131 * explicitly increment the PC += 4 to move to the next instruction.
132 */
133 float a = 6.5f;
134 float b = 0.0f;
135 __asm volatile ("fdiv %s0, %s1, %s2" : "=w" (a) : "w" (a), "w" (b));
136
137 if (mach_exc_caught) {
138 T_PASS("The expected floating point divide-by-zero exception was caught!");
139 } else {
140 T_FAIL("The floating point divide-by-zero exception was not captured :(");
141 }
142 #endif /* __arm64__ */
143 }
144