1 /*
2 * Copyright (c) 2017-2021 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 #include <arm/cpuid.h>
29 #include <arm/cpuid_internal.h>
30 #include <machine/atomic.h>
31 #include <machine/machine_cpuid.h>
32 #include <arm/cpu_data_internal.h>
33
34 static arm_mvfp_info_t cpuid_mvfp_info;
35 static arm_debug_info_t cpuid_debug_info;
36
37 uint32_t
machine_read_midr(void)38 machine_read_midr(void)
39 {
40 uint64_t midr;
41 __asm__ volatile ("mrs %0, MIDR_EL1" : "=r" (midr));
42
43 return (uint32_t)midr;
44 }
45
46 uint32_t
machine_read_clidr(void)47 machine_read_clidr(void)
48 {
49 uint64_t clidr;
50 __asm__ volatile ("mrs %0, CLIDR_EL1" : "=r" (clidr));
51
52 return (uint32_t)clidr;
53 }
54
55 uint32_t
machine_read_ccsidr(void)56 machine_read_ccsidr(void)
57 {
58 uint64_t ccsidr;
59 __asm__ volatile ("mrs %0, CCSIDR_EL1" : "=r" (ccsidr));
60
61 return (uint32_t)ccsidr;
62 }
63
64 void
machine_write_csselr(csselr_cache_level level,csselr_cache_type type)65 machine_write_csselr(csselr_cache_level level, csselr_cache_type type)
66 {
67 uint64_t csselr = (uint64_t)level | (uint64_t)type;
68 __asm__ volatile ("msr CSSELR_EL1, %0" : : "r" (csselr));
69
70 __builtin_arm_isb(ISB_SY);
71 }
72
73 void
machine_do_debugid(void)74 machine_do_debugid(void)
75 {
76 arm_cpuid_id_aa64dfr0_el1 id_dfr0;
77
78 /* read ID_AA64DFR0_EL1 */
79 __asm__ volatile ("mrs %0, ID_AA64DFR0_EL1" : "=r"(id_dfr0.value));
80
81 if (id_dfr0.debug_feature.debug_arch_version) {
82 cpuid_debug_info.num_watchpoint_pairs = id_dfr0.debug_feature.wrps + 1;
83 cpuid_debug_info.num_breakpoint_pairs = id_dfr0.debug_feature.brps + 1;
84 }
85 }
86
87 arm_debug_info_t *
machine_arm_debug_info(void)88 machine_arm_debug_info(void)
89 {
90 return &cpuid_debug_info;
91 }
92
93 void
machine_do_mvfpid()94 machine_do_mvfpid()
95 {
96 cpuid_mvfp_info.neon = 1;
97 cpuid_mvfp_info.neon_hpfp = 1;
98 #if defined(__ARM_ARCH_8_2__)
99 cpuid_mvfp_info.neon_fp16 = 1;
100 #endif /* defined(__ARM_ARCH_8_2__) */
101 }
102
103 arm_mvfp_info_t *
machine_arm_mvfp_info(void)104 machine_arm_mvfp_info(void)
105 {
106 return &cpuid_mvfp_info;
107 }
108