1 /* 2 * Copyright (c) 2007-2016 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 32 /* 33 * ARM CPU identification 34 */ 35 36 #ifndef _MACHINE_CPUID_H_ 37 #define _MACHINE_CPUID_H_ 38 39 #include <stdint.h> 40 #include <mach/boolean.h> 41 #include <machine/machine_cpuid.h> 42 #include <machine/machine_routines.h> 43 44 typedef struct { 45 uint32_t arm_rev : 4, /* 00:03 revision number */ 46 arm_part : 12,/* 04:15 primary part number */ 47 arm_arch : 4,/* 16:19 architecture */ 48 arm_variant : 4,/* 20:23 variant */ 49 arm_implementor : 8;/* 24:31 implementor (0x41) */ 50 } arm_cpuid_bits_t; 51 52 typedef union { 53 arm_cpuid_bits_t arm_info; /* ARM9xx, ARM11xx, and later processors */ 54 uint32_t value; 55 } arm_cpu_info_t; 56 57 /* Implementor codes */ 58 #define CPU_VID_ARM 0x41 // ARM Limited 59 #define CPU_VID_DEC 0x44 // Digital Equipment Corporation 60 #define CPU_VID_MOTOROLA 0x4D // Motorola - Freescale Semiconductor Inc. 61 #define CPU_VID_MARVELL 0x56 // Marvell Semiconductor Inc. 62 #define CPU_VID_INTEL 0x69 // Intel ARM parts. 63 #define CPU_VID_APPLE 0x61 // Apple Inc. 64 65 66 /* ARM Architecture Codes */ 67 68 #define CPU_ARCH_ARMv4 0x1 /* ARMv4 */ 69 #define CPU_ARCH_ARMv4T 0x2 /* ARMv4 + Thumb */ 70 #define CPU_ARCH_ARMv5 0x3 /* ARMv5 */ 71 #define CPU_ARCH_ARMv5T 0x4 /* ARMv5 + Thumb */ 72 #define CPU_ARCH_ARMv5TE 0x5 /* ARMv5 + Thumb + Extensions(?) */ 73 #define CPU_ARCH_ARMv5TEJ 0x6 /* ARMv5 + Thumb + Extensions(?) + //Jazelle(?) XXX */ 74 #define CPU_ARCH_ARMv6 0x7 /* ARMv6 */ 75 #define CPU_ARCH_ARMv7 0x8 /* ARMv7 */ 76 #define CPU_ARCH_ARMv7f 0x9 /* ARMv7 for Cortex A9 */ 77 #define CPU_ARCH_ARMv7s 0xa /* ARMv7 for Swift */ 78 #define CPU_ARCH_ARMv7k 0xb /* ARMv7 for Cortex A7 */ 79 80 #define CPU_ARCH_ARMv8 0xc /* Subtype for CPU_TYPE_ARM64 */ 81 82 #define CPU_ARCH_ARMv8E 0xd /* ARMv8.3a + Apple Private ISA Subtype for CPU_TYPE_ARM64 */ 83 84 /* special code indicating we need to look somewhere else for the architecture version */ 85 #define CPU_ARCH_EXTENDED 0xF 86 87 /* ARM Part Numbers */ 88 /* 89 * XXX: ARM Todo 90 * Fill out these part numbers more completely 91 */ 92 93 /* ARM9 (ARMv4T architecture) */ 94 #define CPU_PART_920T 0x920 95 #define CPU_PART_926EJS 0x926 /* ARM926EJ-S */ 96 97 /* ARM11 (ARMv6 architecture) */ 98 #define CPU_PART_1136JFS 0xB36 /* ARM1136JF-S or ARM1136J-S */ 99 #define CPU_PART_1176JZFS 0xB76 /* ARM1176JZF-S */ 100 101 /* G1 (ARMv7 architecture) */ 102 #define CPU_PART_CORTEXA5 0xC05 103 104 /* M7 (ARMv7 architecture) */ 105 #define CPU_PART_CORTEXA7 0xC07 106 107 /* H2 H3 (ARMv7 architecture) */ 108 #define CPU_PART_CORTEXA8 0xC08 109 110 /* H4 (ARMv7 architecture) */ 111 #define CPU_PART_CORTEXA9 0xC09 112 113 /* H7 (ARMv8 architecture) */ 114 #define CPU_PART_TYPHOON 0x2 115 116 /* H7G (ARMv8 architecture) */ 117 #define CPU_PART_TYPHOON_CAPRI 0x3 118 119 /* H8 (ARMv8 architecture) */ 120 #define CPU_PART_TWISTER 0x4 121 122 /* H8G H8M (ARMv8 architecture) */ 123 #define CPU_PART_TWISTER_ELBA_MALTA 0x5 124 125 /* H9 (ARMv8 architecture) */ 126 #define CPU_PART_HURRICANE 0x6 127 128 /* H9G (ARMv8 architecture) */ 129 #define CPU_PART_HURRICANE_MYST 0x7 130 131 /* H10 p-Core (ARMv8 architecture) */ 132 #define CPU_PART_MONSOON 0x8 133 134 /* H10 e-Core (ARMv8 architecture) */ 135 #define CPU_PART_MISTRAL 0x9 136 137 /* H11 p-Core (ARMv8 architecture) */ 138 #define CPU_PART_VORTEX 0xB 139 140 /* H11 e-Core (ARMv8 architecture) */ 141 #define CPU_PART_TEMPEST 0xC 142 143 /* M9 e-Core (ARMv8 architecture) */ 144 #define CPU_PART_TEMPEST_M9 0xF 145 146 /* H11G p-Core (ARMv8 architecture) */ 147 #define CPU_PART_VORTEX_ARUBA 0x10 148 149 /* H11G e-Core (ARMv8 architecture) */ 150 #define CPU_PART_TEMPEST_ARUBA 0x11 151 152 /* H12 p-Core (ARMv8 architecture) */ 153 #define CPU_PART_LIGHTNING 0x12 154 155 /* H12 e-Core (ARMv8 architecture) */ 156 #define CPU_PART_THUNDER 0x13 157 158 /* M10 e-Core (ARMv8 architecture) */ 159 #define CPU_PART_THUNDER_M10 0x26 160 161 /* H13 e-Core */ 162 #define CPU_PART_ICESTORM 0x20 163 164 /* H13 p-Core */ 165 #define CPU_PART_FIRESTORM 0x21 166 167 /* H13G e-Core */ 168 #define CPU_PART_ICESTORM_TONGA 0x22 169 170 /* H13G p-Core */ 171 #define CPU_PART_FIRESTORM_TONGA 0x23 172 173 /* H13J e-Core */ 174 #define CPU_PART_ICESTORM_JADE_CHOP 0x24 175 #define CPU_PART_ICESTORM_JADE_DIE 0x28 176 177 /* H13J p-Core */ 178 #define CPU_PART_FIRESTORM_JADE_CHOP 0x25 179 #define CPU_PART_FIRESTORM_JADE_DIE 0x29 180 181 /* H14 e-Core */ 182 #define CPU_PART_BLIZZARD 0x30 183 184 /* H14 p-Core */ 185 #define CPU_PART_AVALANCHE 0x31 186 187 /* H14G e-Core */ 188 #define CPU_PART_BLIZZARD_STATEN 0x32 189 190 /* H14G p-Core */ 191 #define CPU_PART_AVALANCHE_STATEN 0x33 192 193 /* H14S e-Core */ 194 #define CPU_PART_BLIZZARD_RHODES_CHOP 0x34 195 196 /* H14S p-Core */ 197 #define CPU_PART_AVALANCHE_RHODES_CHOP 0x35 198 199 /* H14C e-Core */ 200 #define CPU_PART_BLIZZARD_RHODES_DIE 0x38 201 202 /* H14C p-Core */ 203 #define CPU_PART_AVALANCHE_RHODES_DIE 0x39 204 205 /* H15 e-Core */ 206 #define CPU_PART_SAWTOOTH 0x40 207 208 /* H15 p-Core */ 209 #define CPU_PART_EVEREST 0x41 210 211 /* H15 Ibiza e-Core */ 212 #define CPU_PART_ECORE_IBIZA 0x42 213 214 /* H15 Ibiza p-Core */ 215 #define CPU_PART_PCORE_IBIZA 0x43 216 217 /* H15 Palma e-Core. */ 218 #define CPU_PART_ECORE_PALMA 0x48 219 220 /* H15 Palma p-Core. */ 221 #define CPU_PART_PCORE_PALMA 0x49 222 223 /* H15 Coll e-Core. */ 224 #define CPU_PART_ECORE_COLL 0x50 225 226 /* H15 Coll p-Core. */ 227 #define CPU_PART_PCORE_COLL 0x51 228 229 /* H15 Lobos e-Core. */ 230 #define CPU_PART_ECORE_LOBOS 0x44 231 232 /* H15 Lobos p-Core. */ 233 #define CPU_PART_PCORE_LOBOS 0x45 234 235 /* M11 e-Core */ 236 #define CPU_PART_SAWTOOTH_M11 0x46 237 238 /* H16G Donan e-Core. */ 239 #define CPU_PART_ECORE_DONAN 0x52 240 241 /* H16H Donan p-Core. */ 242 #define CPU_PART_PCORE_DONAN 0x53 243 244 /* H16S Brava S e-Core. */ 245 #define CPU_PART_ECORE_BRAVA_S 0x54 246 247 /* H16S Brava S p-Core. */ 248 #define CPU_PART_PCORE_BRAVA_S 0x55 249 250 /* H16C Brava C e-Core. */ 251 #define CPU_PART_ECORE_BRAVA_C 0x58 252 253 /* H16C Brava C p-Core. */ 254 #define CPU_PART_PCORE_BRAVA_C 0x59 255 256 257 258 259 260 /* Cache type identification */ 261 262 /* Supported Cache Types */ 263 typedef enum { 264 CACHE_WRITE_THROUGH, 265 CACHE_WRITE_BACK, 266 CACHE_READ_ALLOCATION, 267 CACHE_WRITE_ALLOCATION, 268 CACHE_UNKNOWN 269 } cache_type_t; 270 271 272 typedef struct { 273 boolean_t c_valid; /* has this cache info been populated? */ 274 boolean_t c_unified; /* unified I & D cache? */ 275 uint32_t c_isize; /* in Bytes (ARM caches can be 0.5 KB) */ 276 boolean_t c_i_ppage; /* protected page restriction for I cache 277 * (see B6-11 in ARM DDI 0100I document). */ 278 uint32_t c_dsize; /* in Bytes (ARM caches can be 0.5 KB) */ 279 boolean_t c_d_ppage; /* protected page restriction for I cache 280 * (see B6-11 in ARM DDI 0100I document). */ 281 cache_type_t c_type; /* WB or WT */ 282 uint32_t c_linesz; /* number of bytes */ 283 uint32_t c_assoc; /* n-way associativity */ 284 uint32_t c_l2size; /* L2 size, if present */ 285 uint32_t c_bulksize_op; /* bulk operation size limit. 0 if disabled */ 286 uint32_t c_inner_cache_size; /* inner dache size */ 287 288 } cache_info_t; 289 290 typedef struct { 291 uint32_t 292 RB:4, /* 3:0 - 32x64-bit media register bank supported: 0x2 */ 293 SP:4, /* 7:4 - Single precision supported in VFPv3: 0x2 */ 294 DP:4, /* 8:11 - Double precision supported in VFPv3: 0x2 */ 295 TE:4, /* 12-15 - Only untrapped exception handling can be selected: 0x0 */ 296 D:4, /* 19:16 - VFP hardware divide supported: 0x1 */ 297 SR:4, /* 23:20 - VFP hardware square root supported: 0x1 */ 298 SV:4, /* 27:24 - VFP short vector supported: 0x1 */ 299 RM:4; /* 31:28 - All VFP rounding modes supported: 0x1 */ 300 } arm_mvfr0_t; 301 302 typedef union { 303 arm_mvfr0_t bits; 304 uint32_t value; 305 } arm_mvfr0_info_t; 306 307 typedef struct { 308 uint32_t 309 FZ:4, /* 3:0 - Full denormal arithmetic supported for VFP: 0x1 */ 310 DN:4, /* 7:4 - Propagation of NaN values supported for VFP: 0x1 */ 311 LS:4, /* 11:8 - Load/store instructions supported for NEON: 0x1 */ 312 I:4, /* 15:12 - Integer instructions supported for NEON: 0x1 */ 313 SP:4, /* 19:16 - Single precision floating-point instructions supported for NEON: 0x1 */ 314 HPFP:4, /* 23:20 - Half precision floating-point instructions supported */ 315 RSVP:8; /* 31:24 - Reserved */ 316 } arm_mvfr1_t; 317 318 typedef union { 319 arm_mvfr1_t bits; 320 uint32_t value; 321 } arm_mvfr1_info_t; 322 323 typedef struct { 324 uint32_t neon; 325 uint32_t neon_hpfp; 326 uint32_t neon_fp16; 327 } arm_mvfp_info_t; 328 329 #ifdef __cplusplus 330 extern "C" { 331 #endif /* __cplusplus */ 332 333 extern void do_cpuid(void); 334 extern arm_cpu_info_t *cpuid_info(void); 335 extern int cpuid_get_cpufamily(void); 336 extern int cpuid_get_cpusubfamily(void); 337 338 extern void do_debugid(void); 339 extern arm_debug_info_t *arm_debug_info(void); 340 341 extern void do_cacheid(void); 342 extern cache_info_t *cache_info(void); 343 extern cache_info_t *cache_info_type(cluster_type_t cluster_type); 344 345 extern void do_mvfpid(void); 346 extern arm_mvfp_info_t *arm_mvfp_info(void); 347 348 #ifdef __cplusplus 349 } 350 #endif /* __cplusplus */ 351 352 #endif // _MACHINE_CPUID_H_ 353