1 /*
2 * Copyright (c) 2012-2023 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 #include <arm/caches_internal.h>
30 #include <arm/cpu_data.h>
31 #include <arm/cpu_data_internal.h>
32 #include <arm/misc_protos.h>
33 #include <arm/thread.h>
34 #include <arm/rtclock.h>
35 #include <arm/trap_internal.h> /* for IS_ARM_GDB_TRAP() et al */
36 #include <arm64/proc_reg.h>
37 #include <arm64/machine_machdep.h>
38 #include <arm64/monotonic.h>
39 #include <arm64/instructions.h>
40
41 #include <kern/debug.h>
42 #include <kern/restartable.h>
43 #include <kern/socd_client.h>
44 #include <kern/task.h>
45 #include <kern/thread.h>
46 #include <kern/zalloc_internal.h>
47 #include <mach/exception.h>
48 #include <mach/arm/traps.h>
49 #include <mach/vm_types.h>
50 #include <mach/machine/thread_status.h>
51
52 #include <machine/atomic.h>
53 #include <machine/limits.h>
54
55 #include <pexpert/arm/protos.h>
56 #include <pexpert/arm64/apple_arm64_cpu.h>
57 #include <pexpert/arm64/apple_arm64_regs.h>
58 #include <pexpert/arm64/board_config.h>
59
60 #include <vm/vm_page.h>
61 #include <vm/pmap.h>
62 #include <vm/vm_fault.h>
63 #include <vm/vm_kern.h>
64 #include <vm/vm_map_xnu.h>
65
66 #include <sys/errno.h>
67 #include <sys/kdebug.h>
68 #include <sys/code_signing.h>
69 #include <sys/reason.h>
70 #include <kperf/kperf.h>
71
72 #include <kern/policy_internal.h>
73 #if CONFIG_TELEMETRY
74 #include <kern/telemetry.h>
75 #endif
76
77 #include <prng/entropy.h>
78
79
80
81
82 #include <arm64/platform_error_handler.h>
83
84 #if KASAN_TBI
85 #include <san/kasan.h>
86 #endif /* KASAN_TBI */
87
88 #if CONFIG_UBSAN_MINIMAL
89 #include <san/ubsan_minimal.h>
90 #endif
91
92
93 #ifdef CONFIG_BTI_TELEMETRY
94 #include <arm64/bti_telemetry.h>
95 #endif /* CONFIG_BTI_TELEMETRY */
96
97 #ifndef __arm64__
98 #error Should only be compiling for arm64.
99 #endif
100
101 #if DEBUG || DEVELOPMENT
102 #define HAS_TELEMETRY_KERNEL_BRK 1
103 #endif
104
105
106 #define TEST_CONTEXT32_SANITY(context) \
107 (context->ss.ash.flavor == ARM_SAVED_STATE32 && context->ss.ash.count == ARM_SAVED_STATE32_COUNT && \
108 context->ns.nsh.flavor == ARM_NEON_SAVED_STATE32 && context->ns.nsh.count == ARM_NEON_SAVED_STATE32_COUNT)
109
110 #define TEST_CONTEXT64_SANITY(context) \
111 (context->ss.ash.flavor == ARM_SAVED_STATE64 && context->ss.ash.count == ARM_SAVED_STATE64_COUNT && \
112 context->ns.nsh.flavor == ARM_NEON_SAVED_STATE64 && context->ns.nsh.count == ARM_NEON_SAVED_STATE64_COUNT)
113
114 #define ASSERT_CONTEXT_SANITY(context) \
115 assert(TEST_CONTEXT32_SANITY(context) || TEST_CONTEXT64_SANITY(context))
116
117
118 #define COPYIN(src, dst, size) \
119 (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) ? \
120 copyin_kern(src, dst, size) : \
121 copyin(src, dst, size)
122
123 #define COPYOUT(src, dst, size) \
124 (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) ? \
125 copyout_kern(src, dst, size) : \
126 copyout(src, dst, size)
127
128 // Below is for concatenating a string param to a string literal
129 #define STR1(x) #x
130 #define STR(x) STR1(x)
131
132 #define ARM64_KDBG_CODE_KERNEL (0 << 8)
133 #define ARM64_KDBG_CODE_USER (1 << 8)
134 #define ARM64_KDBG_CODE_GUEST (2 << 8)
135
136 _Static_assert(ARM64_KDBG_CODE_GUEST <= KDBG_CODE_MAX, "arm64 KDBG trace codes out of range");
137 _Static_assert(ARM64_KDBG_CODE_GUEST <= UINT16_MAX, "arm64 KDBG trace codes out of range");
138
139 void panic_with_thread_kernel_state(const char *msg, arm_saved_state_t *ss) __abortlike;
140
141 void sleh_synchronous_sp1(arm_context_t *, uint64_t, vm_offset_t) __abortlike;
142 void sleh_synchronous(arm_context_t *, uint64_t, vm_offset_t, bool);
143
144
145
146 void sleh_irq(arm_saved_state_t *);
147 void sleh_fiq(arm_saved_state_t *);
148 void sleh_serror(arm_context_t *context, uint64_t esr, vm_offset_t far);
149 void sleh_invalid_stack(arm_context_t *context, uint64_t esr, vm_offset_t far) __dead2;
150
151 static void sleh_interrupt_handler_prologue(arm_saved_state_t *, unsigned int type);
152 static void sleh_interrupt_handler_epilogue(void);
153
154 static void handle_svc(arm_saved_state_t *);
155 static void handle_mach_absolute_time_trap(arm_saved_state_t *);
156 static void handle_mach_continuous_time_trap(arm_saved_state_t *);
157
158 static void handle_msr_trap(arm_saved_state_t *state, uint64_t esr);
159 #if __has_feature(ptrauth_calls)
160 static void handle_pac_fail(arm_saved_state_t *state, uint64_t esr) __dead2;
161 static inline uint64_t fault_addr_bitmask(unsigned int bit_from, unsigned int bit_to);
162 #endif
163 static void handle_bti_fail(arm_saved_state_t *state, uint64_t esr);
164 extern kern_return_t arm_fast_fault(pmap_t, vm_map_address_t, vm_prot_t, bool, bool);
165
166 static void handle_uncategorized(arm_saved_state_t *);
167
168 static void handle_kernel_breakpoint(arm_saved_state_t *, uint64_t);
169
170 static void handle_breakpoint(arm_saved_state_t *, uint64_t) __dead2;
171
172 typedef void (*abort_inspector_t)(uint32_t, fault_status_t *, vm_prot_t *);
173 static void inspect_instruction_abort(uint32_t, fault_status_t *, vm_prot_t *);
174 static void inspect_data_abort(uint32_t, fault_status_t *, vm_prot_t *);
175
176 static int is_vm_fault(fault_status_t);
177 static int is_translation_fault(fault_status_t);
178 static int is_alignment_fault(fault_status_t);
179
180 typedef void (*abort_handler_t)(arm_saved_state_t *, uint64_t, vm_offset_t, fault_status_t, vm_prot_t, expected_fault_handler_t);
181 static void handle_user_abort(arm_saved_state_t *, uint64_t, vm_offset_t, fault_status_t, vm_prot_t, expected_fault_handler_t);
182 static void handle_kernel_abort(arm_saved_state_t *, uint64_t, vm_offset_t, fault_status_t, vm_prot_t, expected_fault_handler_t);
183
184 static void handle_pc_align(arm_saved_state_t *ss) __dead2;
185 static void handle_sp_align(arm_saved_state_t *ss) __dead2;
186 static void handle_sw_step_debug(arm_saved_state_t *ss) __dead2;
187 static void handle_wf_trap(arm_saved_state_t *ss) __dead2;
188 static void handle_fp_trap(arm_saved_state_t *ss, uint64_t esr) __dead2;
189 #if HAS_ARM_FEAT_SME
190 static void handle_sme_trap(arm_saved_state_t *state, uint64_t esr);
191 #endif /* HAS_ARM_FEAT_SME */
192
193 static void handle_watchpoint(vm_offset_t fault_addr) __dead2;
194
195 static void handle_abort(arm_saved_state_t *, uint64_t, vm_offset_t, abort_inspector_t, abort_handler_t, expected_fault_handler_t);
196
197 static void handle_user_trapped_instruction32(arm_saved_state_t *, uint64_t esr) __dead2;
198
199 static void handle_simd_trap(arm_saved_state_t *, uint64_t esr) __dead2;
200
201 extern void current_cached_proc_cred_update(void);
202 void mach_syscall_trace_exit(unsigned int retval, unsigned int call_number);
203
204 struct proc;
205
206 typedef uint32_t arm64_instr_t;
207
208 extern void
209 unix_syscall(struct arm_saved_state * regs, thread_t thread_act, struct proc * proc);
210
211 extern void
212 mach_syscall(struct arm_saved_state*);
213
214 #if CONFIG_DTRACE
215 extern kern_return_t dtrace_user_probe(arm_saved_state_t* regs);
216 extern boolean_t dtrace_tally_fault(user_addr_t);
217
218 /*
219 * Traps for userland processing. Can't include bsd/sys/fasttrap_isa.h, so copy
220 * and paste the trap instructions
221 * over from that file. Need to keep these in sync!
222 */
223 #define FASTTRAP_ARM32_INSTR 0xe7ffdefc
224 #define FASTTRAP_THUMB32_INSTR 0xdefc
225 #define FASTTRAP_ARM64_INSTR 0xe7eeee7e
226
227 #define FASTTRAP_ARM32_RET_INSTR 0xe7ffdefb
228 #define FASTTRAP_THUMB32_RET_INSTR 0xdefb
229 #define FASTTRAP_ARM64_RET_INSTR 0xe7eeee7d
230
231 /* See <rdar://problem/4613924> */
232 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
233 #endif
234
235
236
237 extern void arm64_thread_exception_return(void) __dead2;
238
239 #if defined(APPLETYPHOON)
240 #define CPU_NAME "Typhoon"
241 #elif defined(APPLETWISTER)
242 #define CPU_NAME "Twister"
243 #elif defined(APPLEHURRICANE)
244 #define CPU_NAME "Hurricane"
245 #elif defined(APPLELIGHTNING)
246 #define CPU_NAME "Lightning"
247 #elif defined(APPLEEVEREST)
248 #define CPU_NAME "Everest"
249 #elif defined(APPLEH16)
250 #define CPU_NAME "AppleH16"
251 #else
252 #define CPU_NAME "Unknown"
253 #endif
254
255 #if (CONFIG_KERNEL_INTEGRITY && defined(KERNEL_INTEGRITY_WT))
256 #define ESR_WT_SERROR(esr) (((esr) & 0xffffff00) == 0xbf575400)
257 #define ESR_WT_REASON(esr) ((esr) & 0xff)
258
259 #define WT_REASON_NONE 0
260 #define WT_REASON_INTEGRITY_FAIL 1
261 #define WT_REASON_BAD_SYSCALL 2
262 #define WT_REASON_NOT_LOCKED 3
263 #define WT_REASON_ALREADY_LOCKED 4
264 #define WT_REASON_SW_REQ 5
265 #define WT_REASON_PT_INVALID 6
266 #define WT_REASON_PT_VIOLATION 7
267 #define WT_REASON_REG_VIOLATION 8
268 #endif
269
270 #if defined(HAS_IPI)
271 void cpu_signal_handler(void);
272 extern unsigned int gFastIPI;
273 #endif /* defined(HAS_IPI) */
274
275 static arm_saved_state64_t *original_faulting_state = NULL;
276
277
278 TUNABLE(bool, fp_exceptions_enabled, "-fp_exceptions", false);
279
280 extern vm_offset_t static_memory_end;
281
282 /*
283 * Fault copyio_recovery_entry in copyin/copyout routines.
284 *
285 * Offets are expressed in bytes from ©_recovery_table
286 */
287 struct copyio_recovery_entry {
288 ptrdiff_t cre_start;
289 ptrdiff_t cre_end;
290 ptrdiff_t cre_recovery;
291 };
292
293 extern struct copyio_recovery_entry copyio_recover_table[];
294 extern struct copyio_recovery_entry copyio_recover_table_end[];
295
296 static inline ptrdiff_t
copyio_recovery_offset(uintptr_t addr)297 copyio_recovery_offset(uintptr_t addr)
298 {
299 return (ptrdiff_t)(addr - (uintptr_t)copyio_recover_table);
300 }
301
302 #if !HAS_APPLE_PAC
303 static inline uintptr_t
copyio_recovery_addr(ptrdiff_t offset)304 copyio_recovery_addr(ptrdiff_t offset)
305 {
306 return (uintptr_t)copyio_recover_table + (uintptr_t)offset;
307 }
308 #endif
309
310 static inline struct copyio_recovery_entry *
find_copyio_recovery_entry(arm_saved_state_t * state)311 find_copyio_recovery_entry(arm_saved_state_t *state)
312 {
313 ptrdiff_t offset = copyio_recovery_offset(get_saved_state_pc(state));
314 struct copyio_recovery_entry *e;
315
316 for (e = copyio_recover_table; e < copyio_recover_table_end; e++) {
317 if (offset >= e->cre_start && offset < e->cre_end) {
318 return e;
319 }
320 }
321
322 return NULL;
323 }
324
325 static inline int
is_vm_fault(fault_status_t status)326 is_vm_fault(fault_status_t status)
327 {
328 switch (status) {
329 case FSC_TRANSLATION_FAULT_L0:
330 case FSC_TRANSLATION_FAULT_L1:
331 case FSC_TRANSLATION_FAULT_L2:
332 case FSC_TRANSLATION_FAULT_L3:
333 case FSC_ACCESS_FLAG_FAULT_L1:
334 case FSC_ACCESS_FLAG_FAULT_L2:
335 case FSC_ACCESS_FLAG_FAULT_L3:
336 case FSC_PERMISSION_FAULT_L1:
337 case FSC_PERMISSION_FAULT_L2:
338 case FSC_PERMISSION_FAULT_L3:
339 return TRUE;
340 default:
341 return FALSE;
342 }
343 }
344
345 static inline int
is_translation_fault(fault_status_t status)346 is_translation_fault(fault_status_t status)
347 {
348 switch (status) {
349 case FSC_TRANSLATION_FAULT_L0:
350 case FSC_TRANSLATION_FAULT_L1:
351 case FSC_TRANSLATION_FAULT_L2:
352 case FSC_TRANSLATION_FAULT_L3:
353 return TRUE;
354 default:
355 return FALSE;
356 }
357 }
358
359 static inline int
is_permission_fault(fault_status_t status)360 is_permission_fault(fault_status_t status)
361 {
362 switch (status) {
363 case FSC_PERMISSION_FAULT_L1:
364 case FSC_PERMISSION_FAULT_L2:
365 case FSC_PERMISSION_FAULT_L3:
366 return TRUE;
367 default:
368 return FALSE;
369 }
370 }
371
372 static inline int
is_alignment_fault(fault_status_t status)373 is_alignment_fault(fault_status_t status)
374 {
375 return status == FSC_ALIGNMENT_FAULT;
376 }
377
378 static inline int
is_parity_error(fault_status_t status)379 is_parity_error(fault_status_t status)
380 {
381 switch (status) {
382 #if defined(ARM64_BOARD_CONFIG_T6020)
383 /*
384 * H14 Erratum (rdar://61553243): Despite having FEAT_RAS implemented,
385 * FSC_SYNC_PARITY_X can be reported for data and instruction aborts
386 * and should be interpreted as FSC_SYNC_EXT_ABORT_x
387 */
388 #else
389 /*
390 * TODO: According to ARM ARM, Async Parity (0b011001) is a DFSC that is
391 * only applicable to AArch32 HSR register. Can this be removed?
392 */
393 case FSC_ASYNC_PARITY:
394 case FSC_SYNC_PARITY:
395 case FSC_SYNC_PARITY_TT_L1:
396 case FSC_SYNC_PARITY_TT_L2:
397 case FSC_SYNC_PARITY_TT_L3:
398 return TRUE;
399 #endif
400 default:
401 return FALSE;
402 }
403 }
404
405 static inline int
is_sync_external_abort(fault_status_t status)406 is_sync_external_abort(fault_status_t status)
407 {
408 switch (status) {
409 #if defined(ARM64_BOARD_CONFIG_T6020)
410 /*
411 * H14 Erratum (rdar://61553243): Despite having FEAT_RAS implemented,
412 * FSC_SYNC_PARITY_x can be reported for data and instruction aborts
413 * and should be interpreted as FSC_SYNC_EXT_ABORT_x
414 */
415 case FSC_SYNC_PARITY:
416 #endif /* defined(ARM64_BOARD_CONFIG_T6020) */
417 case FSC_SYNC_EXT_ABORT:
418 return TRUE;
419 default:
420 return FALSE;
421 }
422 }
423
424 static inline int
is_table_walk_error(fault_status_t status)425 is_table_walk_error(fault_status_t status)
426 {
427 switch (status) {
428 case FSC_SYNC_EXT_ABORT_TT_L1:
429 case FSC_SYNC_EXT_ABORT_TT_L2:
430 case FSC_SYNC_EXT_ABORT_TT_L3:
431 #if defined(ARM64_BOARD_CONFIG_T6020)
432 /*
433 * H14 Erratum(rdar://61553243): Despite having FEAT_RAS implemented,
434 * FSC_SYNC_PARITY_x can be reported for data and instruction aborts
435 * and should be interpreted as FSC_SYNC_EXT_ABORT_x
436 */
437 case FSC_SYNC_PARITY_TT_L1:
438 case FSC_SYNC_PARITY_TT_L2:
439 case FSC_SYNC_PARITY_TT_L3:
440 #endif /* defined(ARM64_BOARD_CONFIG_T6020) */
441 return TRUE;
442 default:
443 return FALSE;
444 }
445 }
446
447
448
449 static inline int
is_servicible_fault(fault_status_t status,uint64_t esr)450 is_servicible_fault(fault_status_t status, uint64_t esr)
451 {
452 #pragma unused(esr)
453 return is_vm_fault(status);
454 }
455
456 __dead2 __unused
457 static void
arm64_implementation_specific_error(arm_saved_state_t * state,uint64_t esr,vm_offset_t far)458 arm64_implementation_specific_error(arm_saved_state_t *state, uint64_t esr, vm_offset_t far)
459 {
460 #pragma unused (state, esr, far)
461 panic_plain("Unhandled implementation specific error\n");
462 }
463
464 #if CONFIG_KERNEL_INTEGRITY
465 #pragma clang diagnostic push
466 #pragma clang diagnostic ignored "-Wunused-parameter"
467 static void
kernel_integrity_error_handler(uint64_t esr,vm_offset_t far)468 kernel_integrity_error_handler(uint64_t esr, vm_offset_t far)
469 {
470 #if defined(KERNEL_INTEGRITY_WT)
471 #if (DEVELOPMENT || DEBUG)
472 if (ESR_WT_SERROR(esr)) {
473 switch (ESR_WT_REASON(esr)) {
474 case WT_REASON_INTEGRITY_FAIL:
475 panic_plain("Kernel integrity, violation in frame 0x%016lx.", far);
476 case WT_REASON_BAD_SYSCALL:
477 panic_plain("Kernel integrity, bad syscall.");
478 case WT_REASON_NOT_LOCKED:
479 panic_plain("Kernel integrity, not locked.");
480 case WT_REASON_ALREADY_LOCKED:
481 panic_plain("Kernel integrity, already locked.");
482 case WT_REASON_SW_REQ:
483 panic_plain("Kernel integrity, software request.");
484 case WT_REASON_PT_INVALID:
485 panic_plain("Kernel integrity, encountered invalid TTE/PTE while "
486 "walking 0x%016lx.", far);
487 case WT_REASON_PT_VIOLATION:
488 panic_plain("Kernel integrity, violation in mapping 0x%016lx.",
489 far);
490 case WT_REASON_REG_VIOLATION:
491 panic_plain("Kernel integrity, violation in system register %d.",
492 (unsigned) far);
493 default:
494 panic_plain("Kernel integrity, unknown (esr=0x%08llx).", esr);
495 }
496 }
497 #else
498 if (ESR_WT_SERROR(esr)) {
499 panic_plain("SError esr: 0x%08llx far: 0x%016lx.", esr, far);
500 }
501 #endif
502 #endif
503 }
504 #pragma clang diagnostic pop
505 #endif
506
507 static void
arm64_platform_error(arm_saved_state_t * state,uint64_t esr,vm_offset_t far,platform_error_source_t source)508 arm64_platform_error(arm_saved_state_t *state, uint64_t esr, vm_offset_t far, platform_error_source_t source)
509 {
510 #if CONFIG_KERNEL_INTEGRITY
511 kernel_integrity_error_handler(esr, far);
512 #endif
513
514 (void)source;
515 cpu_data_t *cdp = getCpuDatap();
516
517 if (PE_handle_platform_error(far)) {
518 return;
519 } else if (cdp->platform_error_handler != NULL) {
520 cdp->platform_error_handler(cdp->cpu_id, far);
521 } else {
522 arm64_implementation_specific_error(state, esr, far);
523 }
524 }
525
526 void
panic_with_thread_kernel_state(const char * msg,arm_saved_state_t * ss)527 panic_with_thread_kernel_state(const char *msg, arm_saved_state_t *ss)
528 {
529 boolean_t ss_valid;
530
531 ss_valid = is_saved_state64(ss);
532 arm_saved_state64_t *state = saved_state64(ss);
533
534 os_atomic_cmpxchg(&original_faulting_state, NULL, state, seq_cst);
535
536 // rdar://80659177
537 // Read SoCD tracepoints up to twice — once the first time we call panic and
538 // another time if we encounter a nested panic after that.
539 static int twice = 2;
540 if (twice > 0) {
541 twice--;
542 SOCD_TRACE_XNU(KERNEL_STATE_PANIC, ADDR(state->pc),
543 PACK_LSB(VALUE(state->lr), VALUE(ss_valid)),
544 PACK_2X32(VALUE(state->esr), VALUE(state->cpsr)),
545 VALUE(state->far));
546 }
547
548
549 panic_plain("%s at pc 0x%016llx, lr 0x%016llx (saved state: %p%s)\n"
550 "\t x0: 0x%016llx x1: 0x%016llx x2: 0x%016llx x3: 0x%016llx\n"
551 "\t x4: 0x%016llx x5: 0x%016llx x6: 0x%016llx x7: 0x%016llx\n"
552 "\t x8: 0x%016llx x9: 0x%016llx x10: 0x%016llx x11: 0x%016llx\n"
553 "\t x12: 0x%016llx x13: 0x%016llx x14: 0x%016llx x15: 0x%016llx\n"
554 "\t x16: 0x%016llx x17: 0x%016llx x18: 0x%016llx x19: 0x%016llx\n"
555 "\t x20: 0x%016llx x21: 0x%016llx x22: 0x%016llx x23: 0x%016llx\n"
556 "\t x24: 0x%016llx x25: 0x%016llx x26: 0x%016llx x27: 0x%016llx\n"
557 "\t x28: 0x%016llx fp: 0x%016llx lr: 0x%016llx sp: 0x%016llx\n"
558 "\t pc: 0x%016llx cpsr: 0x%08x esr: 0x%016llx far: 0x%016llx\n",
559 msg, state->pc, state->lr, ss, (ss_valid ? "" : " INVALID"),
560 state->x[0], state->x[1], state->x[2], state->x[3],
561 state->x[4], state->x[5], state->x[6], state->x[7],
562 state->x[8], state->x[9], state->x[10], state->x[11],
563 state->x[12], state->x[13], state->x[14], state->x[15],
564 state->x[16], state->x[17], state->x[18], state->x[19],
565 state->x[20], state->x[21], state->x[22], state->x[23],
566 state->x[24], state->x[25], state->x[26], state->x[27],
567 state->x[28], state->fp, state->lr, state->sp,
568 state->pc, state->cpsr, state->esr, state->far);
569 }
570
571 void
sleh_synchronous_sp1(arm_context_t * context,uint64_t esr,vm_offset_t far __unused)572 sleh_synchronous_sp1(arm_context_t *context, uint64_t esr, vm_offset_t far __unused)
573 {
574 esr_exception_class_t class = ESR_EC(esr);
575 arm_saved_state_t * state = &context->ss;
576
577 switch (class) {
578 case ESR_EC_UNCATEGORIZED:
579 {
580 #if (DEVELOPMENT || DEBUG)
581 uint32_t instr = *((uint32_t*)get_saved_state_pc(state));
582 if (IS_ARM_GDB_TRAP(instr)) {
583 DebuggerCall(EXC_BREAKPOINT, state);
584 }
585 OS_FALLTHROUGH; // panic if we return from the debugger
586 #else
587 panic_with_thread_kernel_state("Unexpected debugger trap while SP1 selected", state);
588 #endif /* (DEVELOPMENT || DEBUG) */
589 }
590 default:
591 panic_with_thread_kernel_state("Synchronous exception taken while SP1 selected", state);
592 }
593 }
594
595
596 __attribute__((noreturn))
597 void
thread_exception_return()598 thread_exception_return()
599 {
600 thread_t thread = current_thread();
601 if (thread->machine.exception_trace_code != 0) {
602 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
603 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, thread->machine.exception_trace_code) | DBG_FUNC_END, 0, 0, 0, 0, 0);
604 thread->machine.exception_trace_code = 0;
605 }
606
607 #if KASAN_TBI
608 kasan_unpoison_curstack(true);
609 #endif /* KASAN_TBI */
610 arm64_thread_exception_return();
611 __builtin_unreachable();
612 }
613
614 /*
615 * check whether task vtimers are running and set thread and CPU BSD AST
616 *
617 * must be called with interrupts masked so updates of fields are atomic
618 * must be emitted inline to avoid generating an FBT probe on the exception path
619 *
620 */
621 __attribute__((__always_inline__))
622 static inline void
task_vtimer_check(thread_t thread)623 task_vtimer_check(thread_t thread)
624 {
625 task_t task = get_threadtask_early(thread);
626
627 if (__improbable(task != NULL && task->vtimers)) {
628 thread_ast_set(thread, AST_BSD);
629 thread->machine.CpuDatap->cpu_pending_ast |= AST_BSD;
630 }
631 }
632
633 #if MACH_ASSERT
634 /**
635 * A version of get_preemption_level() that works in early boot.
636 *
637 * If an exception is raised in early boot before the initial thread has been
638 * set up, then calling get_preemption_level() in the SLEH will trigger an
639 * infinitely-recursing exception. This function handles this edge case.
640 */
641 static inline int
sleh_get_preemption_level(void)642 sleh_get_preemption_level(void)
643 {
644 if (__improbable(current_thread() == NULL)) {
645 return 0;
646 }
647 return get_preemption_level();
648 }
649 #endif // MACH_ASSERT
650
651 static inline bool
is_platform_error(uint64_t esr)652 is_platform_error(uint64_t esr)
653 {
654 esr_exception_class_t class = ESR_EC(esr);
655 uint32_t iss = ESR_ISS(esr);
656 fault_status_t fault_code;
657
658 if (class == ESR_EC_DABORT_EL0 || class == ESR_EC_DABORT_EL1) {
659 fault_code = ISS_DA_FSC(iss);
660 } else if (class == ESR_EC_IABORT_EL0 || class == ESR_EC_IABORT_EL1) {
661 fault_code = ISS_IA_FSC(iss);
662 } else {
663 return false;
664 }
665
666 return is_parity_error(fault_code) || is_sync_external_abort(fault_code) ||
667 is_table_walk_error(fault_code);
668 }
669
670 void
sleh_synchronous(arm_context_t * context,uint64_t esr,vm_offset_t far,__unused bool did_initiate_panic_lockdown)671 sleh_synchronous(arm_context_t *context, uint64_t esr, vm_offset_t far, __unused bool did_initiate_panic_lockdown)
672 {
673 esr_exception_class_t class = ESR_EC(esr);
674 arm_saved_state_t * state = &context->ss;
675 thread_t thread = current_thread();
676 #if MACH_ASSERT
677 int preemption_level = sleh_get_preemption_level();
678 #endif
679 expected_fault_handler_t expected_fault_handler = NULL;
680 #ifdef CONFIG_XNUPOST
681 expected_fault_handler_t saved_expected_fault_handler = NULL;
682 uintptr_t saved_expected_fault_addr = 0;
683 uintptr_t saved_expected_fault_pc = 0;
684 #endif /* CONFIG_XNUPOST */
685
686 ASSERT_CONTEXT_SANITY(context);
687
688 task_vtimer_check(thread);
689
690 #if CONFIG_DTRACE
691 /*
692 * Handle kernel DTrace probes as early as possible to minimize the likelihood
693 * that this path will itself trigger a DTrace probe, which would lead to infinite
694 * probe recursion.
695 */
696 if (__improbable((class == ESR_EC_UNCATEGORIZED) && tempDTraceTrapHook &&
697 (tempDTraceTrapHook(EXC_BAD_INSTRUCTION, state, 0, 0) == KERN_SUCCESS))) {
698 #if CONFIG_SPTM
699 if (__improbable(did_initiate_panic_lockdown)) {
700 panic("Unexpectedly initiated lockdown for DTrace probe?");
701 }
702 #endif
703 return;
704 }
705 #endif
706 bool is_user = PSR64_IS_USER(get_saved_state_cpsr(state));
707
708 #if CONFIG_SPTM
709 // Lockdown should only be initiated for kernel exceptions
710 assert(!(is_user && did_initiate_panic_lockdown));
711 #endif /* CONFIG_SPTM */
712
713 /*
714 * Use KERNEL_DEBUG_CONSTANT_IST here to avoid producing tracepoints
715 * that would disclose the behavior of PT_DENY_ATTACH processes.
716 */
717 if (is_user) {
718 /* Sanitize FAR (but only if the exception was taken from userspace) */
719 switch (class) {
720 case ESR_EC_IABORT_EL1:
721 case ESR_EC_IABORT_EL0:
722 /* If this is a SEA, since we can't trust FnV, just clear FAR from the save area. */
723 if (ISS_IA_FSC(ESR_ISS(esr)) == FSC_SYNC_EXT_ABORT) {
724 saved_state64(state)->far = 0;
725 }
726 break;
727 case ESR_EC_DABORT_EL1:
728 case ESR_EC_DABORT_EL0:
729 /* If this is a SEA, since we can't trust FnV, just clear FAR from the save area. */
730 if (ISS_DA_FSC(ESR_ISS(esr)) == FSC_SYNC_EXT_ABORT) {
731 saved_state64(state)->far = 0;
732 }
733 break;
734 case ESR_EC_WATCHPT_MATCH_EL1:
735 case ESR_EC_WATCHPT_MATCH_EL0:
736 case ESR_EC_PC_ALIGN:
737 break; /* FAR_ELx is valid */
738 default:
739 saved_state64(state)->far = 0;
740 break;
741 }
742
743 thread->machine.exception_trace_code = (uint16_t)(ARM64_KDBG_CODE_USER | class);
744 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
745 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, thread->machine.exception_trace_code) | DBG_FUNC_START,
746 esr, far, get_saved_state_pc(state), 0, 0);
747 } else {
748 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
749 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, ARM64_KDBG_CODE_KERNEL | class) | DBG_FUNC_START,
750 esr, VM_KERNEL_ADDRHIDE(far), VM_KERNEL_UNSLIDE(get_saved_state_pc(state)), 0, 0);
751 }
752
753 if (__improbable(ESR_INSTR_IS_2BYTES(esr))) {
754 /*
755 * We no longer support 32-bit, which means no 2-byte
756 * instructions.
757 */
758 if (is_user) {
759 panic("Exception on 2-byte instruction, "
760 "context=%p, esr=%#llx, far=%p",
761 context, esr, (void *)far);
762 } else {
763 panic_with_thread_kernel_state("Exception on 2-byte instruction", state);
764 }
765 }
766
767 #ifdef CONFIG_XNUPOST
768 if (thread->machine.expected_fault_handler != NULL) {
769 bool matching_fault_pc = false;
770 saved_expected_fault_handler = thread->machine.expected_fault_handler;
771 saved_expected_fault_addr = thread->machine.expected_fault_addr;
772 saved_expected_fault_pc = thread->machine.expected_fault_pc;
773
774 thread->machine.expected_fault_handler = NULL;
775 thread->machine.expected_fault_addr = 0;
776 thread->machine.expected_fault_pc = 0;
777
778 #if __has_feature(ptrauth_calls)
779 /*
780 * Compare only the bits of PC which make up the virtual address.
781 * This ignores the upper bits, which may have been corrupted by HW in
782 * platform dependent ways to signal pointer authentication fault.
783 */
784 uint64_t fault_addr_mask = fault_addr_bitmask(0, 64 - T1SZ_BOOT - 1);
785 uint64_t masked_expected_pc = saved_expected_fault_pc & fault_addr_mask;
786 uint64_t masked_saved_pc = get_saved_state_pc(state) & fault_addr_mask;
787 matching_fault_pc = masked_expected_pc == masked_saved_pc;
788 #else
789 matching_fault_pc =
790 (saved_expected_fault_pc == get_saved_state_pc(state));
791 #endif /* ptrauth_call */
792 if (saved_expected_fault_addr == far ||
793 matching_fault_pc) {
794 expected_fault_handler = saved_expected_fault_handler;
795 }
796 }
797 #endif /* CONFIG_XNUPOST */
798
799 if (__improbable(is_platform_error(esr))) {
800 /*
801 * Must gather error info in platform error handler before
802 * thread is preempted to another core/cluster to guarantee
803 * accurate error details
804 */
805
806 arm64_platform_error(state, esr, far, PLAT_ERR_SRC_SYNC);
807 #if CONFIG_SPTM
808 if (__improbable(did_initiate_panic_lockdown)) {
809 panic("Panic lockdown initiated for platform error");
810 }
811 #endif
812 return;
813 }
814
815 if (is_user && class == ESR_EC_DABORT_EL0) {
816 thread_reset_pcs_will_fault(thread);
817 }
818
819 /* Inherit the interrupt masks from previous context */
820 if (SPSR_INTERRUPTS_ENABLED(get_saved_state_cpsr(state))) {
821 ml_set_interrupts_enabled(TRUE);
822 }
823
824 switch (class) {
825 case ESR_EC_SVC_64:
826 if (!is_saved_state64(state) || !is_user) {
827 panic("Invalid SVC_64 context");
828 }
829
830 handle_svc(state);
831 break;
832
833 case ESR_EC_DABORT_EL0:
834 handle_abort(state, esr, far, inspect_data_abort, handle_user_abort, expected_fault_handler);
835 break;
836
837 case ESR_EC_MSR_TRAP:
838 handle_msr_trap(state, esr);
839 break;
840 /**
841 * Some APPLEVIRTUALPLATFORM targets do not specify armv8.6, but it's still possible for
842 * them to be hosted by a host that implements ARM_FPAC. There's no way for such a host
843 * to disable it or trap it without substantial performance penalty. Therefore, the FPAC
844 * handler here needs to be built into the guest kernels to prevent the exception to fall
845 * through.
846 */
847 #if __has_feature(ptrauth_calls)
848 case ESR_EC_PAC_FAIL:
849 #ifdef CONFIG_XNUPOST
850 if (expected_fault_handler != NULL && expected_fault_handler(state)) {
851 break;
852 }
853 #endif /* CONFIG_XNUPOST */
854 handle_pac_fail(state, esr);
855 __builtin_unreachable();
856
857 #endif /* __has_feature(ptrauth_calls) */
858
859 #if HAS_ARM_FEAT_SME
860 case ESR_EC_SME:
861 handle_sme_trap(state, esr);
862 break;
863 #endif /* HAS_ARM_FEAT_SME */
864
865 case ESR_EC_IABORT_EL0:
866 handle_abort(state, esr, far, inspect_instruction_abort, handle_user_abort, expected_fault_handler);
867 break;
868
869 case ESR_EC_IABORT_EL1:
870 #ifdef CONFIG_XNUPOST
871 if ((expected_fault_handler != NULL) && expected_fault_handler(state)) {
872 break;
873 }
874 #endif /* CONFIG_XNUPOST */
875
876 panic_with_thread_kernel_state("Kernel instruction fetch abort", state);
877
878 case ESR_EC_PC_ALIGN:
879 handle_pc_align(state);
880 __builtin_unreachable();
881
882 case ESR_EC_DABORT_EL1:
883 handle_abort(state, esr, far, inspect_data_abort, handle_kernel_abort, expected_fault_handler);
884 break;
885
886 case ESR_EC_UNCATEGORIZED:
887 assert(!ESR_ISS(esr));
888
889 #if CONFIG_XNUPOST
890 if (!is_user && (expected_fault_handler != NULL) && expected_fault_handler(state)) {
891 /*
892 * The fault handler accepted the exception and handled it on its
893 * own. Don't trap to the debugger/panic.
894 */
895 break;
896 }
897 #endif /* CONFIG_XNUPOST */
898 handle_uncategorized(&context->ss);
899 break;
900
901 case ESR_EC_SP_ALIGN:
902 handle_sp_align(state);
903 __builtin_unreachable();
904
905 case ESR_EC_BKPT_AARCH32:
906 handle_breakpoint(state, esr);
907 __builtin_unreachable();
908
909 case ESR_EC_BRK_AARCH64:
910 #ifdef CONFIG_XNUPOST
911 if ((expected_fault_handler != NULL) && expected_fault_handler(state)) {
912 break;
913 }
914 #endif /* CONFIG_XNUPOST */
915 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
916 handle_kernel_breakpoint(state, esr);
917 break;
918 } else {
919 handle_breakpoint(state, esr);
920 __builtin_unreachable();
921 }
922
923 case ESR_EC_BKPT_REG_MATCH_EL0:
924 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
925 handle_breakpoint(state, esr);
926 }
927 panic("Unsupported Class %u event code. state=%p class=%u esr=%llu far=%p",
928 class, state, class, esr, (void *)far);
929 __builtin_unreachable();
930
931 case ESR_EC_BKPT_REG_MATCH_EL1:
932 panic_with_thread_kernel_state("Hardware Breakpoint Debug exception from kernel. Panic (by design)", state);
933 __builtin_unreachable();
934
935 case ESR_EC_SW_STEP_DEBUG_EL0:
936 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
937 handle_sw_step_debug(state);
938 }
939 panic("Unsupported Class %u event code. state=%p class=%u esr=%llu far=%p",
940 class, state, class, esr, (void *)far);
941 __builtin_unreachable();
942
943 case ESR_EC_SW_STEP_DEBUG_EL1:
944 panic_with_thread_kernel_state("Software Step Debug exception from kernel. Panic (by design)", state);
945 __builtin_unreachable();
946
947 case ESR_EC_WATCHPT_MATCH_EL0:
948 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
949 handle_watchpoint(far);
950 }
951 panic("Unsupported Class %u event code. state=%p class=%u esr=%llu far=%p",
952 class, state, class, esr, (void *)far);
953 __builtin_unreachable();
954
955 case ESR_EC_WATCHPT_MATCH_EL1:
956 /*
957 * If we hit a watchpoint in kernel mode, probably in a copyin/copyout which we don't want to
958 * abort. Turn off watchpoints and keep going; we'll turn them back on in return_from_exception..
959 */
960 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
961 arm_debug_set(NULL);
962 break; /* return to first level handler */
963 }
964 panic("Unsupported Class %u event code. state=%p class=%u esr=%llu far=%p",
965 class, state, class, esr, (void *)far);
966 __builtin_unreachable();
967
968 case ESR_EC_TRAP_SIMD_FP:
969 handle_simd_trap(state, esr);
970 __builtin_unreachable();
971
972 case ESR_EC_ILLEGAL_INSTR_SET:
973 panic("Illegal instruction set exception. state=%p class=%u esr=%llu far=%p spsr=0x%x",
974 state, class, esr, (void *)far, get_saved_state_cpsr(state));
975 __builtin_unreachable();
976
977 case ESR_EC_MCR_MRC_CP15_TRAP:
978 case ESR_EC_MCRR_MRRC_CP15_TRAP:
979 case ESR_EC_MCR_MRC_CP14_TRAP:
980 case ESR_EC_LDC_STC_CP14_TRAP:
981 case ESR_EC_MCRR_MRRC_CP14_TRAP:
982 handle_user_trapped_instruction32(state, esr);
983 __builtin_unreachable();
984
985 case ESR_EC_WFI_WFE:
986 // Use of WFI or WFE instruction when they have been disabled for EL0
987 handle_wf_trap(state);
988 __builtin_unreachable();
989
990 case ESR_EC_FLOATING_POINT_64:
991 handle_fp_trap(state, esr);
992 __builtin_unreachable();
993 case ESR_EC_BTI_FAIL:
994 #ifdef CONFIG_XNUPOST
995 if ((expected_fault_handler != NULL) && expected_fault_handler(state)) {
996 break;
997 }
998 #endif /* CONFIG_XNUPOST */
999 #ifdef CONFIG_BTI_TELEMETRY
1000 if (bti_telemetry_handle_exception(state)) {
1001 /* Telemetry has accepted and corrected the exception, continue */
1002 break;
1003 }
1004 #endif /* CONFIG_BTI_TELEMETRY */
1005 handle_bti_fail(state, esr);
1006 __builtin_unreachable();
1007
1008 default:
1009 handle_uncategorized(state);
1010 }
1011
1012 #ifdef CONFIG_XNUPOST
1013 if (saved_expected_fault_handler != NULL) {
1014 thread->machine.expected_fault_handler = saved_expected_fault_handler;
1015 thread->machine.expected_fault_addr = saved_expected_fault_addr;
1016 thread->machine.expected_fault_pc = saved_expected_fault_pc;
1017 }
1018 #endif /* CONFIG_XNUPOST */
1019
1020 if (is_user) {
1021 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
1022 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, thread->machine.exception_trace_code) | DBG_FUNC_END,
1023 esr, far, get_saved_state_pc(state), 0, 0);
1024 thread->machine.exception_trace_code = 0;
1025 } else {
1026 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
1027 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, ARM64_KDBG_CODE_KERNEL | class) | DBG_FUNC_END,
1028 esr, VM_KERNEL_ADDRHIDE(far), VM_KERNEL_UNSLIDE(get_saved_state_pc(state)), 0, 0);
1029 }
1030 #if MACH_ASSERT
1031 if (preemption_level != sleh_get_preemption_level()) {
1032 panic("synchronous exception changed preemption level from %d to %d", preemption_level, sleh_get_preemption_level());
1033 }
1034 #endif
1035
1036 #if CONFIG_SPTM
1037 if (did_initiate_panic_lockdown
1038 #if CONFIG_XNUPOST
1039 /* Do not engage the panic interlock if we matched a fault handler */
1040 && !expected_fault_handler
1041 #endif /* CONFIG_XNUPOST */
1042 ) {
1043 /*
1044 * fleh already triggered a lockdown but we, for whatever reason, didn't
1045 * end up finding a reason to panic. Catch all panic in this case.
1046 * Note that the panic here has no security benefit as the system is already
1047 * hosed, this is merely for telemetry.
1048 */
1049 panic_with_thread_kernel_state("Panic lockdown initiated", state);
1050 }
1051 #endif /* CONFIG_SPTM */
1052 }
1053
1054 /*
1055 * Uncategorized exceptions are a catch-all for general execution errors.
1056 * ARM64_TODO: For now, we assume this is for undefined instruction exceptions.
1057 */
1058 static void
handle_uncategorized(arm_saved_state_t * state)1059 handle_uncategorized(arm_saved_state_t *state)
1060 {
1061 exception_type_t exception = EXC_BAD_INSTRUCTION;
1062 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
1063 mach_msg_type_number_t numcodes = 2;
1064 uint32_t instr = 0;
1065
1066 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1067
1068 #if CONFIG_DTRACE
1069
1070 if (PSR64_IS_USER64(get_saved_state_cpsr(state))) {
1071 /*
1072 * For a 64bit user process, we care about all 4 bytes of the
1073 * instr.
1074 */
1075 if (instr == FASTTRAP_ARM64_INSTR || instr == FASTTRAP_ARM64_RET_INSTR) {
1076 if (dtrace_user_probe(state) == KERN_SUCCESS) {
1077 return;
1078 }
1079 }
1080 } else if (PSR64_IS_USER32(get_saved_state_cpsr(state))) {
1081 /*
1082 * For a 32bit user process, we check for thumb mode, in
1083 * which case we only care about a 2 byte instruction length.
1084 * For non-thumb mode, we care about all 4 bytes of the instructin.
1085 */
1086 if (get_saved_state_cpsr(state) & PSR64_MODE_USER32_THUMB) {
1087 if (((uint16_t)instr == FASTTRAP_THUMB32_INSTR) ||
1088 ((uint16_t)instr == FASTTRAP_THUMB32_RET_INSTR)) {
1089 if (dtrace_user_probe(state) == KERN_SUCCESS) {
1090 return;
1091 }
1092 }
1093 } else {
1094 if ((instr == FASTTRAP_ARM32_INSTR) ||
1095 (instr == FASTTRAP_ARM32_RET_INSTR)) {
1096 if (dtrace_user_probe(state) == KERN_SUCCESS) {
1097 return;
1098 }
1099 }
1100 }
1101 }
1102
1103 #endif /* CONFIG_DTRACE */
1104
1105 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
1106 if (IS_ARM_GDB_TRAP(instr)) {
1107 boolean_t interrupt_state;
1108 exception = EXC_BREAKPOINT;
1109
1110 interrupt_state = ml_set_interrupts_enabled(FALSE);
1111
1112 /* Save off the context here (so that the debug logic
1113 * can see the original state of this thread).
1114 */
1115 current_thread()->machine.kpcb = state;
1116
1117 /* Hop into the debugger (typically either due to a
1118 * fatal exception, an explicit panic, or a stackshot
1119 * request.
1120 */
1121 DebuggerCall(exception, state);
1122
1123 current_thread()->machine.kpcb = NULL;
1124 (void) ml_set_interrupts_enabled(interrupt_state);
1125 return;
1126 } else {
1127 panic("Undefined kernel instruction: pc=%p instr=%x", (void*)get_saved_state_pc(state), instr);
1128 }
1129 }
1130
1131 /*
1132 * Check for GDB breakpoint via illegal opcode.
1133 */
1134 if (IS_ARM_GDB_TRAP(instr)) {
1135 exception = EXC_BREAKPOINT;
1136 codes[0] = EXC_ARM_BREAKPOINT;
1137 codes[1] = instr;
1138 } else {
1139 codes[1] = instr;
1140 }
1141
1142 exception_triage(exception, codes, numcodes);
1143 __builtin_unreachable();
1144 }
1145
1146 #if __has_feature(ptrauth_calls)
1147 static const uint16_t PTRAUTH_TRAP_START = 0xC470;
1148 static inline bool
brk_comment_is_ptrauth(uint16_t comment)1149 brk_comment_is_ptrauth(uint16_t comment)
1150 {
1151 return comment >= PTRAUTH_TRAP_START &&
1152 comment <= PTRAUTH_TRAP_START + ptrauth_key_asdb;
1153 }
1154
1155 static inline const char *
ptrauth_key_to_string(ptrauth_key key)1156 ptrauth_key_to_string(ptrauth_key key)
1157 {
1158 switch (key) {
1159 case ptrauth_key_asia:
1160 return "IA";
1161 case ptrauth_key_asib:
1162 return "IB";
1163 case ptrauth_key_asda:
1164 return "DA";
1165 case ptrauth_key_asdb:
1166 return "DB";
1167 default:
1168 __builtin_unreachable();
1169 }
1170 }
1171
1172 static void __attribute__((noreturn))
ptrauth_handle_brk_trap(void * tstate,uint16_t comment)1173 ptrauth_handle_brk_trap(void *tstate, uint16_t comment)
1174 {
1175 arm_saved_state_t *state = (arm_saved_state_t *)tstate;
1176 #define MSG_FMT "Break 0x%04X instruction exception from kernel. Ptrauth failure with %s key resulted in 0x%016llx"
1177 char msg[strlen(MSG_FMT)
1178 - strlen("0x%04X") + strlen("0xFFFF")
1179 - strlen("%s") + strlen("IA")
1180 - strlen("0x%016llx") + strlen("0xFFFFFFFFFFFFFFFF")
1181 + 1];
1182 ptrauth_key key = (ptrauth_key)(comment - PTRAUTH_TRAP_START);
1183 const char *key_str = ptrauth_key_to_string(key);
1184 snprintf(msg, sizeof(msg), MSG_FMT, comment, key_str, saved_state64(state)->x[16]);
1185 #undef MSG_FMT
1186
1187 panic_with_thread_kernel_state(msg, state);
1188 __builtin_unreachable();
1189 }
1190 #endif /* __has_feature(ptrauth_calls) */
1191
1192 #if HAS_TELEMETRY_KERNEL_BRK
1193 static uint32_t bound_chk_violations_event;
1194
1195 static void
xnu_soft_trap_handle_breakpoint(void * tstate,uint16_t comment)1196 xnu_soft_trap_handle_breakpoint(
1197 void *tstate,
1198 uint16_t comment)
1199 {
1200 #if CONFIG_UBSAN_MINIMAL
1201 if (comment == UBSAN_SOFT_TRAP_SIGNED_OF) {
1202 ubsan_handle_brk_trap(tstate, comment);
1203 }
1204 #else
1205 (void)tstate;
1206 #endif
1207
1208 if (comment == CLANG_SOFT_TRAP_BOUND_CHK) {
1209 os_atomic_inc(&bound_chk_violations_event, relaxed);
1210 }
1211 }
1212 #endif /* HAS_TELEMETRY_KERNEL_BRK */
1213
1214 static void
xnu_hard_trap_handle_breakpoint(void * tstate,uint16_t comment)1215 xnu_hard_trap_handle_breakpoint(void *tstate, uint16_t comment)
1216 {
1217 switch (comment) {
1218 case XNU_HARD_TRAP_SAFE_UNLINK: {
1219 #define MSG_FMT "panic: corrupt list around element %p"
1220 char msg[strlen(MSG_FMT) - strlen("%p") + 18 + 1];
1221 arm_saved_state64_t *state = saved_state64(tstate);
1222
1223 snprintf(msg, sizeof(msg), MSG_FMT, (void *)state->x[8]);
1224 panic_with_thread_kernel_state(msg, tstate);
1225 #undef MSG_FMT
1226 }
1227 case XNU_HARD_TRAP_STRING_CHK:
1228 panic_with_thread_kernel_state("panic: string operation caused an overflow", tstate);
1229 default:
1230 break;
1231 }
1232 }
1233
1234 #if __has_feature(ptrauth_calls)
1235 KERNEL_BRK_DESCRIPTOR_DEFINE(ptrauth_desc,
1236 .type = KERNEL_BRK_TYPE_PTRAUTH,
1237 .base = PTRAUTH_TRAP_START,
1238 .max = PTRAUTH_TRAP_START + ptrauth_key_asdb,
1239 .options = KERNEL_BRK_UNRECOVERABLE,
1240 .handle_breakpoint = ptrauth_handle_brk_trap);
1241 #endif
1242
1243 KERNEL_BRK_DESCRIPTOR_DEFINE(clang_desc,
1244 .type = KERNEL_BRK_TYPE_CLANG,
1245 .base = CLANG_ARM_TRAP_START,
1246 .max = CLANG_ARM_TRAP_END,
1247 .options = KERNEL_BRK_UNRECOVERABLE,
1248 .handle_breakpoint = NULL);
1249
1250 KERNEL_BRK_DESCRIPTOR_DEFINE(libcxx_desc,
1251 .type = KERNEL_BRK_TYPE_LIBCXX,
1252 .base = LIBCXX_TRAP_START,
1253 .max = LIBCXX_TRAP_END,
1254 .options = KERNEL_BRK_UNRECOVERABLE,
1255 .handle_breakpoint = NULL);
1256
1257 #if HAS_TELEMETRY_KERNEL_BRK
1258 KERNEL_BRK_DESCRIPTOR_DEFINE(xnu_soft_traps_desc,
1259 .type = KERNEL_BRK_TYPE_TELEMETRY,
1260 .base = XNU_SOFT_TRAP_START,
1261 .max = XNU_SOFT_TRAP_END,
1262 .options = KERNEL_BRK_RECOVERABLE | KERNEL_BRK_CORE_ANALYTICS,
1263 .handle_breakpoint = xnu_soft_trap_handle_breakpoint);
1264 #endif /* HAS_TELEMETRY_KERNEL_BRK */
1265
1266 KERNEL_BRK_DESCRIPTOR_DEFINE(xnu_hard_traps_desc,
1267 .type = KERNEL_BRK_TYPE_XNU,
1268 .base = XNU_HARD_TRAP_START,
1269 .max = XNU_HARD_TRAP_END,
1270 .options = KERNEL_BRK_UNRECOVERABLE,
1271 .handle_breakpoint = xnu_hard_trap_handle_breakpoint);
1272
1273 static void
1274 #if !HAS_TELEMETRY_KERNEL_BRK
1275 __attribute__((noreturn))
1276 #endif
handle_kernel_breakpoint(arm_saved_state_t * state,uint64_t esr)1277 handle_kernel_breakpoint(arm_saved_state_t *state, uint64_t esr)
1278 {
1279 uint16_t comment = ISS_BRK_COMMENT(esr);
1280 const struct kernel_brk_descriptor *desc;
1281
1282 #define MSG_FMT "Break 0x%04X instruction exception from kernel. Panic (by design)"
1283 char msg[strlen(MSG_FMT) - strlen("0x%04X") + strlen("0xFFFF") + 1];
1284
1285 desc = find_brk_descriptor_by_comment(comment);
1286
1287 if (!desc) {
1288 goto brk_out;
1289 }
1290
1291 #if HAS_TELEMETRY_KERNEL_BRK
1292 if (desc->options & KERNEL_BRK_TELEMETRY_OPTIONS) {
1293 telemetry_kernel_brk(desc->type, desc->options, (void *)state, comment);
1294 }
1295 #endif
1296
1297 if (desc->handle_breakpoint) {
1298 desc->handle_breakpoint(state, comment); /* May trigger panic */
1299 }
1300
1301 #if HAS_TELEMETRY_KERNEL_BRK
1302 /* Still alive? Check if we should recover. */
1303 if (desc->options & KERNEL_BRK_RECOVERABLE) {
1304 add_saved_state_pc(state, 4);
1305 return;
1306 }
1307 #endif
1308
1309 brk_out:
1310 snprintf(msg, sizeof(msg), MSG_FMT, comment);
1311
1312 panic_with_thread_kernel_state(msg, state);
1313 __builtin_unreachable();
1314 #undef MSG_FMT
1315 }
1316
1317 static void
handle_breakpoint(arm_saved_state_t * state,uint64_t esr __unused)1318 handle_breakpoint(arm_saved_state_t *state, uint64_t esr __unused)
1319 {
1320 exception_type_t exception = EXC_BREAKPOINT;
1321 mach_exception_data_type_t codes[2] = {EXC_ARM_BREAKPOINT};
1322 mach_msg_type_number_t numcodes = 2;
1323
1324 #if __has_feature(ptrauth_calls)
1325 if (ESR_EC(esr) == ESR_EC_BRK_AARCH64 &&
1326 brk_comment_is_ptrauth(ISS_BRK_COMMENT(esr))) {
1327 exception |= EXC_PTRAUTH_BIT;
1328 }
1329 #endif /* __has_feature(ptrauth_calls) */
1330
1331 codes[1] = get_saved_state_pc(state);
1332 exception_triage(exception, codes, numcodes);
1333 __builtin_unreachable();
1334 }
1335
1336 static void
handle_watchpoint(vm_offset_t fault_addr)1337 handle_watchpoint(vm_offset_t fault_addr)
1338 {
1339 exception_type_t exception = EXC_BREAKPOINT;
1340 mach_exception_data_type_t codes[2] = {EXC_ARM_DA_DEBUG};
1341 mach_msg_type_number_t numcodes = 2;
1342
1343 codes[1] = fault_addr;
1344 exception_triage(exception, codes, numcodes);
1345 __builtin_unreachable();
1346 }
1347
1348 static void
handle_abort(arm_saved_state_t * state,uint64_t esr,vm_offset_t fault_addr,abort_inspector_t inspect_abort,abort_handler_t handler,expected_fault_handler_t expected_fault_handler)1349 handle_abort(arm_saved_state_t *state, uint64_t esr, vm_offset_t fault_addr,
1350 abort_inspector_t inspect_abort, abort_handler_t handler, expected_fault_handler_t expected_fault_handler)
1351 {
1352 fault_status_t fault_code;
1353 vm_prot_t fault_type;
1354
1355 inspect_abort(ESR_ISS(esr), &fault_code, &fault_type);
1356 handler(state, esr, fault_addr, fault_code, fault_type, expected_fault_handler);
1357 }
1358
1359 static void
inspect_instruction_abort(uint32_t iss,fault_status_t * fault_code,vm_prot_t * fault_type)1360 inspect_instruction_abort(uint32_t iss, fault_status_t *fault_code, vm_prot_t *fault_type)
1361 {
1362 getCpuDatap()->cpu_stat.instr_ex_cnt++;
1363 *fault_code = ISS_IA_FSC(iss);
1364 *fault_type = (VM_PROT_READ | VM_PROT_EXECUTE);
1365 }
1366
1367 static void
inspect_data_abort(uint32_t iss,fault_status_t * fault_code,vm_prot_t * fault_type)1368 inspect_data_abort(uint32_t iss, fault_status_t *fault_code, vm_prot_t *fault_type)
1369 {
1370 getCpuDatap()->cpu_stat.data_ex_cnt++;
1371 *fault_code = ISS_DA_FSC(iss);
1372
1373 /*
1374 * Cache maintenance operations always report faults as write access.
1375 * Change these to read access, unless they report a permission fault.
1376 * Only certain cache maintenance operations (e.g. 'dc ivac') require write
1377 * access to the mapping, but if a cache maintenance operation that only requires
1378 * read access generates a permission fault, then we will not be able to handle
1379 * the fault regardless of whether we treat it as a read or write fault.
1380 */
1381 if ((iss & ISS_DA_WNR) && (!(iss & ISS_DA_CM) || is_permission_fault(*fault_code))) {
1382 *fault_type = (VM_PROT_READ | VM_PROT_WRITE);
1383 } else {
1384 *fault_type = (VM_PROT_READ);
1385 }
1386 }
1387
1388 #if __has_feature(ptrauth_calls)
1389 static inline uint64_t
fault_addr_bitmask(unsigned int bit_from,unsigned int bit_to)1390 fault_addr_bitmask(unsigned int bit_from, unsigned int bit_to)
1391 {
1392 return ((1ULL << (bit_to - bit_from + 1)) - 1) << bit_from;
1393 }
1394
1395 static inline bool
fault_addr_bit(vm_offset_t fault_addr,unsigned int bit)1396 fault_addr_bit(vm_offset_t fault_addr, unsigned int bit)
1397 {
1398 return (bool)((fault_addr >> bit) & 1);
1399 }
1400
1401 extern int gARM_FEAT_PAuth2;
1402
1403 /**
1404 * Determines whether a fault address taken at EL0 contains a PAC error code
1405 * corresponding to the specified kind of ptrauth key.
1406 */
1407 static bool
user_fault_addr_matches_pac_error_code(vm_offset_t fault_addr,bool data_key)1408 user_fault_addr_matches_pac_error_code(vm_offset_t fault_addr, bool data_key)
1409 {
1410 bool instruction_tbi = !(get_tcr() & TCR_TBID0_TBI_DATA_ONLY);
1411 bool tbi = data_key || __improbable(instruction_tbi);
1412
1413 if (gARM_FEAT_PAuth2) {
1414 /*
1415 * EnhancedPAC2 CPUs don't encode error codes at fixed positions, so
1416 * treat all non-canonical address bits like potential poison bits.
1417 */
1418 uint64_t mask = fault_addr_bitmask(64 - T0SZ_BOOT, 54);
1419 if (!tbi) {
1420 mask |= fault_addr_bitmask(56, 63);
1421 }
1422 return (fault_addr & mask) != 0;
1423 } else {
1424 unsigned int poison_shift;
1425 if (tbi) {
1426 poison_shift = 53;
1427 } else {
1428 poison_shift = 61;
1429 }
1430
1431 /* PAC error codes are always in the form key_number:NOT(key_number) */
1432 bool poison_bit_1 = fault_addr_bit(fault_addr, poison_shift);
1433 bool poison_bit_2 = fault_addr_bit(fault_addr, poison_shift + 1);
1434 return poison_bit_1 != poison_bit_2;
1435 }
1436 }
1437 #endif /* __has_feature(ptrauth_calls) */
1438
1439 /**
1440 * Determines whether the userland thread has a JIT region in RW mode, TPRO
1441 * in RW mode, or JCTL_EL0 in pointer signing mode. A fault in any of these trusted
1442 * code paths may indicate an attack on WebKit. Rather than letting a
1443 * potentially-compromised process try to handle the exception, it will be killed
1444 * by the kernel and a crash report will be generated.
1445 */
1446 static bool
user_fault_in_self_restrict_mode(thread_t thread __unused)1447 user_fault_in_self_restrict_mode(thread_t thread __unused)
1448 {
1449
1450 return false;
1451 }
1452
1453 static void
handle_pc_align(arm_saved_state_t * ss)1454 handle_pc_align(arm_saved_state_t *ss)
1455 {
1456 exception_type_t exc;
1457 mach_exception_data_type_t codes[2];
1458 mach_msg_type_number_t numcodes = 2;
1459
1460 if (!PSR64_IS_USER(get_saved_state_cpsr(ss))) {
1461 panic_with_thread_kernel_state("PC alignment exception from kernel.", ss);
1462 }
1463
1464 exc = EXC_BAD_ACCESS;
1465 #if __has_feature(ptrauth_calls)
1466 if (user_fault_addr_matches_pac_error_code(get_saved_state_pc(ss), false)) {
1467 exc |= EXC_PTRAUTH_BIT;
1468 }
1469 #endif /* __has_feature(ptrauth_calls) */
1470
1471 codes[0] = EXC_ARM_DA_ALIGN;
1472 codes[1] = get_saved_state_pc(ss);
1473
1474 exception_triage(exc, codes, numcodes);
1475 __builtin_unreachable();
1476 }
1477
1478 static void
handle_sp_align(arm_saved_state_t * ss)1479 handle_sp_align(arm_saved_state_t *ss)
1480 {
1481 exception_type_t exc;
1482 mach_exception_data_type_t codes[2];
1483 mach_msg_type_number_t numcodes = 2;
1484
1485 if (!PSR64_IS_USER(get_saved_state_cpsr(ss))) {
1486 panic_with_thread_kernel_state("SP alignment exception from kernel.", ss);
1487 }
1488
1489 exc = EXC_BAD_ACCESS;
1490 #if __has_feature(ptrauth_calls)
1491 if (user_fault_addr_matches_pac_error_code(get_saved_state_sp(ss), true)) {
1492 exc |= EXC_PTRAUTH_BIT;
1493 }
1494 #endif /* __has_feature(ptrauth_calls) */
1495
1496 codes[0] = EXC_ARM_SP_ALIGN;
1497 codes[1] = get_saved_state_sp(ss);
1498
1499 exception_triage(exc, codes, numcodes);
1500 __builtin_unreachable();
1501 }
1502
1503 static void
handle_wf_trap(arm_saved_state_t * state)1504 handle_wf_trap(arm_saved_state_t *state)
1505 {
1506 exception_type_t exc;
1507 mach_exception_data_type_t codes[2];
1508 mach_msg_type_number_t numcodes = 2;
1509 uint32_t instr = 0;
1510
1511 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1512
1513 exc = EXC_BAD_INSTRUCTION;
1514 codes[0] = EXC_ARM_UNDEFINED;
1515 codes[1] = instr;
1516
1517 exception_triage(exc, codes, numcodes);
1518 __builtin_unreachable();
1519 }
1520
1521 static void
handle_fp_trap(arm_saved_state_t * state,uint64_t esr)1522 handle_fp_trap(arm_saved_state_t *state, uint64_t esr)
1523 {
1524 exception_type_t exc = EXC_ARITHMETIC;
1525 mach_exception_data_type_t codes[2];
1526 mach_msg_type_number_t numcodes = 2;
1527 uint32_t instr = 0;
1528
1529 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
1530 panic_with_thread_kernel_state("Floating point exception from kernel", state);
1531 }
1532
1533 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1534 codes[1] = instr;
1535
1536 /* The floating point trap flags are only valid if TFV is set. */
1537 if (!fp_exceptions_enabled) {
1538 exc = EXC_BAD_INSTRUCTION;
1539 codes[0] = EXC_ARM_UNDEFINED;
1540 } else if (!(esr & ISS_FP_TFV)) {
1541 codes[0] = EXC_ARM_FP_UNDEFINED;
1542 } else if (esr & ISS_FP_UFF) {
1543 codes[0] = EXC_ARM_FP_UF;
1544 } else if (esr & ISS_FP_OFF) {
1545 codes[0] = EXC_ARM_FP_OF;
1546 } else if (esr & ISS_FP_IOF) {
1547 codes[0] = EXC_ARM_FP_IO;
1548 } else if (esr & ISS_FP_DZF) {
1549 codes[0] = EXC_ARM_FP_DZ;
1550 } else if (esr & ISS_FP_IDF) {
1551 codes[0] = EXC_ARM_FP_ID;
1552 } else if (esr & ISS_FP_IXF) {
1553 codes[0] = EXC_ARM_FP_IX;
1554 } else {
1555 panic("Unrecognized floating point exception, state=%p, esr=%#llx", state, esr);
1556 }
1557
1558 exception_triage(exc, codes, numcodes);
1559 __builtin_unreachable();
1560 }
1561
1562
1563
1564 /*
1565 * handle_alignment_fault_from_user:
1566 * state: Saved state
1567 *
1568 * Attempts to deal with an alignment fault from userspace (possibly by
1569 * emulating the faulting instruction). If emulation failed due to an
1570 * unservicable fault, the ESR for that fault will be stored in the
1571 * recovery_esr field of the thread by the exception code.
1572 *
1573 * Returns:
1574 * -1: Emulation failed (emulation of state/instr not supported)
1575 * 0: Successfully emulated the instruction
1576 * EFAULT: Emulation failed (probably due to permissions)
1577 * EINVAL: Emulation failed (probably due to a bad address)
1578 */
1579
1580
1581 static int
handle_alignment_fault_from_user(arm_saved_state_t * state,kern_return_t * vmfr)1582 handle_alignment_fault_from_user(arm_saved_state_t *state, kern_return_t *vmfr)
1583 {
1584 int ret = -1;
1585
1586 #pragma unused (state)
1587 #pragma unused (vmfr)
1588
1589 return ret;
1590 }
1591
1592
1593
1594 #if HAS_ARM_FEAT_SME
1595 static void
handle_sme_trap(arm_saved_state_t * state,uint64_t esr)1596 handle_sme_trap(arm_saved_state_t *state, uint64_t esr)
1597 {
1598 exception_type_t exc = EXC_BAD_INSTRUCTION;
1599 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
1600 mach_msg_type_number_t numcodes = 2;
1601
1602 if (!PSR64_IS_USER(get_saved_state_cpsr(state))) {
1603 panic("SME exception from kernel, state=%p, esr=%#llx", state, esr);
1604 }
1605 if (!arm_sme_version()) {
1606 /*
1607 * If SME is disabled in software but userspace executes an SME
1608 * instruction anyway, then the CPU will still raise an
1609 * SME-specific trap. Triage it as if the CPU raised an
1610 * undefined-instruction trap.
1611 */
1612 exception_triage(exc, codes, numcodes);
1613 __builtin_unreachable();
1614 }
1615
1616 if (ISS_SME_SMTC(ESR_ISS(esr)) == ISS_SME_SMTC_CAPCR) {
1617 thread_t thread = current_thread();
1618 switch (machine_thread_sme_state_alloc(thread)) {
1619 case KERN_SUCCESS:
1620 return;
1621
1622
1623 default:
1624 panic("Failed to allocate SME state for thread %p", thread);
1625 }
1626 }
1627
1628 uint32_t instr;
1629 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1630 codes[1] = instr;
1631
1632 exception_triage(exc, codes, numcodes);
1633 __builtin_unreachable();
1634 }
1635 #endif /* HAS_ARM_FEAT_SME */
1636
1637 static void
handle_sw_step_debug(arm_saved_state_t * state)1638 handle_sw_step_debug(arm_saved_state_t *state)
1639 {
1640 thread_t thread = current_thread();
1641 exception_type_t exc;
1642 mach_exception_data_type_t codes[2];
1643 mach_msg_type_number_t numcodes = 2;
1644
1645 if (!PSR64_IS_USER(get_saved_state_cpsr(state))) {
1646 panic_with_thread_kernel_state("SW_STEP_DEBUG exception from kernel.", state);
1647 }
1648
1649 // Disable single step and unmask interrupts (in the saved state, anticipating next exception return)
1650 if (thread->machine.DebugData != NULL) {
1651 thread->machine.DebugData->uds.ds64.mdscr_el1 &= ~0x1;
1652 } else {
1653 panic_with_thread_kernel_state("SW_STEP_DEBUG exception thread DebugData is NULL.", state);
1654 }
1655
1656 mask_user_saved_state_cpsr(thread->machine.upcb, 0, PSR64_SS | DAIF_ALL);
1657
1658 // Special encoding for gdb single step event on ARM
1659 exc = EXC_BREAKPOINT;
1660 codes[0] = 1;
1661 codes[1] = 0;
1662
1663 exception_triage(exc, codes, numcodes);
1664 __builtin_unreachable();
1665 }
1666
1667 #if MACH_ASSERT
1668 TUNABLE_WRITEABLE(int, panic_on_jit_guard, "panic_on_jit_guard", 0);
1669 #endif /* MACH_ASSERT */
1670
1671 static void
handle_user_abort(arm_saved_state_t * state,uint64_t esr,vm_offset_t fault_addr,fault_status_t fault_code,vm_prot_t fault_type,expected_fault_handler_t expected_fault_handler)1672 handle_user_abort(arm_saved_state_t *state, uint64_t esr, vm_offset_t fault_addr,
1673 fault_status_t fault_code, vm_prot_t fault_type, expected_fault_handler_t expected_fault_handler)
1674 {
1675 exception_type_t exc = EXC_BAD_ACCESS;
1676 mach_exception_data_type_t codes[2];
1677 mach_msg_type_number_t numcodes = 2;
1678 thread_t thread = current_thread();
1679
1680 (void)expected_fault_handler;
1681
1682 if (__improbable(!SPSR_INTERRUPTS_ENABLED(get_saved_state_cpsr(state)))) {
1683 panic_with_thread_kernel_state("User abort from non-interruptible context", state);
1684 }
1685
1686 thread->iotier_override = THROTTLE_LEVEL_NONE; /* Reset IO tier override before handling abort from userspace */
1687
1688 if (!is_servicible_fault(fault_code, esr) &&
1689 thread->t_rr_state.trr_fault_state != TRR_FAULT_NONE) {
1690 thread_reset_pcs_done_faulting(thread);
1691 }
1692
1693 if (is_vm_fault(fault_code)) {
1694 vm_map_t map = thread->map;
1695 vm_offset_t vm_fault_addr = fault_addr;
1696 kern_return_t result = KERN_FAILURE;
1697
1698 assert(map != kernel_map);
1699
1700 if (!(fault_type & VM_PROT_EXECUTE)) {
1701 vm_fault_addr = VM_USER_STRIP_TBI(fault_addr);
1702 }
1703
1704 /* check to see if it is just a pmap ref/modify fault */
1705 if (!is_translation_fault(fault_code)) {
1706 result = arm_fast_fault(map->pmap,
1707 vm_fault_addr,
1708 fault_type, (fault_code == FSC_ACCESS_FLAG_FAULT_L3), TRUE);
1709 }
1710 if (result != KERN_SUCCESS) {
1711
1712 {
1713 /* We have to fault the page in */
1714 result = vm_fault(map, vm_fault_addr, fault_type,
1715 /* change_wiring */ FALSE, VM_KERN_MEMORY_NONE, THREAD_ABORTSAFE,
1716 /* caller_pmap */ NULL, /* caller_pmap_addr */ 0);
1717 }
1718 }
1719 if (thread->t_rr_state.trr_fault_state != TRR_FAULT_NONE) {
1720 thread_reset_pcs_done_faulting(thread);
1721 }
1722 if (result == KERN_SUCCESS || result == KERN_ABORTED) {
1723 return;
1724 }
1725
1726 /*
1727 * vm_fault() should never return KERN_FAILURE for page faults from user space.
1728 * If it does, we're leaking preemption disables somewhere in the kernel.
1729 */
1730 if (__improbable(result == KERN_FAILURE)) {
1731 panic("vm_fault() KERN_FAILURE from user fault on thread %p", thread);
1732 }
1733
1734 codes[0] = result;
1735 } else if (is_alignment_fault(fault_code)) {
1736 kern_return_t vmfkr = KERN_SUCCESS;
1737 thread->machine.recover_esr = 0;
1738 thread->machine.recover_far = 0;
1739 int result = handle_alignment_fault_from_user(state, &vmfkr);
1740 if (result == 0) {
1741 /* Successfully emulated, or instruction
1742 * copyin() for decode/emulation failed.
1743 * Continue, or redrive instruction.
1744 */
1745 thread_exception_return();
1746 } else if (((result == EFAULT) || (result == EINVAL)) &&
1747 (thread->machine.recover_esr == 0)) {
1748 /*
1749 * If we didn't actually take a fault, but got one of
1750 * these errors, then we failed basic sanity checks of
1751 * the fault address. Treat this as an invalid
1752 * address.
1753 */
1754 codes[0] = KERN_INVALID_ADDRESS;
1755 } else if ((result == EFAULT) &&
1756 (thread->machine.recover_esr)) {
1757 /*
1758 * Since alignment aborts are prioritized
1759 * ahead of translation aborts, the misaligned
1760 * atomic emulation flow may have triggered a
1761 * VM pagefault, which the VM could not resolve.
1762 * Report the VM fault error in codes[]
1763 */
1764
1765 codes[0] = vmfkr;
1766 assertf(vmfkr != KERN_SUCCESS, "Unexpected vmfkr 0x%x", vmfkr);
1767 /* Cause ESR_EC to reflect an EL0 abort */
1768 thread->machine.recover_esr &= ~ESR_EC_MASK;
1769 thread->machine.recover_esr |= (ESR_EC_DABORT_EL0 << ESR_EC_SHIFT);
1770 set_saved_state_esr(thread->machine.upcb, thread->machine.recover_esr);
1771 set_saved_state_far(thread->machine.upcb, thread->machine.recover_far);
1772 fault_addr = thread->machine.recover_far;
1773 } else {
1774 /* This was just an unsupported alignment
1775 * exception. Misaligned atomic emulation
1776 * timeouts fall in this category.
1777 */
1778 codes[0] = EXC_ARM_DA_ALIGN;
1779 }
1780 } else if (is_parity_error(fault_code)) {
1781 #if defined(APPLE_ARM64_ARCH_FAMILY)
1782 /*
1783 * Platform errors are handled in sleh_sync before interrupts are enabled.
1784 */
1785 #else
1786 panic("User parity error.");
1787 #endif
1788 } else {
1789 codes[0] = KERN_FAILURE;
1790 }
1791
1792 #if CODE_SIGNING_MONITOR
1793 /*
1794 * If the code reaches here, it means we weren't able to resolve the fault and we're
1795 * going to be sending the task an exception. On systems which have the code signing
1796 * monitor enabled, an execute fault which cannot be handled must result in sending
1797 * a SIGKILL to the task.
1798 */
1799 if (is_vm_fault(fault_code) && (fault_type & VM_PROT_EXECUTE)) {
1800 csm_code_signing_violation(current_proc(), fault_addr);
1801 }
1802 #endif
1803
1804 codes[1] = fault_addr;
1805 #if __has_feature(ptrauth_calls)
1806 bool is_data_abort = (ESR_EC(esr) == ESR_EC_DABORT_EL0);
1807 if (user_fault_addr_matches_pac_error_code(fault_addr, is_data_abort)) {
1808 exc |= EXC_PTRAUTH_BIT;
1809 }
1810 #endif /* __has_feature(ptrauth_calls) */
1811
1812 if (user_fault_in_self_restrict_mode(thread) &&
1813 task_is_jit_exception_fatal(get_threadtask(thread))) {
1814 int flags = PX_KTRIAGE;
1815 exception_info_t info = {
1816 .os_reason = OS_REASON_SELF_RESTRICT,
1817 .exception_type = exc,
1818 .mx_code = codes[0],
1819 .mx_subcode = codes[1]
1820 };
1821
1822 #if MACH_ASSERT
1823 printf("\nGUARD_REASON_JIT exc %d codes=<0x%llx,0x%llx> syscalls %d task %p thread %p va 0x%lx code 0x%x type 0x%x esr 0x%llx\n",
1824 exc, codes[0], codes[1], thread->syscalls_unix, current_task(), thread, fault_addr, fault_code, fault_type, esr);
1825 if (panic_on_jit_guard &&
1826 current_task()->thread_count == 1 &&
1827 thread->syscalls_unix < 24) {
1828 panic("GUARD_REASON_JIT exc %d codes=<0x%llx,0x%llx> syscalls %d task %p thread %p va 0x%lx code 0x%x type 0x%x esr 0x%llx state %p j %d t %d s user 0x%llx (0x%llx) jb 0x%llx (0x%llx)",
1829 exc, codes[0], codes[1], thread->syscalls_unix, current_task(), thread, fault_addr, fault_code, fault_type, esr, state,
1830 0, 0, 0ull, 0ull,
1831 0ull, 0ull
1832 );
1833 }
1834 #endif /* MACH_ASSERT */
1835
1836 exit_with_mach_exception(current_proc(), info, flags);
1837 }
1838
1839 exception_triage(exc, codes, numcodes);
1840 __builtin_unreachable();
1841 }
1842
1843 /**
1844 * Panic because the kernel abort handler tried to apply a recovery handler that
1845 * isn't inside copyio_recover_table[].
1846 *
1847 * @param state original saved-state
1848 * @param recover invalid recovery handler
1849 */
1850 __attribute__((noreturn, used))
1851 static void
panic_on_invalid_recovery_handler(arm_saved_state_t * state,struct copyio_recovery_entry * recover)1852 panic_on_invalid_recovery_handler(arm_saved_state_t *state, struct copyio_recovery_entry *recover)
1853 {
1854 panic("attempt to set invalid recovery handler %p on kernel saved-state %p", recover, state);
1855 }
1856
1857 static void
handle_kernel_abort_recover(arm_saved_state_t * state,uint64_t esr,vm_offset_t fault_addr,thread_t thread,struct copyio_recovery_entry * _Nonnull recover)1858 handle_kernel_abort_recover(
1859 arm_saved_state_t *state,
1860 uint64_t esr,
1861 vm_offset_t fault_addr,
1862 thread_t thread,
1863 struct copyio_recovery_entry *_Nonnull recover)
1864 {
1865 thread->machine.recover_esr = esr;
1866 thread->machine.recover_far = fault_addr;
1867 #if defined(HAS_APPLE_PAC)
1868 MANIPULATE_SIGNED_THREAD_STATE(state,
1869 "adrp x6, _copyio_recover_table_end@page \n"
1870 "add x6, x6, _copyio_recover_table_end@pageoff \n"
1871 "cmp %[recover], x6 \n"
1872 "b.lt 1f \n"
1873 "bl _panic_on_invalid_recovery_handler \n"
1874 "brk #0 \n"
1875 "1: \n"
1876 "adrp x6, _copyio_recover_table@page \n"
1877 "add x6, x6, _copyio_recover_table@pageoff \n"
1878 "cmp %[recover], x6 \n"
1879 "b.ge 1f \n"
1880 "bl _panic_on_invalid_recovery_handler \n"
1881 "brk #0 \n"
1882 "1: \n"
1883 "ldr x1, [%[recover], %[CRE_RECOVERY]] \n"
1884 "add x1, x1, x6 \n"
1885 "str x1, [x0, %[SS64_PC]] \n",
1886 [recover] "r"(recover),
1887 [CRE_RECOVERY] "i"(offsetof(struct copyio_recovery_entry, cre_recovery))
1888 );
1889 #else
1890 if ((uintptr_t)recover < (uintptr_t)copyio_recover_table ||
1891 (uintptr_t)recover >= (uintptr_t)copyio_recover_table_end) {
1892 panic_on_invalid_recovery_handler(state, recover);
1893 }
1894 saved_state64(state)->pc = copyio_recovery_addr(recover->cre_recovery);
1895 #endif
1896 }
1897
1898 static void
handle_kernel_abort(arm_saved_state_t * state,uint64_t esr,vm_offset_t fault_addr,fault_status_t fault_code,vm_prot_t fault_type,expected_fault_handler_t expected_fault_handler)1899 handle_kernel_abort(arm_saved_state_t *state, uint64_t esr, vm_offset_t fault_addr,
1900 fault_status_t fault_code, vm_prot_t fault_type, expected_fault_handler_t expected_fault_handler)
1901 {
1902 thread_t thread = current_thread();
1903 struct copyio_recovery_entry *recover = find_copyio_recovery_entry(state);
1904
1905 #ifndef CONFIG_XNUPOST
1906 (void)expected_fault_handler;
1907 #endif /* CONFIG_XNUPOST */
1908
1909 #if CONFIG_DTRACE
1910 if (is_vm_fault(fault_code) && thread->t_dtrace_inprobe) { /* Executing under dtrace_probe? */
1911 if (dtrace_tally_fault(fault_addr)) { /* Should a fault under dtrace be ignored? */
1912 /*
1913 * Point to next instruction, or recovery handler if set.
1914 */
1915 if (recover) {
1916 handle_kernel_abort_recover(state, esr, VM_USER_STRIP_PTR(fault_addr), thread, recover);
1917 } else {
1918 add_saved_state_pc(state, 4);
1919 }
1920 return;
1921 } else {
1922 panic_with_thread_kernel_state("Unexpected page fault under dtrace_probe", state);
1923 }
1924 }
1925 #endif
1926
1927 if (is_vm_fault(fault_code)) {
1928 kern_return_t result = KERN_FAILURE;
1929 vm_map_t map;
1930 int interruptible;
1931
1932 /*
1933 * Ensure no faults in the physical aperture. This could happen if
1934 * a page table is incorrectly allocated from the read only region
1935 * when running with KTRR.
1936 */
1937
1938 #ifdef CONFIG_XNUPOST
1939 if (expected_fault_handler && expected_fault_handler(state)) {
1940 return;
1941 }
1942 #endif /* CONFIG_XNUPOST */
1943
1944 if (fault_addr >= gVirtBase && fault_addr < static_memory_end) {
1945 panic_with_thread_kernel_state("Unexpected fault in kernel static region\n", state);
1946 }
1947
1948 if (VM_KERNEL_ADDRESS(fault_addr) || thread == THREAD_NULL || recover == 0) {
1949 /*
1950 * If no recovery handler is supplied, always drive the fault against
1951 * the kernel map. If the fault was taken against a userspace VA, indicating
1952 * an unprotected access to user address space, vm_fault() should fail and
1953 * ultimately lead to a panic here.
1954 */
1955 map = kernel_map;
1956 interruptible = THREAD_UNINT;
1957
1958 #if CONFIG_KERNEL_TAGGING
1959 /*
1960 * If kernel tagging is enabled, canonicalize the address here, so that we have a
1961 * chance to find it in the VM ranges. Do not mess with exec fault cases.
1962 */
1963 if (!((fault_type) & VM_PROT_EXECUTE)) {
1964 fault_addr = vm_memtag_canonicalize_address(fault_addr);
1965 }
1966 #endif /* CONFIG_KERNEL_TAGGING */
1967 } else {
1968 map = thread->map;
1969
1970 /**
1971 * In the case that the recovery handler is set (e.g., during copyio
1972 * and dtrace probes), we don't want the vm_fault() operation to be
1973 * aborted early. Those code paths can't handle restarting the
1974 * vm_fault() operation so don't allow it to return early without
1975 * creating the wanted mapping.
1976 */
1977 interruptible = (recover) ? THREAD_UNINT : THREAD_ABORTSAFE;
1978
1979 }
1980
1981 if (fault_addr >= gVirtBase && fault_addr < static_memory_end) {
1982 panic_with_thread_kernel_state("Unexpected fault in kernel static region\n", state);
1983 }
1984
1985 /* check to see if it is just a pmap ref/modify fault */
1986 if (!is_translation_fault(fault_code)) {
1987 result = arm_fast_fault(map->pmap,
1988 fault_addr,
1989 fault_type, (fault_code == FSC_ACCESS_FLAG_FAULT_L3), FALSE);
1990 if (result == KERN_SUCCESS) {
1991 return;
1992 }
1993 }
1994
1995 /**
1996 * vm_fault() can be called with preemption disabled (and indeed this is expected for
1997 * certain copyio() scenarios), but can't safely be called with interrupts disabled once
1998 * the system has gone multi-threaded. Other than some early-boot situations such as
1999 * startup kext loading, kernel paging operations should never be triggered by
2000 * non-interruptible code in the first place, so a fault from such a context will
2001 * ultimately produce a kernel data abort panic anyway. In these cases, skip calling
2002 * vm_fault() to avoid masking the real kernel panic with a failed VM locking assertion.
2003 */
2004 if (__probable(SPSR_INTERRUPTS_ENABLED(get_saved_state_cpsr(state)) ||
2005 startup_phase < STARTUP_SUB_EARLY_BOOT ||
2006 current_cpu_datap()->cpu_hibernate)) {
2007 if (result != KERN_PROTECTION_FAILURE) {
2008 // VM will query this property when deciding to throttle this fault, we don't want to
2009 // throttle kernel faults for copyio faults. The presence of a recovery entry is used as a
2010 // proxy for being in copyio code.
2011 bool const was_recover = thread->recover;
2012 thread->recover = was_recover || recover;
2013
2014 /*
2015 * We have to "fault" the page in.
2016 */
2017 result = vm_fault(map, fault_addr, fault_type,
2018 /* change_wiring */ FALSE, VM_KERN_MEMORY_NONE, interruptible,
2019 /* caller_pmap */ NULL, /* caller_pmap_addr */ 0);
2020
2021 thread->recover = was_recover;
2022 }
2023
2024 if (result == KERN_SUCCESS) {
2025 return;
2026 }
2027 }
2028
2029 /*
2030 * If we have a recover handler, invoke it now.
2031 */
2032 if (recover) {
2033 handle_kernel_abort_recover(state, esr, fault_addr, thread, recover);
2034 return;
2035 }
2036
2037 panic_fault_address = fault_addr;
2038 } else if (is_alignment_fault(fault_code)) {
2039 if (recover) {
2040 handle_kernel_abort_recover(state, esr, fault_addr, thread, recover);
2041 return;
2042 }
2043 panic_with_thread_kernel_state("Unaligned kernel data abort.", state);
2044 } else if (is_parity_error(fault_code)) {
2045 #if defined(APPLE_ARM64_ARCH_FAMILY)
2046 /*
2047 * Platform errors are handled in sleh_sync before interrupts are enabled.
2048 */
2049 #else
2050 panic_with_thread_kernel_state("Kernel parity error.", state);
2051 #endif
2052 } else {
2053 kprintf("Unclassified kernel abort (fault_code=0x%x)\n", fault_code);
2054 }
2055
2056 panic_with_thread_kernel_state("Kernel data abort.", state);
2057 }
2058
2059 extern void syscall_trace(struct arm_saved_state * regs);
2060
2061 static void
handle_svc(arm_saved_state_t * state)2062 handle_svc(arm_saved_state_t *state)
2063 {
2064 int trap_no = get_saved_state_svc_number(state);
2065 thread_t thread = current_thread();
2066 struct proc *p;
2067
2068 #define handle_svc_kprintf(x...) /* kprintf("handle_svc: " x) */
2069
2070 #define TRACE_SYSCALL 1
2071 #if TRACE_SYSCALL
2072 syscall_trace(state);
2073 #endif
2074
2075 thread->iotier_override = THROTTLE_LEVEL_NONE; /* Reset IO tier override before handling SVC from userspace */
2076
2077 if (trap_no == (int)PLATFORM_SYSCALL_TRAP_NO) {
2078 platform_syscall(state);
2079 panic("Returned from platform_syscall()?");
2080 }
2081
2082 current_cached_proc_cred_update();
2083
2084 if (trap_no < 0) {
2085 switch (trap_no) {
2086 case MACH_ARM_TRAP_ABSTIME:
2087 handle_mach_absolute_time_trap(state);
2088 return;
2089 case MACH_ARM_TRAP_CONTTIME:
2090 handle_mach_continuous_time_trap(state);
2091 return;
2092 }
2093
2094 /* Counting perhaps better in the handler, but this is how it's been done */
2095 thread->syscalls_mach++;
2096 mach_syscall(state);
2097 } else {
2098 /* Counting perhaps better in the handler, but this is how it's been done */
2099 thread->syscalls_unix++;
2100 p = get_bsdthreadtask_info(thread);
2101
2102 assert(p);
2103
2104 unix_syscall(state, thread, p);
2105 }
2106 }
2107
2108 static void
handle_mach_absolute_time_trap(arm_saved_state_t * state)2109 handle_mach_absolute_time_trap(arm_saved_state_t *state)
2110 {
2111 uint64_t now = mach_absolute_time();
2112 saved_state64(state)->x[0] = now;
2113 }
2114
2115 static void
handle_mach_continuous_time_trap(arm_saved_state_t * state)2116 handle_mach_continuous_time_trap(arm_saved_state_t *state)
2117 {
2118 uint64_t now = mach_continuous_time();
2119 saved_state64(state)->x[0] = now;
2120 }
2121
2122
2123 __attribute__((noreturn))
2124 static void
handle_msr_trap(arm_saved_state_t * state,uint64_t esr)2125 handle_msr_trap(arm_saved_state_t *state, uint64_t esr)
2126 {
2127 exception_type_t exception = EXC_BAD_INSTRUCTION;
2128 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
2129 mach_msg_type_number_t numcodes = 2;
2130 uint32_t instr = 0;
2131
2132 if (!is_saved_state64(state)) {
2133 panic("MSR/MRS trap (ESR 0x%llx) from 32-bit state", esr);
2134 }
2135
2136 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
2137 panic("MSR/MRS trap (ESR 0x%llx) from kernel", esr);
2138 }
2139
2140 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
2141 codes[1] = instr;
2142
2143 exception_triage(exception, codes, numcodes);
2144 __builtin_unreachable();
2145 }
2146
2147 #if __has_feature(ptrauth_calls)
2148 static void
stringify_gpr(unsigned int r,char reg[4])2149 stringify_gpr(unsigned int r, char reg[4])
2150 {
2151 switch (r) {
2152 case 29:
2153 strncpy(reg, "fp", 4);
2154 return;
2155
2156 case 30:
2157 strncpy(reg, "lr", 4);
2158 return;
2159
2160 case 31:
2161 strncpy(reg, "xzr", 4);
2162 return;
2163
2164 default:
2165 snprintf(reg, 4, "x%u", r);
2166 return;
2167 }
2168 }
2169
2170 static void
autxx_instruction_extract_reg(uint32_t instr,char reg[4])2171 autxx_instruction_extract_reg(uint32_t instr, char reg[4])
2172 {
2173 unsigned int rd = ARM64_INSTR_AUTxx_RD_GET(instr);
2174 stringify_gpr(rd, reg);
2175 }
2176
2177 static const char *
autix_system_instruction_extract_reg(uint32_t instr)2178 autix_system_instruction_extract_reg(uint32_t instr)
2179 {
2180 unsigned int crm_op2 = ARM64_INSTR_AUTIx_SYSTEM_CRM_OP2_GET(instr);
2181 if (crm_op2 == ARM64_INSTR_AUTIx_SYSTEM_CRM_OP2_AUTIA1716 ||
2182 crm_op2 == ARM64_INSTR_AUTIx_SYSTEM_CRM_OP2_AUTIB1716) {
2183 return "x17";
2184 } else {
2185 return "lr";
2186 }
2187 }
2188
2189 static void
bxrax_instruction_extract_reg(uint32_t instr,char reg[4])2190 bxrax_instruction_extract_reg(uint32_t instr, char reg[4])
2191 {
2192 unsigned int rn = ARM64_INSTR_BxRAx_RN_GET(instr);
2193 stringify_gpr(rn, reg);
2194 }
2195
2196 static void
handle_pac_fail(arm_saved_state_t * state,uint64_t esr)2197 handle_pac_fail(arm_saved_state_t *state, uint64_t esr)
2198 {
2199 exception_type_t exception = EXC_BAD_ACCESS | EXC_PTRAUTH_BIT;
2200 mach_exception_data_type_t codes[2] = {EXC_ARM_PAC_FAIL};
2201 mach_msg_type_number_t numcodes = 2;
2202 uint32_t instr = 0;
2203
2204 if (!is_saved_state64(state)) {
2205 panic("PAC failure (ESR 0x%llx) from 32-bit state", esr);
2206 }
2207
2208 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
2209
2210 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
2211 #define GENERIC_PAC_FAILURE_MSG_FMT "PAC failure from kernel with %s key"
2212 #define AUTXX_MSG_FMT GENERIC_PAC_FAILURE_MSG_FMT " while authing %s"
2213 #define BXRAX_MSG_FMT GENERIC_PAC_FAILURE_MSG_FMT " while branching to %s"
2214 #define RETAX_MSG_FMT GENERIC_PAC_FAILURE_MSG_FMT " while returning"
2215 #define GENERIC_MSG_FMT GENERIC_PAC_FAILURE_MSG_FMT
2216 #define MAX_PAC_MSG_FMT BXRAX_MSG_FMT
2217
2218 char msg[strlen(MAX_PAC_MSG_FMT)
2219 - strlen("%s") + strlen("IA")
2220 - strlen("%s") + strlen("xzr")
2221 + 1];
2222 ptrauth_key key = (ptrauth_key)(esr & 0x3);
2223 const char *key_str = ptrauth_key_to_string(key);
2224
2225 if (ARM64_INSTR_IS_AUTxx(instr)) {
2226 char reg[4];
2227 autxx_instruction_extract_reg(instr, reg);
2228 snprintf(msg, sizeof(msg), AUTXX_MSG_FMT, key_str, reg);
2229 } else if (ARM64_INSTR_IS_AUTIx_SYSTEM(instr)) {
2230 const char *reg = autix_system_instruction_extract_reg(instr);
2231 snprintf(msg, sizeof(msg), AUTXX_MSG_FMT, key_str, reg);
2232 } else if (ARM64_INSTR_IS_BxRAx(instr)) {
2233 char reg[4];
2234 bxrax_instruction_extract_reg(instr, reg);
2235 snprintf(msg, sizeof(msg), BXRAX_MSG_FMT, key_str, reg);
2236 } else if (ARM64_INSTR_IS_RETAx(instr)) {
2237 snprintf(msg, sizeof(msg), RETAX_MSG_FMT, key_str);
2238 } else {
2239 snprintf(msg, sizeof(msg), GENERIC_MSG_FMT, key_str);
2240 }
2241 panic_with_thread_kernel_state(msg, state);
2242 }
2243
2244 codes[1] = instr;
2245
2246 exception_triage(exception, codes, numcodes);
2247 __builtin_unreachable();
2248 }
2249 #endif /* __has_feature(ptrauth_calls) */
2250
2251 __attribute__((noreturn))
2252 static void
handle_bti_fail(arm_saved_state_t * state,uint64_t esr)2253 handle_bti_fail(arm_saved_state_t *state, uint64_t esr)
2254 {
2255 uint32_t btype = (uint32_t) esr & ISS_BTI_BTYPE_MASK;
2256
2257 if (!is_saved_state64(state)) {
2258 /* BTI is an ARMv8 feature, this should not be possible */
2259 panic("BTI failure for 32-bit state? (ESR=0x%llx)", esr);
2260 }
2261
2262 /*
2263 * We currently only expect BTI to be enabled for kernel pages, so panic if
2264 * we detect otherwise.
2265 */
2266 if (!PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
2267 panic("Unexpected non-kernel BTI failure? (ESR=0x%llx)", esr);
2268 }
2269
2270 #define BTI_FAIL_PTR_FMT "%04x"
2271 #define BTI_FAIL_MSG_FMT "Kernel BTI failure (BTYPE=0x" BTI_FAIL_PTR_FMT ")"
2272 /* Replace the pointer format with the length of the pointer message+NULL */
2273 char msg[strlen(BTI_FAIL_MSG_FMT) - strlen(BTI_FAIL_PTR_FMT) + 8 + 1];
2274 snprintf(msg, sizeof(msg), BTI_FAIL_MSG_FMT, btype);
2275 panic_with_thread_kernel_state(msg, state);
2276 __builtin_unreachable();
2277 }
2278
2279 static void
handle_user_trapped_instruction32(arm_saved_state_t * state,uint64_t esr)2280 handle_user_trapped_instruction32(arm_saved_state_t *state, uint64_t esr)
2281 {
2282 exception_type_t exception = EXC_BAD_INSTRUCTION;
2283 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
2284 mach_msg_type_number_t numcodes = 2;
2285 uint32_t instr;
2286
2287 if (is_saved_state64(state)) {
2288 panic("ESR (0x%llx) for instruction trapped from U32, but saved state is 64-bit.", esr);
2289 }
2290
2291 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
2292 panic("ESR (0x%llx) for instruction trapped from U32, actually came from kernel?", esr);
2293 }
2294
2295 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
2296 codes[1] = instr;
2297
2298 exception_triage(exception, codes, numcodes);
2299 __builtin_unreachable();
2300 }
2301
2302 static void
handle_simd_trap(arm_saved_state_t * state,uint64_t esr)2303 handle_simd_trap(arm_saved_state_t *state, uint64_t esr)
2304 {
2305 exception_type_t exception = EXC_BAD_INSTRUCTION;
2306 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
2307 mach_msg_type_number_t numcodes = 2;
2308 uint32_t instr = 0;
2309
2310 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
2311 panic("ESR (0x%llx) for SIMD trap from userland, actually came from kernel?", esr);
2312 }
2313
2314 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
2315 codes[1] = instr;
2316
2317 exception_triage(exception, codes, numcodes);
2318 __builtin_unreachable();
2319 }
2320
2321 void
sleh_irq(arm_saved_state_t * state)2322 sleh_irq(arm_saved_state_t *state)
2323 {
2324 cpu_data_t * cdp __unused = getCpuDatap();
2325 #if MACH_ASSERT
2326 int preemption_level = sleh_get_preemption_level();
2327 #endif
2328
2329
2330 sleh_interrupt_handler_prologue(state, DBG_INTR_TYPE_OTHER);
2331
2332 #if USE_APPLEARMSMP
2333 PE_handle_ext_interrupt();
2334 #else
2335 /* Run the registered interrupt handler. */
2336 cdp->interrupt_handler(cdp->interrupt_target,
2337 cdp->interrupt_refCon,
2338 cdp->interrupt_nub,
2339 cdp->interrupt_source);
2340 #endif
2341
2342 entropy_collect();
2343
2344
2345 sleh_interrupt_handler_epilogue();
2346 #if MACH_ASSERT
2347 if (preemption_level != sleh_get_preemption_level()) {
2348 panic("irq handler %p changed preemption level from %d to %d", cdp->interrupt_handler, preemption_level, sleh_get_preemption_level());
2349 }
2350 #endif
2351 }
2352
2353 void
sleh_fiq(arm_saved_state_t * state)2354 sleh_fiq(arm_saved_state_t *state)
2355 {
2356 unsigned int type = DBG_INTR_TYPE_UNKNOWN;
2357 #if MACH_ASSERT
2358 int preemption_level = sleh_get_preemption_level();
2359 #endif
2360
2361 #if MONOTONIC_FIQ
2362 uint64_t pmcr0 = 0, upmsr = 0;
2363 #endif /* MONOTONIC_FIQ */
2364
2365 #if defined(HAS_IPI)
2366 boolean_t is_ipi = FALSE;
2367 uint64_t ipi_sr = 0;
2368
2369 if (gFastIPI) {
2370 MRS(ipi_sr, "S3_5_C15_C1_1");
2371
2372 if (ipi_sr & ARM64_IPISR_IPI_PENDING) {
2373 is_ipi = TRUE;
2374 }
2375 }
2376
2377 if (is_ipi) {
2378 type = DBG_INTR_TYPE_IPI;
2379 } else
2380 #endif /* defined(HAS_IPI) */
2381 if (ml_get_timer_pending()) {
2382 type = DBG_INTR_TYPE_TIMER;
2383 }
2384 #if MONOTONIC_FIQ
2385 /* Consult the PMI sysregs last, after IPI/timer
2386 * classification.
2387 */
2388 else if (mt_pmi_pending(&pmcr0, &upmsr)) {
2389 type = DBG_INTR_TYPE_PMI;
2390 }
2391 #endif /* MONOTONIC_FIQ */
2392
2393 sleh_interrupt_handler_prologue(state, type);
2394
2395 #if APPLEVIRTUALPLATFORM
2396 uint64_t iar = __builtin_arm_rsr64("ICC_IAR0_EL1");
2397 #endif
2398
2399 #if defined(HAS_IPI)
2400 if (type == DBG_INTR_TYPE_IPI) {
2401 /*
2402 * Order is important here: we must ack the IPI by writing IPI_SR
2403 * before we call cpu_signal_handler(). Otherwise, there will be
2404 * a window between the completion of pending-signal processing in
2405 * cpu_signal_handler() and the ack during which a newly-issued
2406 * IPI to this CPU may be lost. ISB is required to ensure the msr
2407 * is retired before execution of cpu_signal_handler().
2408 */
2409 MSR("S3_5_C15_C1_1", ARM64_IPISR_IPI_PENDING);
2410 __builtin_arm_isb(ISB_SY);
2411 cpu_signal_handler();
2412 } else
2413 #endif /* defined(HAS_IPI) */
2414 #if MONOTONIC_FIQ
2415 if (type == DBG_INTR_TYPE_PMI) {
2416 INTERRUPT_MASKED_DEBUG_START(mt_fiq, DBG_INTR_TYPE_PMI);
2417 mt_fiq(getCpuDatap(), pmcr0, upmsr);
2418 INTERRUPT_MASKED_DEBUG_END();
2419 } else
2420 #endif /* MONOTONIC_FIQ */
2421 {
2422 /*
2423 * We don't know that this is a timer, but we don't have insight into
2424 * the other interrupts that go down this path.
2425 */
2426
2427 cpu_data_t *cdp = getCpuDatap();
2428
2429 cdp->cpu_decrementer = -1; /* Large */
2430
2431 /*
2432 * ARM64_TODO: whether we're coming from userland is ignored right now.
2433 * We can easily thread it through, but not bothering for the
2434 * moment (AArch32 doesn't either).
2435 */
2436 INTERRUPT_MASKED_DEBUG_START(rtclock_intr, DBG_INTR_TYPE_TIMER);
2437 rtclock_intr(TRUE);
2438 INTERRUPT_MASKED_DEBUG_END();
2439 }
2440
2441 #if APPLEVIRTUALPLATFORM
2442 if (iar != GIC_SPURIOUS_IRQ) {
2443 __builtin_arm_wsr64("ICC_EOIR0_EL1", iar);
2444 __builtin_arm_isb(ISB_SY);
2445 }
2446 #endif
2447
2448 sleh_interrupt_handler_epilogue();
2449 #if MACH_ASSERT
2450 if (preemption_level != sleh_get_preemption_level()) {
2451 panic("fiq type %u changed preemption level from %d to %d", type, preemption_level, sleh_get_preemption_level());
2452 }
2453 #endif
2454 }
2455
2456 void
sleh_serror(arm_context_t * context,uint64_t esr,vm_offset_t far)2457 sleh_serror(arm_context_t *context, uint64_t esr, vm_offset_t far)
2458 {
2459 task_vtimer_check(current_thread());
2460
2461 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_SERR_ARM, 0) | DBG_FUNC_START,
2462 esr, VM_KERNEL_ADDRHIDE(far));
2463 arm_saved_state_t *state = &context->ss;
2464 #if MACH_ASSERT
2465 int preemption_level = sleh_get_preemption_level();
2466 #endif
2467
2468 if (PSR64_IS_USER(get_saved_state_cpsr(state))) {
2469 /* Sanitize FAR (only if we came from userspace) */
2470 saved_state64(state)->far = 0;
2471 }
2472
2473 ASSERT_CONTEXT_SANITY(context);
2474 arm64_platform_error(state, esr, far, PLAT_ERR_SRC_ASYNC);
2475 #if MACH_ASSERT
2476 if (preemption_level != sleh_get_preemption_level()) {
2477 panic("serror changed preemption level from %d to %d", preemption_level, sleh_get_preemption_level());
2478 }
2479 #endif
2480 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_SERR_ARM, 0) | DBG_FUNC_END,
2481 esr, VM_KERNEL_ADDRHIDE(far));
2482 }
2483
2484 void
mach_syscall_trace_exit(unsigned int retval,unsigned int call_number)2485 mach_syscall_trace_exit(unsigned int retval,
2486 unsigned int call_number)
2487 {
2488 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
2489 MACHDBG_CODE(DBG_MACH_EXCP_SC, (call_number)) |
2490 DBG_FUNC_END, retval, 0, 0, 0, 0);
2491 }
2492
2493 __attribute__((noreturn))
2494 void
thread_syscall_return(kern_return_t error)2495 thread_syscall_return(kern_return_t error)
2496 {
2497 thread_t thread;
2498 struct arm_saved_state *state;
2499
2500 thread = current_thread();
2501 state = get_user_regs(thread);
2502
2503 assert(is_saved_state64(state));
2504 saved_state64(state)->x[0] = error;
2505
2506 #if MACH_ASSERT
2507 kern_allocation_name_t
2508 prior __assert_only = thread_get_kernel_state(thread)->allocation_name;
2509 assertf(prior == NULL, "thread_set_allocation_name(\"%s\") not cleared", kern_allocation_get_name(prior));
2510 #endif /* MACH_ASSERT */
2511
2512 if (kdebug_enable) {
2513 /* Invert syscall number (negative for a mach syscall) */
2514 mach_syscall_trace_exit(error, (-1) * get_saved_state_svc_number(state));
2515 }
2516
2517 thread_exception_return();
2518 }
2519
2520 void
syscall_trace(struct arm_saved_state * regs __unused)2521 syscall_trace(
2522 struct arm_saved_state * regs __unused)
2523 {
2524 /* kprintf("syscall: %d\n", saved_state64(regs)->x[16]); */
2525 }
2526
2527 static void
sleh_interrupt_handler_prologue(arm_saved_state_t * state,unsigned int type)2528 sleh_interrupt_handler_prologue(arm_saved_state_t *state, unsigned int type)
2529 {
2530 const bool is_user = PSR64_IS_USER(get_saved_state_cpsr(state));
2531
2532 if (is_user == true) {
2533 /* Sanitize FAR (only if the interrupt occurred while the CPU was in usermode) */
2534 saved_state64(state)->far = 0;
2535 }
2536
2537 recount_enter_interrupt();
2538
2539 task_vtimer_check(current_thread());
2540
2541 uint64_t pc = is_user ? get_saved_state_pc(state) :
2542 VM_KERNEL_UNSLIDE(get_saved_state_pc(state));
2543
2544 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
2545 0, pc, is_user, type);
2546
2547 #if CONFIG_TELEMETRY
2548 if (telemetry_needs_record) {
2549 telemetry_mark_curthread(is_user, FALSE);
2550 }
2551 #endif /* CONFIG_TELEMETRY */
2552 }
2553
2554 static void
sleh_interrupt_handler_epilogue(void)2555 sleh_interrupt_handler_epilogue(void)
2556 {
2557 #if KPERF
2558 kperf_interrupt();
2559 #endif /* KPERF */
2560 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END);
2561 recount_leave_interrupt();
2562 }
2563
2564 void
sleh_invalid_stack(arm_context_t * context,uint64_t esr __unused,vm_offset_t far __unused)2565 sleh_invalid_stack(arm_context_t *context, uint64_t esr __unused, vm_offset_t far __unused)
2566 {
2567 thread_t thread = current_thread();
2568 vm_offset_t kernel_stack_bottom, sp;
2569
2570 sp = get_saved_state_sp(&context->ss);
2571 vm_offset_t kstackptr = (vm_offset_t)thread->machine.kstackptr;
2572 kernel_stack_bottom = round_page(kstackptr) - KERNEL_STACK_SIZE;
2573
2574 if ((sp < kernel_stack_bottom) && (sp >= (kernel_stack_bottom - PAGE_SIZE))) {
2575 panic_with_thread_kernel_state("Invalid kernel stack pointer (probable overflow).", &context->ss);
2576 }
2577
2578 panic_with_thread_kernel_state("Invalid kernel stack pointer (probable corruption).", &context->ss);
2579 }
2580
2581
2582 #if MACH_ASSERT
2583 static int trap_handled;
2584 static void
handle_recoverable_kernel_trap(__unused void * tstate,uint16_t comment)2585 handle_recoverable_kernel_trap(
2586 __unused void *tstate,
2587 uint16_t comment)
2588 {
2589 assert(comment == TEST_RECOVERABLE_SOFT_TRAP);
2590
2591 printf("Recoverable trap handled.\n");
2592 trap_handled = 1;
2593 }
2594
2595 KERNEL_BRK_DESCRIPTOR_DEFINE(test_desc,
2596 .type = KERNEL_BRK_TYPE_TEST,
2597 .base = TEST_RECOVERABLE_SOFT_TRAP,
2598 .max = TEST_RECOVERABLE_SOFT_TRAP,
2599 .options = KERNEL_BRK_RECOVERABLE,
2600 .handle_breakpoint = handle_recoverable_kernel_trap);
2601
2602 static int
recoverable_kernel_trap_test(__unused int64_t in,int64_t * out)2603 recoverable_kernel_trap_test(__unused int64_t in, int64_t *out)
2604 {
2605 ml_recoverable_trap(TEST_RECOVERABLE_SOFT_TRAP);
2606
2607 *out = trap_handled;
2608 return 0;
2609 }
2610
2611 SYSCTL_TEST_REGISTER(recoverable_kernel_trap, recoverable_kernel_trap_test);
2612
2613 #endif
2614