xref: /xnu-11215.1.10/osfmk/corecrypto/cc_runtime_config.h (revision 8d741a5de7ff4191bf97d57b9f54c2f6d4a15585)
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35 
36 #ifndef CORECRYPTO_CC_RUNTIME_CONFIG_H_
37 #define CORECRYPTO_CC_RUNTIME_CONFIG_H_
38 
39 #include <corecrypto/cc_config.h>
40 #include <corecrypto/cc.h>
41 
42 #if defined(__x86_64__) || defined(__i386__)
43 
44 #define CC_HAS_DIT() (0)
45 
46 #if CC_KERNEL
47     #include <i386/cpuid.h>
48     #define CC_HAS_RDRAND() ((cpuid_features() & CPUID_FEATURE_RDRAND) != 0)
49     #define CC_HAS_AESNI() ((cpuid_features() & CPUID_FEATURE_AES) != 0)
50     #define CC_HAS_SupplementalSSE3() ((cpuid_features() & CPUID_FEATURE_SSSE3) != 0)
51     #define CC_HAS_AVX1() ((cpuid_features() & CPUID_FEATURE_AVX1_0) != 0)
52     #define CC_HAS_AVX2() ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_AVX2) != 0)
53     #define CC_HAS_AVX512_AND_IN_KERNEL()    ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_AVX512F) !=0)
54     #define CC_HAS_BMI2() ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_BMI2) != 0)
55     #define CC_HAS_ADX() ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_ADX) != 0)
56 
57 #elif CC_DARWIN && CC_INTERNAL_SDK
58     #include <System/i386/cpu_capabilities.h>
59     #define CC_HAS_RDRAND() (_get_cpu_capabilities() & kHasRDRAND)
60     #define CC_HAS_AESNI() (_get_cpu_capabilities() & kHasAES)
61     #define CC_HAS_SupplementalSSE3() (_get_cpu_capabilities() & kHasSupplementalSSE3)
62     #define CC_HAS_AVX1() (_get_cpu_capabilities() & kHasAVX1_0)
63     #define CC_HAS_AVX2() (_get_cpu_capabilities() & kHasAVX2_0)
64     #define CC_HAS_AVX512_AND_IN_KERNEL() 0
65     #define CC_HAS_BMI2() (_get_cpu_capabilities() & kHasBMI2)
66     #define CC_HAS_ADX() (_get_cpu_capabilities() & kHasADX)
67 
68 #elif CC_SGX
69     #include <cpuid.h>
70     #include <stdbool.h>
71     #include <stdint.h>
72 
73     #define CPUID_REG_RAX 0
74     #define CPUID_REG_RBX 1
75     #define CPUID_REG_RCX 2
76     #define CPUID_REG_RDX 3
77 
78     #define CPUID_FEATURE_AES 25
79     #define CPUID_FEATURE_SSE3 0
80     #define CPUID_FEATURE_AVX1 28
81     #define CPUID_FEATURE_LEAF7_AVX2 5
82     #define CPUID_FEATURE_LEAF7_BMI2 8
83     #define CPUID_FEATURE_RDRAND 30
84     #define CPUID_FEATURE_LEAF7_ADX 19
85 
86 CC_INLINE bool
_cpu_supports(uint64_t leaf,uint64_t subleaf,uint8_t cpuid_register,uint8_t bit)87 _cpu_supports(uint64_t leaf, uint64_t subleaf, uint8_t cpuid_register, uint8_t bit)
88 {
89 	uint64_t registers[4] = {0};
90 	registers[CPUID_REG_RAX] = leaf;
91 	registers[CPUID_REG_RCX] = subleaf;
92 	if (oe_emulate_cpuid(&registers[CPUID_REG_RAX], &registers[CPUID_REG_RBX], &registers[CPUID_REG_RCX], &registers[CPUID_REG_RDX])) {
93 		return false;
94 	}
95 	return (registers[cpuid_register] >> bit) & 1;
96 }
97 
98 
99     #define CC_HAS_AESNI() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_AES)
100     #define CC_HAS_SupplementalSSE3() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_SSE3)
101     #define CC_HAS_AVX1() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_AVX1)
102     #define CC_HAS_AVX2() _cpu_supports(7, 0, CPUID_REG_RBX, CPUID_FEATURE_LEAF7_AVX2)
103     #define CC_HAS_AVX512_AND_IN_KERNEL() 0
104     #define CC_HAS_BMI2() _cpu_supports(7, 0, CPUID_REG_RBX, CPUID_FEATURE_LEAF7_BMI2)
105     #define CC_HAS_RDRAND() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_RDRAND)
106     #define CC_HAS_ADX() _cpu_supports(7, 0, CPUID_REG_RBX, CPUID_FEATURE_LEAF7_ADX)
107 #else
108     #define CC_HAS_AESNI() __builtin_cpu_supports("aes")
109     #define CC_HAS_SupplementalSSE3() __builtin_cpu_supports("ssse3")
110     #define CC_HAS_AVX1() __builtin_cpu_supports("avx")
111     #define CC_HAS_AVX2() __builtin_cpu_supports("avx2")
112     #define CC_HAS_AVX512_AND_IN_KERNEL() 0
113     #define CC_HAS_BMI2() __builtin_cpu_supports("bmi2")
114 #if CC_LINUX || !CC_INTERNAL_SDK
115     #include <cpuid.h>
116 
117 CC_INLINE bool
_cpu_supports_rdrand(void)118 _cpu_supports_rdrand(void)
119 {
120 	unsigned int eax, ebx, ecx, edx;
121 	__cpuid(1, eax, ebx, ecx, edx);
122 	return ecx & bit_RDRND;
123 }
124 
125 CC_INLINE bool
_cpu_supports_adx(void)126 _cpu_supports_adx(void)
127 {
128 	unsigned int eax, ebx, ecx, edx;
129 	__cpuid_count(7, 0, eax, ebx, ecx, edx);
130 	return ebx & bit_ADX;
131 }
132 
133     #define CC_HAS_RDRAND() _cpu_supports_rdrand()
134     #define CC_HAS_ADX() _cpu_supports_adx()
135 #else
136     #define CC_HAS_RDRAND() 0
137     #define CC_HAS_ADX() 0
138 #endif
139 
140 #endif
141 
142 #endif  // defined(__x86_64__) || defined(__i386__)
143 
144 #if defined(__arm64__)
145 
146 #if CC_TXM
147 
148     #define CC_HAS_SHA512() (CC_ARM_FEATURE_SHA512)
149     #define CC_HAS_SHA3() (0)
150 
151 extern bool cc_dit_supported(void);
152     #define CC_HAS_DIT() (cc_dit_supported())
153 
154 #elif CC_DARWIN && CC_INTERNAL_SDK
155     #include <System/arm/cpu_capabilities.h>
156 
157 #if __has_feature(address_sanitizer)
158  #define CC_COMMPAGE_CPU_CAPABILITIES \
159 	(*((volatile __attribute__((address_space(1))) uint64_t *)_COMM_PAGE_CPU_CAPABILITIES64))
160 #else
161  #define CC_COMMPAGE_CPU_CAPABILITIES \
162 	(*((volatile uint64_t *)_COMM_PAGE_CPU_CAPABILITIES64))
163 #endif
164 
165 CC_INLINE bool
_cpu_supports(uint64_t flag)166 _cpu_supports(uint64_t flag)
167 {
168 	return CC_COMMPAGE_CPU_CAPABILITIES & flag;
169 }
170 
171     #define CC_HAS_SHA512() _cpu_supports(kHasARMv82SHA512)
172     #define CC_HAS_SHA3() _cpu_supports(kHasARMv82SHA3)
173     #define CC_HAS_DIT() _cpu_supports(kHasFeatDIT)
174 #else
175     #define CC_HAS_SHA512() (CC_ARM_FEATURE_SHA512)
176     #define CC_HAS_SHA3() (0)
177     #define CC_HAS_DIT() (0)
178 #endif
179 
180 #endif // defined(__arm64__)
181 
182 #endif /* CORECRYPTO_CC_RUNTIME_CONFIG_H_ */
183