1 /*
2 * Copyright (c) 2019 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 #include <stdlib.h>
30 #include <darwintest.h>
31 #include <mach/mach.h>
32 #include <mach/thread_status.h>
33
34 T_GLOBAL_META(
35 T_META_NAMESPACE("xnu.arm"),
36 T_META_RADAR_COMPONENT_NAME("xnu"),
37 T_META_RADAR_COMPONENT_VERSION("arm"),
38 T_META_OWNER("justin_unger"),
39 T_META_RUN_CONCURRENTLY(true)
40 );
41
42 #define PSR64_USER_MASK (0xFU << 28)
43 #define PSR64_OPT_BITS (0x01 << 12) // user-writeable bits that may or may not be set, depending on hardware/device/OS/moon phase
44
45 #if __arm64__
46 __attribute__((noreturn))
47 static void
phase2()48 phase2()
49 {
50 kern_return_t err;
51 arm_thread_state64_t ts;
52 mach_msg_type_number_t count = ARM_THREAD_STATE64_COUNT;
53 uint32_t nzcv = (uint32_t) __builtin_arm_rsr64("NZCV");
54
55 T_QUIET; T_ASSERT_EQ(nzcv & PSR64_USER_MASK, PSR64_USER_MASK, "All condition flags are set");
56
57 err = thread_get_state(mach_thread_self(), ARM_THREAD_STATE64, (thread_state_t)&ts, &count);
58 T_QUIET; T_ASSERT_EQ(err, KERN_SUCCESS, "Got own thread state after corrupting CPSR");
59
60 T_QUIET; T_ASSERT_EQ(ts.__cpsr & ~(PSR64_USER_MASK | PSR64_OPT_BITS), 0, "No privileged fields in CPSR are set");
61
62 exit(0);
63 }
64 #endif
65
66 T_DECL(thread_set_state_arm64_cpsr,
67 "Test that user mode cannot control privileged fields in CPSR/PSTATE.")
68 {
69 #if !__arm64__
70 T_SKIP("Running on non-arm64 target, skipping...");
71 #else
72 kern_return_t err;
73 mach_msg_type_number_t count;
74 arm_thread_state64_t ts;
75
76 count = ARM_THREAD_STATE64_COUNT;
77 err = thread_get_state(mach_thread_self(), ARM_THREAD_STATE64, (thread_state_t)&ts, &count);
78 T_QUIET; T_ASSERT_EQ(err, KERN_SUCCESS, "Got own thread state");
79
80 /*
81 * jump to the second phase while attempting to set all the bits
82 * in CPSR. If we survive the jump and read back CPSR without any
83 * bits besides condition flags set, the test passes. If kernel
84 * does not mask out the privileged CPSR bits correctly, we can
85 * expect an illegal instruction set panic due to SPSR.IL being
86 * set upon ERET to user mode.
87 */
88
89 void *new_pc = (void *)&phase2;
90 arm_thread_state64_set_pc_fptr(ts, new_pc);
91 ts.__cpsr = ~0U;
92
93 err = thread_set_state(mach_thread_self(), ARM_THREAD_STATE64, (thread_state_t)&ts, ARM_THREAD_STATE64_COUNT);
94
95 /* NOT REACHED */
96
97 T_ASSERT_FAIL("Thread did not reach expected state. err = %d", err);
98
99 #endif
100 }
101