1*699cd480SApple OSS Distributions# CPU Counters 2*699cd480SApple OSS Distributions 3*699cd480SApple OSS DistributionsCPU performance counters are hardware registers that count events of interest to efficient CPU execution. 4*699cd480SApple OSS DistributionsCounters that measure events closely correlated with each CPU's execution pipeline are managed by the Core Performance Monitoring Unit (CPMU). 5*699cd480SApple OSS DistributionsThe CPMU contains both fixed instructions and cycles counters, as well as configurable counters that can be programmed to count any of several hundred possible events. 6*699cd480SApple OSS DistributionsIn addition to the CPMU, the Last Level Cache (LLC) hosts the Uncore Performance Monitoring Unit (UPMU), which measures effects that aren't necessarily correlated to a single CPU. 7*699cd480SApple OSS DistributionsAll counters in the UPMU are configurable. 8*699cd480SApple OSS Distributions 9*699cd480SApple OSS DistributionsCounters are typically used in one of two ways. 10*699cd480SApple OSS DistributionsIn "counting" mode, their counts are periodically queried and tallied up for a duration of interest. 11*699cd480SApple OSS DistributionsIn "sampling" mode, the counters are programmed to generate a Performance Monitor Interrupt (PMI) periodically, during which the currently running code can be sampled, like a time profiler. 12*699cd480SApple OSS Distributions 13*699cd480SApple OSS Distributions## Subsystems 14*699cd480SApple OSS Distributions 15*699cd480SApple OSS DistributionsThere are several subsystems that provide access to CPU counter hardware: 16*699cd480SApple OSS Distributions 17*699cd480SApple OSS Distributions- kpc: The Kernel Performance Counter system is the oldest subsystem and still manages the configurable CPMU counters. 18*699cd480SApple OSS DistributionsIt can use PMIs from these counters to trigger kperf samples and counter values can be recorded in kperf samples. 19*699cd480SApple OSS Distributions 20*699cd480SApple OSS Distributions- Monotonic: The Monotonic system provides access to the fixed CPMU counters with limited support for PMIs. 21*699cd480SApple OSS DistributionsAdditionally, the UPMU is entirely provided by a Monotonic dev node interface. 22*699cd480SApple OSS Distributions 23*699cd480SApple OSS Distributions- cpc: The CPU Performance Counter subsystem provides a policy layer on top of kpc and Monotonic to prevent malicious use of the hardware. 24*699cd480SApple OSS Distributions 25*699cd480SApple OSS DistributionsEventually, cpc will subsume kpc's and Monotonic's roles in the system. 26*699cd480SApple OSS Distributions 27*699cd480SApple OSS Distributions## Integrations 28*699cd480SApple OSS Distributions 29*699cd480SApple OSS Distributions- The Recount subsystem makes extensive use of the fixed CPMU counters to attribute CPU resources back to threads and processes. 30*699cd480SApple OSS Distributions 31*699cd480SApple OSS Distributions- Microstackshot telemetry is sampled periodically using the CPMU's cycle PMI trigger. 32*699cd480SApple OSS Distributions 33*699cd480SApple OSS Distributions- Stackshot includes cycles and instructions for each thread container in its kcdata. 34*699cd480SApple OSS Distributions 35*699cd480SApple OSS Distributions- The kperf profiling system can trigger samples of thread states and call stacks using CPMU PMIs, allowing it to sample thread states and call stacks. 36*699cd480SApple OSS DistributionsAnd CPU counter values can be sampled by kperf on other triggers, like timers or kdebug events. 37*699cd480SApple OSS Distributions 38*699cd480SApple OSS Distributions## See Also 39*699cd480SApple OSS Distributions 40*699cd480SApple OSS Distributions- `doc/recount.md` 41