1 /* Copyright (c) (2012,2014,2015,2016,2017,2018,2019,2020) Apple Inc. All rights reserved. 2 * 3 * corecrypto is licensed under Apple Inc.’s Internal Use License Agreement (which 4 * is contained in the License.txt file distributed with corecrypto) and only to 5 * people who accept that license. IMPORTANT: Any license rights granted to you by 6 * Apple Inc. (if any) are limited to internal use within your organization only on 7 * devices and computers you own or control, for the sole purpose of verifying the 8 * security characteristics and correct functioning of the Apple Software. You may 9 * not, directly or indirectly, redistribute the Apple Software or any portions thereof. 10 */ 11 12 #ifndef CORECRYPTO_CC_RUNTIME_CONFIG_H_ 13 #define CORECRYPTO_CC_RUNTIME_CONFIG_H_ 14 15 #include <corecrypto/cc_config.h> 16 17 #if defined(__x86_64__) || defined(__i386__) 18 19 #if CC_KERNEL 20 #include <i386/cpuid.h> 21 #define CC_HAS_RDRAND() ((cpuid_features() & CPUID_FEATURE_RDRAND) != 0) 22 #define CC_HAS_AESNI() ((cpuid_features() & CPUID_FEATURE_AES) != 0) 23 #define CC_HAS_SupplementalSSE3() ((cpuid_features() & CPUID_FEATURE_SSSE3) != 0) 24 #define CC_HAS_AVX1() ((cpuid_features() & CPUID_FEATURE_AVX1_0) != 0) 25 #define CC_HAS_AVX2() ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_AVX2) != 0) 26 #define CC_HAS_AVX512_AND_IN_KERNEL() ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_AVX512F) !=0) 27 #define CC_HAS_BMI2() ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_BMI2) != 0) 28 #define CC_HAS_ADX() ((cpuid_info()->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_ADX) != 0) 29 30 #elif CC_DARWIN && CC_INTERNAL_SDK 31 #include <System/i386/cpu_capabilities.h> 32 #define CC_HAS_RDRAND() (_get_cpu_capabilities() & kHasRDRAND) 33 #define CC_HAS_AESNI() (_get_cpu_capabilities() & kHasAES) 34 #define CC_HAS_SupplementalSSE3() (_get_cpu_capabilities() & kHasSupplementalSSE3) 35 #define CC_HAS_AVX1() (_get_cpu_capabilities() & kHasAVX1_0) 36 #define CC_HAS_AVX2() (_get_cpu_capabilities() & kHasAVX2_0) 37 #define CC_HAS_AVX512_AND_IN_KERNEL() 0 38 #define CC_HAS_BMI2() (_get_cpu_capabilities() & kHasBMI2) 39 #define CC_HAS_ADX() (_get_cpu_capabilities() & kHasADX) 40 41 #elif CC_SGX 42 #include <cpuid.h> 43 #include <stdbool.h> 44 #include <stdint.h> 45 46 #define CPUID_REG_RAX 0 47 #define CPUID_REG_RBX 1 48 #define CPUID_REG_RCX 2 49 #define CPUID_REG_RDX 3 50 51 #define CPUID_FEATURE_AES 25 52 #define CPUID_FEATURE_SSE3 0 53 #define CPUID_FEATURE_AVX1 28 54 #define CPUID_FEATURE_LEAF7_AVX2 5 55 #define CPUID_FEATURE_LEAF7_BMI2 8 56 #define CPUID_FEATURE_RDRAND 30 57 #define CPUID_FEATURE_LEAF7_ADX 19 58 _cpu_supports(uint64_t leaf,uint64_t subleaf,uint8_t cpuid_register,uint8_t bit)59 CC_INLINE bool _cpu_supports(uint64_t leaf, uint64_t subleaf, uint8_t cpuid_register, uint8_t bit) { 60 uint64_t registers[4] = {0}; 61 registers[CPUID_REG_RAX] = leaf; 62 registers[CPUID_REG_RCX] = subleaf; 63 if (oe_emulate_cpuid(®isters[CPUID_REG_RAX], ®isters[CPUID_REG_RBX], ®isters[CPUID_REG_RCX], ®isters[CPUID_REG_RDX])) { 64 return false; 65 } 66 return (registers[cpuid_register] >> bit) & 1; 67 } 68 69 70 #define CC_HAS_AESNI() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_AES) 71 #define CC_HAS_SupplementalSSE3() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_SSE3) 72 #define CC_HAS_AVX1() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_AVX1) 73 #define CC_HAS_AVX2() _cpu_supports(7, 0, CPUID_REG_RBX, CPUID_FEATURE_LEAF7_AVX2) 74 #define CC_HAS_AVX512_AND_IN_KERNEL() 0 75 #define CC_HAS_BMI2() _cpu_supports(7, 0, CPUID_REG_RBX, CPUID_FEATURE_LEAF7_BMI2) 76 #define CC_HAS_RDRAND() _cpu_supports(1, 0, CPUID_REG_RCX, CPUID_FEATURE_RDRAND) 77 #define CC_HAS_ADX() _cpu_supports(7, 0, CPUID_REG_RBX, CPUID_FEATURE_LEAF7_ADX) 78 #else 79 #define CC_HAS_AESNI() __builtin_cpu_supports("aes") 80 #define CC_HAS_SupplementalSSE3() __builtin_cpu_supports("ssse3") 81 #define CC_HAS_AVX1() __builtin_cpu_supports("avx") 82 #define CC_HAS_AVX2() __builtin_cpu_supports("avx2") 83 #define CC_HAS_AVX512_AND_IN_KERNEL() 0 84 #define CC_HAS_BMI2() __builtin_cpu_supports("bmi2") 85 #if CC_LINUX || !CC_INTERNAL_SDK 86 #include <cpuid.h> 87 #include <stdbool.h> 88 _cpu_supports_rdrand()89 CC_INLINE bool _cpu_supports_rdrand() 90 { 91 unsigned int eax, ebx, ecx, edx; 92 __cpuid(1, eax, ebx, ecx, edx); 93 return ecx & bit_RDRND; 94 } 95 _cpu_supports_adx()96 CC_INLINE bool _cpu_supports_adx() 97 { 98 unsigned int eax, ebx, ecx, edx; 99 __cpuid_count(7, 0, eax, ebx, ecx, edx); 100 return ebx & bit_ADX; 101 } 102 103 #define CC_HAS_RDRAND() _cpu_supports_rdrand() 104 #define CC_HAS_ADX() _cpu_supports_adx() 105 #else 106 #define CC_HAS_RDRAND() 0 107 #define CC_HAS_ADX() 0 108 #endif 109 110 #endif 111 112 #endif // defined(__x86_64__) || defined(__i386__) 113 114 #if defined(__arm64__) 115 116 #if CC_DARWIN && CC_INTERNAL_SDK 117 #include <System/arm/cpu_capabilities.h> 118 #define CC_HAS_SHA512() (_get_cpu_capabilities() & kHasARMv82SHA512) 119 #define CC_HAS_SHA3() (_get_cpu_capabilities() & kHasARMv82SHA3) 120 #else 121 #define CC_HAS_SHA512() (0) 122 #define CC_HAS_SHA3() (0) 123 #endif 124 125 #endif // defined(__arm64__) 126 127 #endif /* CORECRYPTO_CC_RUNTIME_CONFIG_H_ */ 128