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/xnu-8020.140.41/osfmk/arm64/
H A Dbcopy.s96 cmp x3, x2
99 cmp x2, #(kSmallCopy)
139 sub x2, x2, x5 // update length
142 subs x2, x2, #64
162 subs x2, x2, #32
173 add x1, x1, x2
178 add x3, x3, x2
199 subs x2, x2, #8
201 adds x2, x2, #8
205 subs x2, x2, #1
[all …]
H A Dbzero.s55 mov x2, x1
58 cmp x2, #128
75 add x2, x2, x0 // end of buffer
77 subs x2, x2, x4 // if the end of the buffer comes first, jump
81 subs x2, x2, #64 // decrement length
83 1: add x3, x3, x2 // back up pointer to (end of buffer) - 64.
108 cmp x2, #64
122 add x2, x2, x0 // end of buffer
124 subs x2, x2, x4 // if the end of the buffer comes first, jump
131 subs x2, x2, #64
[all …]
H A Dcaches_asm.s66 and x2, x0, x9
68 add x1, x1, x2
148 CACHE_AT_LEVEL x2, x1, x3
149 cbz x2, 5f // No cache at this level, all higher levels may be skipped
150 cmp x2, #2
152 mov x2, x1
153 GET_CACHE_CONFIG x2, x9, x10, x11
154 lsl x2, x1, #1 // level field for cisw/csw, bits 1:3
157 dc $0, x2 // clean dcache line by way/set
158 add x2, x2, x9 // increment set index
[all …]
H A Dmachine_routines_asm.s97 mov x2, x0
112 mov x2, x1
174 mrs x2, FPCR // Grab FPCR
178 and x2, x2, x0 // Be paranoid, and clear bits we expect to
180 orr x0, x1, x2 // OR them to get FPSCR equivalent state
200 orr x2, x4, x5
201 and x2, x2, x0 // Clear the bits that don't apply to FPCR
203 msr FPCR, x2 // Write FPSR
227 mrs x2, MDSCR_EL1
228 bic x2, x2, x0
[all …]
H A Dstrncmp.s75 cbz x2, L_scalarDone
84 subs x2, x2, #1 // decrement length
119 0: cmp x2, x7
121 sub x6, x2, x7
134 mov x2, x6
143 subs x2, x2, #1 // decrement length
166 subs x2, x2, #16
184 cmp x3, x2
H A Dmemcmp_zero.s85 mov x2, x0 // copy the original addr
88 ldp q4, q5, [x2]
89 ldp q6, q7, [x2, #32]
90 sub x2, x0, x2 // bytes between original and aligned addr
91 sub x1, x1, x2 // update length
132 0: ldr x2, [x0],#8
133 orr x3, x3, x2 // use orr to keep non-zero bytes
H A Dstrnlen.s80 and x2, x0, #-16
81 ldr q0, [x2]
107 0: ldr q0, [x2, #16]!
116 sub x0, x2, x0
134 sub x0, x2, x0 // index of vector in string
162 and x2, x0, #0xf
163 sub x3, x3, x2
200 add x0, x0, x2
H A Dcswitch.s230 set_thread_registers x0, x1, x2
233 set_process_dependent_keys_and_sync_context x0, x1, x2, x3, w4
261 mov x22, x2 //wait result
294 set_thread_registers x2, x3, x4
295 ldr x3, [x2, TH_KSTACKPTR]
297 set_process_dependent_keys_and_sync_context x2, x3, x4, x5, w6
331 ldr x2, [x1, CPU_ISTACKPTR] // Switch to interrupt stack
332 mov sp, x2
347 set_process_dependent_keys_and_sync_context x0, x1, x2, x3, w4
353 set_thread_registers x0, x1, x2
H A Dpinst.s87 check_instruction x2, x3, __pinst_set_ttbr1, 0xd65f03c0d5182020
92 check_instruction x2, x3, __pinst_set_vbar, 0xd65f03c0d518c000
97 check_instruction x2, x3, __pinst_set_tcr, 0xd65f03c0d5182040
102 check_instruction x2, x3, __pinst_set_sctlr, 0xd65f03c0d5181000
123 check_instruction x2, x3, __pinst_spsel_1, 0xd65f03c0d50041bf
H A Dstart.s157 cmp x0, x2 // Compare cpu data phys cpu and MPIDR_EL1 phys cpu
171 adrp x2, EXT(resume_idle_cpu)@page
172 add x2, x2, EXT(resume_idle_cpu)@pageoff
173 cmp x0, x2
175 adrp x2, EXT(start_cpu)@page
176 add x2, x2, EXT(start_cpu)@pageoff
177 cmp x0, x2
527 mov x2, #(TTE_PGENTRIES) // Load number of entries per page
528 lsl x2, x2, #2 // Shift by 2 for num entries on 4 pages
532 subs x2, x2, #1 // entries--
[all …]
H A Dlocore.s146 stp x2, x3, [sp, #-16]! // Save {x2-x3}
148 mov x2, #(ESR_EC_SP_ALIGN << ESR_EC_SHIFT)
149 cmp x1, x2 // If we have a stack alignment exception
151 mov x2, #(ESR_EC_DABORT_EL1 << ESR_EC_SHIFT)
152 cmp x1, x2 // If we have a data abort, we need to
157 ldr x2, [x1, TH_KSTACKPTR] // Get top of kernel stack
158 sub x3, x2, KERNEL_STACK_SIZE // Find bottom of kernel stack
159 cmp x0, x2 // if (SP_EL0 >= kstack top)
165 ldr x2, [x1, CPU_INTSTACK_TOP] // Get top of istack
166 sub x3, x2, INTSTACK_SIZE_NUM // Find bottom of istack
[all …]
H A Dsmccc_asm.h44 stp x2, x3, [sp, #- 16]!
54 ldp x2, x3, [sp], #16
H A Dmachine_routines_asm.h85 mov \tmp2, x2
91 mov x2, \tmp2
H A Dlz4_encode_arm64.s47 #define src_ptr x2
86 ldr x11, [x2] // src
386 str x11, [x2]
H A DWKdmCompress_4k.s181 #define scratch x2
184 #define tempTagsArray x2 // scratch
H A DWKdmCompress_16k.s183 #define scratch x2
186 #define tempTagsArray x2 // scratch
H A Dexception_asm.h144 stp x2, x3, [x0, SS64_X2] // Save remaining GPRs
/xnu-8020.140.41/osfmk/arm/commpage/
H A Dcommpage_asm.s151 stp x2, x9, [sp, #-16]!
158 ldp x2, x9, [sp], #16
291 str x1, [x10, x2] // Set old tail -> offset = new elem
326 casa w10, w11, [x2] // Atomic CAS with acquire barrier
349 stlr wzr, [x2] // Drop spin lock with release barrier (pairs with acquire in casa)
374 str xzr, [x1, x2] // Zero the forward link in the new element
431 add x2, x0, #16 // address of lock = x2 = x0 + 16
442 ldxr w9, [x2] // arm the monitor for the lock address
454 BACKOFF x2
/xnu-8020.140.41/libsyscall/wrappers/
H A Dvarargs_wrappers.s42 ldp x2, x3, [fp, #16]
65 ldr x2, [fp, #16]
81 ldp x1, x2, [fp, #16]
98 ldp x1, x2, [fp, #16]
132 ldp x1, x2, [fp, #16]
H A Dmach_absolute_time.s231 ldr x2, [x3] // Load the offset
232 cmp x1, x2 // Compare our offset values...
258 cmp x2, #USER_TIMEBASE_NONE // Are userspace reads supported?
260 cmp x2, #USER_TIMEBASE_NOSPEC
/xnu-8020.140.41/osfmk/kern/
H A Darithmetic_128.h71 uint32_t x2 = (uint32_t)x; in mul64x64() local
83 prod->low = (uint64_t)x2 * (uint64_t)y2; in mul64x64()
88 add.low = (uint64_t)x2 * (uint64_t)y1; in mul64x64()
/xnu-8020.140.41/san/memory/
H A Dkasan-test-arm64.s46 ldp fp, x2, [x0, JMP_fp_sp]
51 add sp, x2, #0
/xnu-8020.140.41/libsyscall/custom/
H A D__syscall.s65 ldp x1, x2, [sp]
H A D__gettimeofday.s114 movz x2, #0x0
/xnu-8020.140.41/bsd/dev/arm64/
H A Dcpu_in_cksum.s99 #define off x2
426 and x2, x4, x3, lsr #16

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