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Searched refs:r4 (Results 1 – 19 of 19) sorted by relevance

/xnu-8020.140.41/osfmk/arm/
H A Dbcopy.s54 stmfd sp!, { r0, r4, r5, r7, lr }
90 ldmia r1!, { r3, r4, r5, r6, r8, r10, r11, r12 }
92 stmia r0!, { r3, r4, r5, r6, r8, r10, r11, r12 }
93 ldmia r1!, { r3, r4, r5, r6, r8, r10, r11, r12 }
96 stmia r0!, { r3, r4, r5, r6, r8, r10, r11, r12 }
109 ldmiage r1!, { r3, r4, r5, r12 }
110 stmiage r0!, { r3, r4, r5, r12 }
120 ldreq r4, [r1], #4
125 streq r4, [r0], #4
137 ldrhcs r4, [r1], #2
[all …]
H A Dlocore.s93 adr r4, EXT(ResetHandlerData)
94 ldr r0, [r4, ASSIST_RESET_HANDLER]
97 adr r4, EXT(ResetHandlerData)
98 ldr r1, [r4, CPU_DATA_ENTRIES]
103 adr r4, EXT(ResetHandlerData)
104 ldr r0, [r4, BOOT_ARGS]
105 ldr r1, [r4, CPU_DATA_ENTRIES]
343 mrs r4, spsr
344 str r4, [sp, SS_CPSR] // Save user mode cpsr
406 mrs r4, lr_und
[all …]
H A Dstart.s70 ldr r4, [r0, BA_TOP_OF_KERNEL_DATA] // Get the top of kernel data
71 orr r5, r4, #(TTBR_SETUP & 0x00FF) // Setup PTWs memory attribute
114 LOAD_ADDR(r4, fleh_reset)
116 str r4, [r5]
117 LOAD_ADDR(r4, fleh_undef)
119 str r4, [r5]
120 LOAD_ADDR(r4, fleh_swi)
122 str r4, [r5]
123 LOAD_ADDR(r4, fleh_prefabt)
125 str r4, [r5]
[all …]
H A Dcswitch.s96 ldmia r3!, {r4-r14} // Load thread status
116 mov r4,r0 // Load continuation
128 blx r4 // Branch to continuation
156 stmia r3!, {r4-r14} // Save general registers to pcb
171 ldmia r3!, {r4-r14} // Restore new thread status
196 stmia r3!, {r4-r14} // Save general registers to pcb
221 stmia r3!, {r4-r14} // Save general registers to pcb
240 ldmia r3!, {r4-r14} // Restore new thread status
H A Dstrncmp.s40 push {r4-r7,lr} ;\
45 pop {r4-r7,lr}
126 orr r4, r5, r8, lsl r6
127 cmpeq ip, r4
H A Dlz4_encode_armv7.s47 #define src_end r4
57 push {r4-r7, lr}
60 ldrd r4, r5, [sp, #36]
67 …sub r4, r4, margin // subtract safety margin from src_size (src_size < margin is detect…
68 add src_end, src_ptr, r4 // src end - margin.
77 pop {r4-r7, pc}
H A DWKdmCompress_new.s178 #define remaining r4
191 …#define R13 r4 // only safe to use between phase-1 and phase-2
225 push {r4-r6,r8-r11}
426 ldr r4,[ecx, #2] // w2:6bits:w1
428 uxth r5, r4, ror #16 // w2
429 uxth r4, r4 // w1
430 orr r0, r0, r4, lsl #10 // w1:w0
460 pop {r4-r6,r8-r11}
H A Dbzero.s93 stmfd sp!, { r4-r6, r8, r10-r11 }
94 mov r4, r2
111 ldmfd sp!, { r4-r6, r8, r10-r11 }
H A Dmachine_routines_asm.s636 stmfd sp!, { r4, r5, r6 } ;\
639 ldr r4, [r12, TH_RECOVER] ;\
719 str r4, [r12, TH_RECOVER] ;\
720 ldmfd sp!, { r4, r5, r6 }
739 stmfd sp!, { r4, r5, r6 }
744 ldr r4, [r12, TH_RECOVER] ;\
772 str r4, [r12, TH_RECOVER]
773 ldmfd sp!, { r4, r5, r6 }
914 str r4, [r12, TH_RECOVER]
915 ldmfd sp!, { r4, r5, r6 }
[all …]
H A DWKdmDecompress_new.s98 #define ebx r4
99 #define hashTable r4
122 push {r4-r6,r8-r11}
341 pop {r4-r6,r8-r11}
H A Dlz4_decode_armv7NEON.s55 #define src_end r4 // arg4
74 push {r4-r7, lr} // Save registers
85 pop {r4-r7,pc}
/xnu-8020.140.41/osfmk/mach/arm/
H A Dsyscall_sw.h48 stmfd sp!, { r4-r5 } /* save r4-r5, keep stack 64-bit aligned */; \
49 ldr r4, [ ip ] /* load arg 5 */ ; \
52 ldmfd sp!, { r4-r5 } /* restore r4-r5 */ ;\
76 #define _kernel_trap_4(trap_name, trap_number) _kernel_trap_6to9(trap_name, trap_number, r4-r5, r4-…
78 #define _kernel_trap_5(trap_name, trap_number) _kernel_trap_6to9(trap_name, trap_number, r4-r5, r4-…
79 …6(trap_name, trap_number) _kernel_trap_6to9(trap_name, trap_number, r4-r6 COMMA r8, r4-r6 COMMA r8)
80 …7(trap_name, trap_number) _kernel_trap_6to9(trap_name, trap_number, r4-r6 COMMA r8, r4-r6 COMMA r8)
81 …8(trap_name, trap_number) _kernel_trap_6to9(trap_name, trap_number, r4-r6 COMMA r8, r4-r6 COMMA r8)
82 …9(trap_name, trap_number) _kernel_trap_6to9(trap_name, trap_number, r4-r6 COMMA r8, r4-r6 COMMA r8)
91 #define _kernel_trap_6(trap_name, trap_number) _kernel_trap_6to9(trap_name, trap_number, r4-r5, r4-…
[all …]
/xnu-8020.140.41/bsd/dev/arm/
H A Dcpu_in_cksum.s147 stmfd sp!, {r4-r11,lr}
157 ldmfd sp!, {r4-r11, pc}
223 ldrb r4, [r0], #0x01 /* Fetch 1st byte */
230 orreq r2, r5, r4, lsl #8
232 orrne r2, r4, r5, lsl #8
235 orreq r2, r4, r5, lsl #8
237 orrne r2, r5, r4, lsl #8
318 ldmia r0!, {r3, r4, r5, r6}
320 adcs r2, r2, r4
322 ldmia r0!, {r3, r4, r5, r7}
[all …]
H A Dcpu_copy_in_cksum.s83 #define need_swap r4
87 push {r4,r5,r7,lr}
324 pop {r4,r5,r7,pc}
/xnu-8020.140.41/libsyscall/custom/
H A DSYS.h261 stmfd sp!, { r4-r5 } /* save r4-r5 */ ;\
262 ldr r4, [ip] /* load 5th arg */ ; \
264 ldmfd sp!, { r4-r5 } /* restore r4-r5 */ ; \
293 #define SYSCALL_4(name) SYSCALL_6to12(name, r4-r5, r4-r5)
295 #define SYSCALL_5(name) SYSCALL_6to12(name, r4-r5, r4-r5)
296 #define SYSCALL_6(name) SYSCALL_6to12(name, r4-r6 COMMA r8, r4-r6 COMMA r8)
297 #define SYSCALL_7(name) SYSCALL_6to12(name, r4-r6 COMMA r8, r4-r6 COMMA r8)
298 #define SYSCALL_8(name) SYSCALL_6to12(name, r4-r6 COMMA r8, r4-r6 COMMA r8)
299 #define SYSCALL_12(name) SYSCALL_6to12(name, r4-r6 COMMA r8, r4-r6 COMMA r8)
309 #define SYSCALL_6(name) SYSCALL_6to12(name, r4-r5, r4-r5)
[all …]
H A D__fork.s107 stmfd sp!, {r4, r7, lr}
122 ldmfd sp!, {r4, r7, pc}
129 ldmfd sp!, {r4, r7, pc} // pop and return
/xnu-8020.140.41/libsyscall/wrappers/
H A Dmach_absolute_time.s186 push {r4, r5, r7, lr} // Push a frame
189 ldr r4, [ip] // Load offset low bits
198 eor r4, r2 // Compare our offset values...
200 orrs r5, r4
204 pop {r4, r5, r7, pc} // Pop the frame
/xnu-8020.140.41/EXTERNAL_HEADERS/corecrypto/
H A Dccchacha20poly1305.h33 uint32_t r0, r1, r2, r3, r4; member
/xnu-8020.140.41/tools/lldbmacros/core/
H A Doperating_system.py258 self.r4 = 0
299 self.r4, self.r5, self.r6, self.r7,
313 self.r4 = saved_state.GetChildMemberWithName('r').GetChildAtIndex(4).GetValueAsUnsigned()
339 self.r4 = saved_state.GetChildMemberWithName('r').GetChildAtIndex(4).GetValueAsUnsigned()