Searched refs:rdmsr64 (Results 1 – 18 of 18) sorted by relevance
134 range[i].base = rdmsr64(MSR_IA32_MTRR_PHYSBASE(i)); in mtrr_get_var_ranges()135 range[i].mask = rdmsr64(MSR_IA32_MTRR_PHYSMASK(i)); in mtrr_get_var_ranges()169 range[0].types = rdmsr64(MSR_IA32_MTRR_FIX64K_00000); in mtrr_get_fix_ranges()170 range[1].types = rdmsr64(MSR_IA32_MTRR_FIX16K_80000); in mtrr_get_fix_ranges()171 range[2].types = rdmsr64(MSR_IA32_MTRR_FIX16K_A0000); in mtrr_get_fix_ranges()173 range[3 + i].types = rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i); in mtrr_get_fix_ranges()203 match = range[0].types == rdmsr64(MSR_IA32_MTRR_FIX64K_00000) && in mtrr_check_fix_ranges()204 range[1].types == rdmsr64(MSR_IA32_MTRR_FIX16K_80000) && in mtrr_check_fix_ranges()205 range[2].types == rdmsr64(MSR_IA32_MTRR_FIX16K_A0000); in mtrr_check_fix_ranges()208 rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i); in mtrr_check_fix_ranges()[all …]
107 ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP); in mca_get_availability()214 rdmsr64(IA32_MCG_CTL) : 0ULL; in mca_save_state()215 mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS); in mca_save_state()219 bank->mca_mci_ctl = rdmsr64(IA32_MCi_CTL(i)); in mca_save_state()220 bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i)); in mca_save_state()225 rdmsr64(IA32_MCi_MISC(i)) : 0ULL; in mca_save_state()227 rdmsr64(IA32_MCi_ADDR(i)) : 0ULL; in mca_save_state()
199 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) & ~DEBUGCTL_LBR_ENA); in i386_lbr_disable()215 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) | DEBUGCTL_LBR_ENA); in i386_lbr_enable()237 cpu_lbr_type = PERFCAP_LBR_TYPE(rdmsr64(MSR_IA32_PERF_CAPABILITIES)); in i386_lbr_init()301 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) | DEBUGCTL_LBR_ENA); in i386_lbr_init()449 old_pcb->lbrs.lbrs[i].from_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from); in i386_lbr_synch()450 old_pcb->lbrs.lbrs[i].to_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to); in i386_lbr_synch()451 old_pcb->lbrs.lbrs[i].info = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_info); in i386_lbr_synch()455 old_pcb->lbrs.lbrs[i].from_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from); in i386_lbr_synch()456 old_pcb->lbrs.lbrs[i].to_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to); in i386_lbr_synch()461 old_pcb->lbrs.lbr_tos = rdmsr64(MSR_IA32_LASTBRANCH_TOS); in i386_lbr_synch()[all …]
221 msr_flex_ratio = rdmsr64(MSR_FLEX_RATIO); in tsc_init()222 msr_platform_info = rdmsr64(MSR_PLATFORM_INFO); in tsc_init()248 prfsts = rdmsr64(IA32_PERF_STS); in tsc_init()
278 rdmsr64(MSR_IA32_TSX_FORCE_ABORT) | MSR_IA32_TSXFA_RTM_FORCE_ABORT); in do_cwas()285 uint64_t mcuoptctrl = rdmsr64(MSR_IA32_MCU_OPT_CTRL); in do_cwas()661 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32); in cpuid_set_generic_info()673 info_p->cpuid_processor_flag = (rdmsr64(MSR_IA32_PLATFORM_ID) >> 50) & 0x7; in cpuid_set_generic_info()990 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info()1001 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info()1513 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES); in cpuid_wa_required()1555 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES); in cpuid_wa_required()1578 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES); in cpuid_wa_required()
265 return rdmsr64(LAPIC_MSR(ICR)); in x2apic_read_icr()375 if (rdmsr64(MSR_IA32_APIC_BASE) & MSR_IA32_APIC_BASE_BSP) { in lapic_init_slave()821 return rdmsr64(MSR_IA32_TSC_DEADLINE); in lapic_get_tsc_deadline_timer()
501 rdmsr64(uint32_t msr) in rdmsr64() function
250 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE)); in kprint_state()251 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE)); in kprint_state()
520 wrmsr64(MSR_IA32_EFER, rdmsr64(MSR_IA32_EFER) | MSR_IA32_EFER_SCE); in cpu_syscall_init()
809 gsbase = rdmsr64(MSR_IA32_GS_BASE); in vstart()
71 return rdmsr64( MSR_IA32_PERF_FIXED_CTR_CTRL ); in IA32_FIXED_CTR_CTRL()88 return rdmsr64(MSR_IA32_PERFCTR0 + ctr); in IA32_PMCx()101 return rdmsr64(MSR_IA32_EVNTSEL0 + ctr); in IA32_PERFEVTSELx()248 global = rdmsr64(MSR_IA32_PERF_GLOBAL_CTRL); in set_running_fixed()274 global = rdmsr64(MSR_IA32_PERF_GLOBAL_CTRL); in set_running_configurable()410 status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS); in kpc_get_configurable_counters()661 status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS); in kpc_pmi_handler()
275 uint64_t status = rdmsr64(GLOBAL_STATUS); in mt_check_for_pmi()
66 (rdmsr64(MSR_IA32_FEATURE_CONTROL) & MSR_IA32_FEATCTL_VMXON); in vmxon_is_enabled()107 msr_image = rdmsr64(MSR_IA32_FEATURE_CONTROL); in vmx_enable()150 #define rdmsr_mask(msr, mask) (uint32_t)(rdmsr64(msr) & (mask)) in vmx_cpu_init()
72 #define VMX_CAP(msr, shift, mask) (rdmsr64(msr) & ((mask) << (shift)))
135 uint64_t gsbase = rdmsr64(MSR_IA32_GS_BASE); in kprintf()
315 if (rdmsr64(MSR_IA32_GS_BASE) == EARLY_GSBASE_MAGIC) { in ensure_gsbase()
394 *value = rdmsr64(msr); in kdp_machine_msr64_read()
391 uint64_t misc_enable = rdmsr64(MSR_IA32_MISC_ENABLE); in commpage_init_cpu_capabilities()