| /xnu-12377.81.4/osfmk/arm64/ |
| H A D | start.s | 51 msr VBAR_EL1, x0
62 msr TCR_EL1, x1
72 msr TTBR1_EL1, x0
84 msr SPSel, #0 // Back to SP0
87 msr SCTLR_EL1, x0
130 msr OSLAR_EL1, xzr
131 msr DAIFSet, #(DAIFSC_ALL) // Disable all interrupts
137 msr VBAR_EL1, x0
200 msr TPIDR_EL1, x13
329 msr TPIDR_EL0, x0
[all …]
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| H A D | pinst.s | 63 msr TTBR1_EL1, x0
67 msr VBAR_EL1, x0
71 msr TCR_EL1, x0
76 msr SCTLR_EL1, x0
119 msr SPSel, #1
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| H A D | cswitch.s | 136 msr SSBS, x$1
142 msr TCO, x$1
147 msr UAO, x$1
152 msr DIT, x$1
188 msr TPIDR_EL1, $0 // Write new thread pointer to TPIDR_EL1
193 msr TPIDR_EL0, $2
196 msr TPIDRRO_EL0, $1
199 msr CONTEXTIDR_EL1, $1 // CONTEXTIDR_EL1 (top 32-bits are RES0).
375 msr DAIFSet, #(DAIFSC_STANDARD_DISABLE) // Disable interrupts
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| H A D | platform_tests_asm.s | 156 msr SPSel, #1
160 msr SPSel, #0
163 msr SPSel, #1
175 msr SPSel, #0
191 msr SPSel, #1
198 msr SPSel, #0
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| H A D | machine_routines_asm.s | 159 msr CPU_CFG, x13
222 msr FPSR, x1 // Write FPCR
223 msr FPCR, x2 // Write FPSR
253 msr MDSCR_EL1, x16
292 msr TTBR1_EL1, x0
311 msr TTBR0_EL1, x0
334 msr ACTLR_EL1, x0
348 msr VBAR_EL1, x0
375 msr TCR_EL1, x0
413 msr DAIFSet, #(DAIFSC_STANDARD_DISABLE) // Disable all asynchronous exceptions
[all …]
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| H A D | locore.s | 200 msr TTBR0_EL1, x18
216 msr TCR_EL1, x18
237 msr TCO, #0
344 msr ELR_EL1, x19
359 msr ELR_EL1, x18
505 msr SPSel, #0 // Switch to SP0
686 msr ELR_EL1, x16
744 msr SP_EL0, x0 // Copy the user PCB pointer to SP0
746 msr SPSel, #0 // Switch to SP0
785 msr FPSR, x2
[all …]
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| H A D | strncmp.s | 109 msr TCO, #1
179 msr TCO, #0 // Disable TCO, tag checking is enabled
222 msr TCO, #0 // Disable TCO, tag checking is enabled
231 msr TCO, #0 // Disable TCO, tag checking is enabled
249 msr TCO, #0 // Disable TCO, tag checking is enabled
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| H A D | machine_routines_asm.h | 58 msr SPSel, #1
98 msr SPSel, #0
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| H A D | exception_asm.h | 244 msr SPSel, #1
248 msr SPSel, x19
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| H A D | pac_asm.h | 244 msr RGSR_EL1, \y
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| H A D | proc_reg.h | 3470 msr $0, $2
3710 msr $0, $2
3722 msr $0, $2
3737 msr $0, $3
3753 msr \sreg, \scr1
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| H A D | caches_asm.s | 96 msr CSSELR_EL1, $0 // Select appropriate cache
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| /xnu-12377.81.4/osfmk/arm64/sptm/ |
| H A D | start_sptm.s | 99 msr TPIDR_EL1, xzr
100 msr TPIDRRO_EL0, xzr
106 msr CPU_OVRD, x9
124 msr SPSel, #1
130 msr SPSel, #0
152 msr VBAR_EL1, x9
237 msr SPSel, #1
242 msr SPSel, #0
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| /xnu-12377.81.4/osfmk/i386/ |
| H A D | proc_reg.h | 415 extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
416 extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
449 #define rdmsr(msr, lo, hi) \ argument
450 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
452 #define wrmsr(msr, lo, hi) \ argument
453 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
501 rdmsr64(uint32_t msr) in rdmsr64() argument
504 rdmsr(msr, lo, hi); in rdmsr64()
509 wrmsr64(uint32_t msr, uint64_t val) in wrmsr64() argument
511 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL)); in wrmsr64()
[all …]
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| H A D | cpuid.c | 1013 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
1014 if (0 == msr) { in cpuid_set_info()
1016 msr = (1 << 16) | 1; in cpuid_set_info()
1018 info_p->core_count = bitfield32((uint32_t)msr, 19, 16); in cpuid_set_info()
1019 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
1024 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
1025 if (0 == msr) { in cpuid_set_info()
1027 msr = (1 << 16) | 1; in cpuid_set_info()
1029 info_p->core_count = bitfield32((uint32_t)msr, 31, 16); in cpuid_set_info()
1030 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
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| /xnu-12377.81.4/osfmk/i386/vmx/ |
| H A D | vmx_cpu.h | 72 #define VMX_CAP(msr, shift, mask) (rdmsr64(msr) & ((mask) << (shift))) argument
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| H A D | vmx_cpu.c | 150 #define rdmsr_mask(msr, mask) (uint32_t)(rdmsr64(msr) & (mask)) in vmx_cpu_init() argument
409 #define CHK(msr, shift, mask) if (!VMX_CAP(msr, shift, mask)) return FALSE; in vmx_hv_support() argument
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| /xnu-12377.81.4/pexpert/pexpert/arm64/ |
| H A D | apple_arm64_regs.h | 212 msr $2, $1
217 msr $3, $1
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| /xnu-12377.81.4/osfmk/kdp/ml/i386/ |
| H A D | kdp_x86_common.c | 391 uint32_t msr = rq->address; in kdp_machine_msr64_read() local
397 *value = rdmsr64(msr); in kdp_machine_msr64_read()
405 uint32_t msr = rq->address; in kdp_machine_msr64_write() local
411 wrmsr64(msr, *value); in kdp_machine_msr64_write()
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| /xnu-12377.81.4/doc/arm/ |
| H A D | sme.md | 100 the above `msr` instructions
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