Searched refs:MMU_I_CLINE (Results 1 – 2 of 2) sorted by relevance
140 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro148 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro156 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro164 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro172 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro180 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro188 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro196 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro204 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro212 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro[all …]
66 mov x9, #((1<<MMU_I_CLINE)-1) 71 lsr x1, x1, #MMU_I_CLINE // Set cache line counter74 add x0, x0, #1<<MMU_I_CLINE // Get next cache aligned addr