Searched refs:MMU_CLINE (Results 1 – 4 of 4) sorted by relevance
| /xnu-11215.61.5/osfmk/arm64/ |
| H A D | caches_asm.s | 260 mov x9, #((1<<MMU_CLINE)-1)
265 lsr x4, x4, #MMU_CLINE // Set cache line counter
269 add x3, x3, #(1<<MMU_CLINE) // Get next cache aligned addr
277 #define CLINE_FLUSH_STRIDE MMU_CLINE
423 mov x9, #((1<<MMU_CLINE)-1)
428 lsr x1, x1, #MMU_CLINE // Set cache line counter
432 add x0, x0, #(1<<MMU_CLINE) // Get next cache aligned addr
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| H A D | proc_reg.h | 143 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ macro
151 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
159 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
167 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
175 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
183 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
191 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
199 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
207 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
215 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
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| H A D | loose_ends.c | 271 for (addr64_t dczva_offset = 0; dczva_offset < PAGE_SIZE; dczva_offset += (1ULL << MMU_CLINE)) { in bzero_phys()
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| /xnu-11215.61.5/doc/building/ |
| H A D | xnu_build_consolidation.md | 127 The L1 cache line size is still hardcoded, and defined as `MMU_CLINE`. Since this value is always t…
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