Searched refs:CORESIGHT_ED (Results 1 – 3 of 3) sorted by relevance
149 …volatile uint32_t *editr = (volatile uint32_t *)(cdp->coresight_base[CORESIGHT_ED] + EDITR_REG_OFF… in ml_dbgwrap_stuff_instr()150 …volatile uint32_t *edscr = (volatile uint32_t *)(cdp->coresight_base[CORESIGHT_ED] + EDSCR_REG_OFF… in ml_dbgwrap_stuff_instr()151 …volatile uint32_t *edrcr = (volatile uint32_t *)(cdp->coresight_base[CORESIGHT_ED] + EDRCR_REG_OFF… in ml_dbgwrap_stuff_instr()208 …volatile uint32_t *edscr = (volatile uint32_t *)(cdp->coresight_base[CORESIGHT_ED] + EDSCR_REG_OFF… in ml_dbgwrap_read_dtr()221 uint32_t dtrrx = *((volatile uint32_t*)(cdp->coresight_base[CORESIGHT_ED] + EDDTRRX_REG_OFFSET)); in ml_dbgwrap_read_dtr()222 uint32_t dtrtx = *((volatile uint32_t*)(cdp->coresight_base[CORESIGHT_ED] + EDDTRTX_REG_OFFSET)); in ml_dbgwrap_read_dtr()231 if ((cdp == NULL) || (cdp->coresight_base[CORESIGHT_ED] == 0)) { in ml_dbgwrap_halt_cpu_with_state()236 …*((volatile uint32_t *)(cdp->coresight_base[CORESIGHT_ED] + ARM_DEBUG_OFFSET_DBGLAR)) = ARM_DBG_LO… in ml_dbgwrap_halt_cpu_with_state()245 …if (*((volatile uint32_t *)(cdp->coresight_base[CORESIGHT_ED] + EDPRSR_REG_OFFSET)) & EDPRSR_OSLK)… in ml_dbgwrap_halt_cpu_with_state()
284 if (((i == CORESIGHT_ED) || (i == CORESIGHT_UTT)) && !coresight_debug_enabled) { in configure_coresight_registers()1062 if (cpu_data_ptr->coresight_base[CORESIGHT_ED]) { in ml_arm_sleep()1063 …*(volatile uint32_t *)(cpu_data_ptr->coresight_base[CORESIGHT_ED] + ARM_DEBUG_OFFSET_DBGLAR) = ARM… in ml_arm_sleep()1064 … *(volatile uint32_t *)(cpu_data_ptr->coresight_base[CORESIGHT_ED] + ARM_DEBUG_OFFSET_DBGPRCR) = 0; in ml_arm_sleep()1127 if (cpu_data_ptr->coresight_base[CORESIGHT_ED]) { in ml_arm_sleep()1128 …*(volatile uint32_t *)(cpu_data_ptr->coresight_base[CORESIGHT_ED] + ARM_DEBUG_OFFSET_DBGLAR) = ARM… in ml_arm_sleep()1129 … *(volatile uint32_t *)(cpu_data_ptr->coresight_base[CORESIGHT_ED] + ARM_DEBUG_OFFSET_DBGPRCR) = 0; in ml_arm_sleep()
2255 #define CORESIGHT_ED 0 macro