1 /* 2 * Copyright (c) 2000-2022 Apple Inc. All rights reserved. 3 */ 4 #ifndef _PEXPERT_ARM_APPLE_UART_REGS_H 5 #define _PEXPERT_ARM_APPLE_UART_REGS_H 6 7 #define APPLE_UART 8 9 typedef union { 10 uint32_t raw; 11 struct { 12 uint32_t receive_mode : 2; 13 uint32_t transmit_mode : 2; 14 uint32_t send_break_signal : 1; 15 uint32_t loop_back_mode : 1; 16 uint32_t : 1; 17 uint32_t rx_time_out_enable : 1; 18 uint32_t : 1; 19 uint32_t new_receive_time_out_interrupt_enable : 1; 20 uint32_t clock_selection : 1; 21 uint32_t receive_time_out_interrupt_enable : 1; 22 uint32_t receive_interrupt_enable : 1; 23 uint32_t transmit_interrupt : 1; 24 uint32_t error_interrupt_enable : 1; 25 uint32_t unspecified : 1; 26 uint32_t auto_baud_rate_interrupt_enable : 1; 27 uint32_t auto_baud_rate_counter_start_command : 1; 28 uint32_t mask_dma_request_enable : 1; 29 uint32_t transmit_stop : 1; 30 uint32_t sw_rst : 1; 31 uint32_t dma_burst_en : 1; 32 uint32_t : 10; 33 }; 34 } ucon_t; 35 36 typedef union { 37 uint32_t raw; 38 struct { 39 uint32_t word_length : 2; 40 uint32_t number_of_stop_bits : 1; 41 uint32_t parity_mode : 3; 42 uint32_t infra_red_mode : 1; 43 uint32_t tolerant_mode : 1; 44 uint32_t i_o_inverted_mode : 1; 45 uint32_t : 23; 46 }; 47 } ulcon_t; 48 49 typedef union { 50 uint32_t raw; 51 struct { 52 uint32_t fifo_enable : 1; 53 uint32_t rx_fifo_reset : 1; 54 uint32_t tx_fifo_reset : 1; 55 uint32_t : 1; 56 uint32_t rx_fifo_interrupt_trigger_level_dma_watermark : 2; 57 uint32_t tx_fifo_interrupt_trigger_level_dma_watermark : 2; 58 uint32_t nrts_trigger_level : 2; 59 uint32_t : 22; 60 }; 61 } ufcon_t; 62 63 typedef union { 64 uint32_t raw; 65 struct { 66 uint32_t rx_fifo_count : 4; 67 uint32_t tx_fifo_count : 4; 68 uint32_t rx_fifo_full : 1; 69 uint32_t tx_fifo_full : 1; 70 uint32_t : 22; 71 }; 72 } ufstat_t; 73 74 typedef union { 75 uint32_t raw; 76 struct { 77 uint32_t receive_buffer_data_ready : 1; 78 uint32_t transmit_buffer_empty : 1; 79 uint32_t transmitter_empty : 1; 80 uint32_t receive_time_out_interrupt_status : 1; 81 uint32_t receive_interrupt_status : 1; 82 uint32_t transmit_interrupt_status : 1; 83 uint32_t error_interrupt_status : 1; 84 uint32_t : 1; 85 uint32_t auto_baud_interrupt_status : 1; 86 uint32_t new_receive_time_out_interrupt_status : 1; 87 uint32_t : 22; 88 }; 89 } utrstat_t; 90 91 typedef union { 92 uint32_t raw; 93 struct { 94 uint32_t ubr_div : 16; 95 uint32_t sample_rate : 4; 96 uint32_t : 12; 97 }; 98 } ubrdiv_t; 99 100 typedef union { 101 uint32_t raw; 102 struct { 103 uint32_t txdata : 8; 104 uint32_t : 24; 105 }; 106 } utxh_t; 107 108 typedef union { 109 uint32_t raw; 110 struct { 111 uint32_t rxdata : 8; 112 uint32_t : 24; 113 }; 114 } urxh_t; 115 116 typedef struct { 117 ulcon_t ulcon; 118 ucon_t ucon; 119 ufcon_t ufcon; 120 uint32_t umcon; 121 utrstat_t utrstat; 122 uint32_t uerstat; 123 ufstat_t ufstat; 124 uint32_t umstat; 125 utxh_t utxh; 126 urxh_t urxh; 127 ubrdiv_t ubrdiv; 128 uint32_t uabrcnt; 129 uint8_t rsvd0[4]; 130 uint32_t utxoffset; 131 uint32_t urxoffset; 132 uint32_t uver; 133 } apple_uart_registers_t; 134 135 typedef enum { 136 UCON_CLOCK_SELECTION_PLCK = 0, 137 UCON_CLOCK_SELECTION_NCLK = 1, 138 } ucon_clock_selection_t; 139 140 typedef enum { 141 UCON_TRANSMIT_MODE_DISABLE = 0, 142 UCON_TRANSMIT_MODE_INTERRUPT_OR_POLLING = 1, 143 UCON_TRANSMIT_MODE_UNDEFINED = 2, 144 UCON_TRANSMIT_MODE_DMA = 3, 145 } ucon_transmit_mode_t; 146 147 typedef enum { 148 UCON_RECEIVE_MODE_DISABLE = 0, 149 UCON_RECEIVE_MODE_INTERRUPT_OR_POLLING = 1, 150 UCON_RECEIVE_MODE_UNDEFINED = 2, 151 UCON_RECEIVE_MODE_DMA = 3, 152 } ucon_receive_mode_t; 153 154 typedef enum { 155 ULCON_WORD_LENGTH_5_BITS = 0, 156 ULCON_WORD_LENGTH_6_BITS = 1, 157 ULCON_WORD_LENGTH_7_BITS = 2, 158 ULCON_WORD_LENGTH_8_BITS = 3, 159 } ulcon_word_length_t; 160 161 typedef enum { 162 ULCON_PARITY_MODE_NONE = 0, 163 ULCON_PARITY_MODE_ODD = 4, 164 ULCON_PARITY_MODE_EVEN = 5, 165 ULCON_PARITY_MODE_1 = 6, 166 ULCON_PARITY_MODE_0 = 7, 167 } ulcon_parity_mode_t; 168 169 typedef enum { 170 ULCON_STOP_BITS_1 = 0, 171 ULCON_STOP_BITS_2 = 1, 172 } ulcon_stop_bits_t; 173 174 typedef enum { 175 UFCON_TX_FIFO_ITL_0_BYTES = 0, 176 UFCON_TX_FIFO_ITL_4_BYTES = 1, 177 UFCON_TX_FIFO_ITL_8_BYTES = 2, 178 UFCON_TX_FIFO_ITL_12_BYTES = 3, 179 } ufcon_tx_fifo_itl_t; 180 181 #endif /* #define _PEXPERT_ARM_APPLE_UART_REGS_H */ 182