Searched refs:CACHELINE_SIZE (Results 1 – 1 of 1) sorted by relevance
944 #define CACHELINE_SIZE 64 in user_trap() macro945 THREAD_TO_PCB(thread)->insn_cacheline[CACHELINE_SIZE] = (uint8_t)(rip & (CACHELINE_SIZE - 1)); in user_trap()1345 #define CACHELINE_MASK (CACHELINE_SIZE - 1) in copy_instruction_stream()1358 &pcb->insn_cacheline[0], CACHELINE_SIZE) != 0 in copy_instruction_stream()1361 #if x86_INSTRUCTION_STATE_CACHELINE_SIZE != CACHELINE_SIZE in copy_instruction_stream()