Searched refs:MMU_I_CLINE (Results 1 – 2 of 2) sorted by relevance
155 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro163 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro171 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro179 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro187 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro195 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro203 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro211 #define MMU_I_CLINE 6 macro219 #define MMU_I_CLINE 6 macro
65 mov x9, #((1<<MMU_I_CLINE)-1) 70 lsr x1, x1, #MMU_I_CLINE // Set cache line counter73 add x0, x0, #1<<MMU_I_CLINE // Get next cache aligned addr