Searched refs:MMU_CLINE (Results 1 – 3 of 3) sorted by relevance
| /xnu-8792.81.2/osfmk/arm64/ |
| H A D | caches_asm.s | 256 mov x9, #((1<<MMU_CLINE)-1)
261 lsr x4, x4, #MMU_CLINE // Set cache line counter
265 add x3, x3, #(1<<MMU_CLINE) // Get next cache aligned addr
280 #define CLINE_FLUSH_STRIDE MMU_CLINE
407 mov x9, #((1<<MMU_CLINE)-1)
412 lsr x1, x1, #MMU_CLINE // Set cache line counter
416 add x0, x0, #(1<<MMU_CLINE) // Get next cache aligned addr
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| H A D | proc_reg.h | 158 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ macro
166 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
174 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
182 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
190 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
198 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
206 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
214 #define MMU_CLINE 6 macro
222 #define MMU_CLINE 6 macro
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| /xnu-8792.81.2/doc/ |
| H A D | xnu_build_consolidation.md | 125 The L1 cache line size is still hardcoded, and defined as `MMU_CLINE`. Since this value is always t…
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