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Searched refs:insn_cacheline (Results 1 – 4 of 4) sorted by relevance

/xnu-8792.61.2/osfmk/i386/
H A Dtrap.c941 THREAD_TO_PCB(thread)->insn_cacheline[CACHELINE_SIZE] = (uint8_t)(rip & (CACHELINE_SIZE - 1)); in user_trap()
943 &THREAD_TO_PCB(thread)->insn_cacheline[0], in user_trap()
944 sizeof(THREAD_TO_PCB(thread)->insn_cacheline) - 1); in user_trap()
1344 (*(uint64_t *)(uintptr_t)&pcb->insn_cacheline[0] != CACHELINE_DATA_NOT_PRESENT && in copy_instruction_stream()
1345 *(uint64_t *)(uintptr_t)&pcb->insn_cacheline[8] != CACHELINE_DATA_NOT_PRESENT)) { in copy_instruction_stream()
1354 &pcb->insn_cacheline[0], CACHELINE_SIZE) != 0 in copy_instruction_stream()
1360 bcopy(&pcb->insn_cacheline[0], &pcb->insn_state->insn_cacheline[0], in copy_instruction_stream()
1368 …ntf("\t[%d] cl=0x%08llx vs. ci=0x%08llx\n", i, *(uint64_t *)(uintptr_t)&pcb->insn_cacheline[i * 8], in copy_instruction_stream()
1418 (*(uint64_t *)(uintptr_t)&pcb->insn_cacheline[0] != CACHELINE_DATA_NOT_PRESENT && in copy_instruction_stream()
1419 *(uint64_t *)(uintptr_t)&pcb->insn_cacheline[8] != CACHELINE_DATA_NOT_PRESENT)) { in copy_instruction_stream()
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H A Dthread.h155 uint8_t insn_cacheline[65]; /* XXX: Hard-coded cacheline size */ member
H A Dpcb.c1811 bcopy(&src_state->insn_cacheline[0], &state->insn_cacheline[0], in machine_thread_get_state()
1814 bzero(&state->insn_cacheline[0], x86_INSTRUCTION_STATE_CACHELINE_SIZE); in machine_thread_get_state()
/xnu-8792.61.2/osfmk/mach/i386/
H A D_structs.h676 __uint8_t insn_cacheline[x86_INSTRUCTION_STATE_CACHELINE_SIZE]; variable