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Searched refs:L3 (Results 1 – 5 of 5) sorted by relevance

/xnu-8792.61.2/san/memory/
H A Dkasan-x86_64.c142 uint64_t *L3; in kasan_map_shadow_superpage_zero() local
146 L3 = (uint64_t *)(IdlePML4[addr.pml4] & ~PAGE_MASK); in kasan_map_shadow_superpage_zero()
147 if (L3 == NULL) { in kasan_map_shadow_superpage_zero()
149 L3 = (uint64_t *)phys2virt(pmem); in kasan_map_shadow_superpage_zero()
154 L3 = (uint64_t *)phys2virt(L3); in kasan_map_shadow_superpage_zero()
157 L2 = (uint64_t *)(L3[addr.pdpt] & ~PAGE_MASK); in kasan_map_shadow_superpage_zero()
161 L3[addr.pdpt] = pmem in kasan_map_shadow_superpage_zero()
198 uint64_t *L3; in kasan_map_shadow() local
203 L3 = (uint64_t *)(IdlePML4[addr.pml4] & ~PAGE_MASK); in kasan_map_shadow()
204 if (L3 == NULL) { in kasan_map_shadow()
[all …]
/xnu-8792.61.2/osfmk/i386/
H A Dcpuid.c79 L3, /* L3 (unified) cache */ enumerator
136 { 0x46, CACHE, L3, 4, 4 * M, 64 },
137 { 0x47, CACHE, L3, 8, 8 * M, 64 },
140 { 0x4A, CACHE, L3, 12, 6 * M, 64 },
141 { 0x4B, CACHE, L3, 16, 8 * M, 64 },
142 { 0x4C, CACHE, L3, 12, 12 * M, 64 },
143 { 0x4D, CACHE, L3, 16, 16 * M, 64 },
189 { 0xD0, CACHE, L3, 4, 512 * K, 64 },
190 { 0xD1, CACHE, L3, 4, 1 * M, 64 },
191 { 0xD2, CACHE, L3, 4, 2 * M, 64 },
[all …]
H A Di386_init.c560 #define L3(x, n) L2(x,n-4) L2(x,n) macro
561 #define L4(x, n) L3(x,n-8) L3(x,n)
/xnu-8792.61.2/osfmk/x86_64/
H A Dboot_pt.c74 #define L3(x, n) L2(x,n-4) L2(x,n) macro
75 #define L4(x, n) L3(x,n-8) L3(x,n)
/xnu-8792.61.2/tests/
H A Dstackshot_tests.m1449 …// L0-L2 table and non-compressed L3 block entries should always have bit 1 set; assumes L0-L2 blo…