Searched refs:MSR (Results 1 – 4 of 4) sorted by relevance
| /xnu-8020.140.41/osfmk/arm64/ |
| H A D | machine_routines.c | 196 MSR("S3_5_C15_C0_0", x); in ml_cpu_signal_type()
200 MSR("S3_5_C15_C0_1", x); in ml_cpu_signal_type()
204 MSR("S3_5_C15_C0_1", x); in ml_cpu_signal_type()
248 MSR("S3_5_C15_C3_1", abstime); in ml_cpu_signal_deferred_adjust_timer()
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| H A D | proc_reg.h | 2354 #define MSR(reg, src) __asm__ volatile ("msr " reg ", %0" :: "r" (src)) macro
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| H A D | sleh.c | 1915 MSR("S3_5_C15_C1_1", ipi_sr); in sleh_fiq()
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| /xnu-8020.140.41/tests/ |
| H A D | hvtest_x86.m | 1242 …T_ASSERT_EQ(hv_vcpu_enable_native_msr(vcpu, msrs[i], true), HV_SUCCESS, "enable native MSR %x", ms…
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