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Searched refs:MMU_I_CLINE (Results 1 – 3 of 3) sorted by relevance

/xnu-8020.140.41/osfmk/arm/
H A Dproc_reg.h284 #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */ macro
311 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro
319 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro
327 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro
335 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro
343 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro
351 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro
359 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro
367 #define MMU_I_CLINE 6 macro
375 #define MMU_I_CLINE 6 macro
H A Dcaches_asm.s120 and r2, r0, #((1<<MMU_I_CLINE)-1)
121 bic r0, r0, #((1<<MMU_I_CLINE)-1) // Cached aligned
124 mov r1, r1, LSR #MMU_I_CLINE // Set cache line counter
127 add r0, r0, #1<<MMU_I_CLINE // Get next cache aligned addr
/xnu-8020.140.41/osfmk/arm64/
H A Dcaches_asm.s65 mov x9, #((1<<MMU_I_CLINE)-1)
70 lsr x1, x1, #MMU_I_CLINE // Set cache line counter
73 add x0, x0, #1<<MMU_I_CLINE // Get next cache aligned addr