Searched refs:MMU_CLINE (Results 1 – 5 of 5) sorted by relevance
| /xnu-8020.140.41/osfmk/arm/ |
| H A D | caches_asm.s | 76 and r2, r0, #((1<<MMU_CLINE)-1)
77 bic r0, r0, #((1<<MMU_CLINE)-1) // Cached aligned
80 mov r1, r1, LSR #MMU_CLINE // Set cache line counter
84 add r0, r0, #1<<MMU_CLINE // Get next cache aligned addr
210 and r2, r0, #((1<<MMU_CLINE)-1)
211 bic r3, r0, #((1<<MMU_CLINE)-1) // Cached aligned
214 mov r12, r12, LSR #MMU_CLINE // Set cache line counter
218 add r3, r3, #1<<MMU_CLINE // Get next cache aligned addr
237 and r2, r0, #((1<<MMU_CLINE)-1)
238 bic r0, r0, #((1<<MMU_CLINE)-1) // Cached aligned
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| H A D | proc_reg.h | 288 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ macro
294 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
314 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ macro
322 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
330 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
338 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
346 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
354 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
362 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ macro
370 #define MMU_CLINE 6 macro
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| H A D | locore.s | 707 subhi r3, r3, #1<<MMU_CLINE
736 subhi r3, r3, #1<<MMU_CLINE
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| /xnu-8020.140.41/osfmk/arm64/ |
| H A D | caches_asm.s | 224 mov x9, #((1<<MMU_CLINE)-1)
229 lsr x4, x4, #MMU_CLINE // Set cache line counter
233 add x3, x3, #(1<<MMU_CLINE) // Get next cache aligned addr
248 #define CLINE_FLUSH_STRIDE MMU_CLINE
375 mov x9, #((1<<MMU_CLINE)-1)
380 lsr x1, x1, #MMU_CLINE // Set cache line counter
384 add x0, x0, #(1<<MMU_CLINE) // Get next cache aligned addr
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| /xnu-8020.140.41/doc/ |
| H A D | xnu_build_consolidation.md | 125 The L1 cache line size is still hardcoded, and defined as `MMU_CLINE`. Since this value is always t…
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