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Searched refs:wrmsr (Results 1 – 7 of 7) sorted by relevance

/xnu-8020.101.4/tests/
H A Dhvtest_x86_guest.c45 wrmsr(uint64_t msr, uint64_t value) in wrmsr() function
57 wrmsr(MSR_IA32_STAR, 0x123456789abcdef0); in native_msr_vcpu_entry()
58 wrmsr(MSR_IA32_LSTAR, 0x123456789abc); in native_msr_vcpu_entry()
59 wrmsr(MSR_IA32_CSTAR, 0x123456789abc); in native_msr_vcpu_entry()
61 wrmsr(MSR_IA32_FMASK, 0x123456789abcdef0); in native_msr_vcpu_entry()
63 wrmsr(MSR_IA32_TSC_AUX, 0x123); in native_msr_vcpu_entry()
65 wrmsr(MSR_IA32_SYSENTER_CS, 0xffff); in native_msr_vcpu_entry()
66 wrmsr(MSR_IA32_SYSENTER_ESP, 0x123456789abc); in native_msr_vcpu_entry()
67 wrmsr(MSR_IA32_SYSENTER_EIP, 0x123456789abc); in native_msr_vcpu_entry()
69 wrmsr(MSR_IA32_FS_BASE, 0x123456789abc); in native_msr_vcpu_entry()
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H A Dhvtest_x86_asm.s405 wrmsr
H A Dhvtest_x86.m1003 T_ASSERT_EQ(reason, (uint64_t)VMX_REASON_WRMSR, "check for wrmsr");
1004 T_ASSERT_EQ(get_reg(vcpu, HV_X86_RCX), 0xc0000080LL, "expected EFER wrmsr");
1005 T_ASSERT_EQ(get_reg(vcpu, HV_X86_RDX), 0x0LL, "expected EFER wrmsr higher bits 0");
1006 T_ASSERT_EQ(get_reg(vcpu, HV_X86_RAX), 0x100LL, "expected EFER wrmsr lower bits LME");
/xnu-8020.101.4/osfmk/x86_64/
H A Dstart.s115 wrmsr ;\
454 wrmsr /* Update */
490 wrmsr
494 wrmsr
H A Dlocore.s155 wrmsr
/xnu-8020.101.4/osfmk/i386/
H A Dlapic_native.c231 wrmsr(MSR_IA32_APIC_BASE, lo, hi); in x2apic_init()
258 wrmsr(LAPIC_MSR(reg), value, 0); in x2apic_write()
270 wrmsr(LAPIC_MSR(ICR), cmd, dst); in x2apic_write_icr()
603 wrmsr(MSR_IA32_APIC_BASE, lo, hi); in lapic_probe()
664 wrmsr(MSR_IA32_APIC_BASE, lo, hi); in lapic_shutdown()
H A Dproc_reg.h452 #define wrmsr(msr, lo, hi) \ macro
461 #define write_tsc(lo, hi) wrmsr(0x10, lo, hi)
511 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL)); in wrmsr64()