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Searched refs:msr (Results 1 – 22 of 22) sorted by relevance

/xnu-8020.101.4/osfmk/arm64/
H A Dstart.s51 msr VBAR_EL1, x0
62 msr TCR_EL1, x1
72 msr TTBR1_EL1, x0
84 msr SPSel, #0 // Back to SP0
87 msr SCTLR_EL1, x0
130 msr OSLAR_EL1, xzr
131 msr DAIFSet, #(DAIFSC_ALL) // Disable all interrupts
137 msr VBAR_EL1, x0
191 msr TPIDR_EL1, x13
319 msr TPIDR_EL0, x0
[all …]
H A Dpinst.s62 msr TTBR1_EL1, x0
66 msr VBAR_EL1, x0
70 msr TCR_EL1, x0
75 msr SCTLR_EL1, x0
114 msr SPSel, #1
H A Dmachine_routines_asm.s100 msr CPU_CFG, x13
161 msr FPSR, x1 // Write FPCR
162 msr FPCR, x2 // Write FPSR
191 msr MDSCR_EL1, x2
228 msr TTBR1_EL1, x0
246 msr TTBR0_EL1, x0
267 msr ACTLR_EL1, x0
280 msr VBAR_EL1, x0
306 msr TCR_EL1, x0
343 msr DAIFSet, #(DAIFSC_IRQF | DAIFSC_FIQF) // Disable IRQ
[all …]
H A Dlocore.s80 msr TTBR0_EL1, x18
96 msr TCR_EL1, x18
297 msr SPSel, #0 // Switch to SP0
393 msr SP_EL0, x0 // Copy the user PCB pointer to SP0
395 msr SPSel, #0 // Switch to SP0
489 msr ELR_EL1, lr // Return to caller
808 msr DAIFSet, #DAIFSC_ALL // Disable exceptions
856 msr DAIFSet, #DAIFSC_ALL // Disable exceptions
920 msr CPACR_EL1, x0
938 msr TPIDR_EL0, x0
[all …]
H A Dcswitch.s136 msr TPIDR_EL1, $0 // Write new thread pointer to TPIDR_EL1
141 msr TPIDR_EL0, $2
144 msr TPIDRRO_EL0, $1
148 msr CONTEXTIDR_EL1, $1 // CONTEXTIDR_EL1 (top 32-bits are RES0).
312 msr DAIFSet, #(DAIFSC_FIQF | DAIFSC_IRQF) // Disable interrupts
H A Dmachine_routines_asm.h57 msr SPSel, #1
92 msr SPSel, #0
H A Dexception_asm.h208 msr SPSel, #1
210 msr SPSel, x19
H A Dproc_reg.h2029 msr $0, $2
2287 msr $0, $2
2299 msr $0, $2
2313 msr $0, $3
2329 msr \sreg, \scr1
H A Dcaches_asm.s95 msr CSSELR_EL1, $0 // Select appropriate cache
/xnu-8020.101.4/tests/
H A Dhvtest_x86_guest.c34 rdmsr(uint64_t msr) in rdmsr() argument
36 uint32_t idx = (uint32_t)msr; in rdmsr()
45 wrmsr(uint64_t msr, uint64_t value) in wrmsr() argument
47 uint32_t idx = (uint32_t)msr; in wrmsr()
H A Dhvtest_x86.m1217 #define T_NATIVE_MSR(msr)
/xnu-8020.101.4/osfmk/i386/
H A Dproc_reg.h415 extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
416 extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
449 #define rdmsr(msr, lo, hi) \ argument
450 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
452 #define wrmsr(msr, lo, hi) \ argument
453 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
501 rdmsr64(uint32_t msr) in rdmsr64() argument
504 rdmsr(msr, lo, hi); in rdmsr64()
509 wrmsr64(uint32_t msr, uint64_t val) in wrmsr64() argument
511 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL)); in wrmsr64()
[all …]
H A Dcpuid.c990 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
991 if (0 == msr) { in cpuid_set_info()
993 msr = (1 << 16) | 1; in cpuid_set_info()
995 info_p->core_count = bitfield32((uint32_t)msr, 19, 16); in cpuid_set_info()
996 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
1001 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
1002 if (0 == msr) { in cpuid_set_info()
1004 msr = (1 << 16) | 1; in cpuid_set_info()
1006 info_p->core_count = bitfield32((uint32_t)msr, 31, 16); in cpuid_set_info()
1007 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
/xnu-8020.101.4/osfmk/i386/vmx/
H A Dvmx_cpu.h72 #define VMX_CAP(msr, shift, mask) (rdmsr64(msr) & ((mask) << (shift))) argument
H A Dvmx_cpu.c150 #define rdmsr_mask(msr, mask) (uint32_t)(rdmsr64(msr) & (mask)) in vmx_cpu_init() argument
409 #define CHK(msr, shift, mask) if (!VMX_CAP(msr, shift, mask)) return FALSE; in vmx_hv_support() argument
/xnu-8020.101.4/pexpert/pexpert/arm64/
H A Dapple_arm64_regs.h136 msr $2, $1
141 msr $3, $1
/xnu-8020.101.4/osfmk/kdp/ml/i386/
H A Dkdp_x86_common.c388 uint32_t msr = rq->address; in kdp_machine_msr64_read() local
394 *value = rdmsr64(msr); in kdp_machine_msr64_read()
402 uint32_t msr = rq->address; in kdp_machine_msr64_write() local
408 wrmsr64(msr, *value); in kdp_machine_msr64_write()
/xnu-8020.101.4/osfmk/arm/
H A Dbzero.s129 msr cpsr_f, r1
149 msr cpsr_f, r3
H A Dmachine_routines_asm.s541 msr cpsr, r3 // Restore cpsr
571 msr cpsr, r3 // Restore cpsr
601 msr cpsr, r3 // Restore cpsr
659 msr cpsr, r5 ;\
1251 msr cpsr_c, #(PSR_FIQ_MODE|PSR_FIQF|PSR_IRQF) // Change mode to FIQ with FIQ/IRQ disabled
1258 msr cpsr_c, r3 // Restore saved CPSR
1349 msr cpsr_c, #(PSR_FIQ_MODE|PSR_FIQF|PSR_IRQF) // Change mode to FIQ with FIQ/IRQ disabled.
1352 msr cpsr_c, r2 // Restore saved CPSR
H A Dbcopy.s117 msr cpsr_f, r2
134 msr cpsr_f, r12
279 msr cpsr_f, r12
H A Dlocore.s348 msr spsr_cxsf, r3 // Set spsr(svc mode cpsr)
539 msr spsr_cxsf, r3 // Set spsr(svc mode cpsr)
854 msr spsr_cxsf, r3 // Set spsr(svc mode cpsr)
1003 msr spsr_cxsf, r3 // Set spsr(svc mode cpsr)
1174 msr spsr_cxsf, r4 // Restore spsr
1751 msr spsr_cxsf, r4 // Restore the spsr
1898 msr spsr_cxsf, r4 // Restore spsr(user mode cpsr)
H A Dstart.s335 msr cpsr_x, r11 // Update cpsr