1 /* 2 * Copyright (c) 2007 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 /* 32 * Mach Operating System 33 * Copyright (c) 1991,1990 Carnegie Mellon University 34 * All Rights Reserved. 35 * 36 * Permission to use, copy, modify and distribute this software and its 37 * documentation is hereby granted, provided that both the copyright 38 * notice and this permission notice appear in all copies of the 39 * software, derivative works or modified versions, and any portions 40 * thereof, and that both notices appear in supporting documentation. 41 * 42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 45 * 46 * Carnegie Mellon requests users of this software to return to 47 * 48 * Software Distribution Coordinator or [email protected] 49 * School of Computer Science 50 * Carnegie Mellon University 51 * Pittsburgh PA 15213-3890 52 * 53 * any improvements or extensions that they make and grant Carnegie Mellon 54 * the rights to redistribute these changes. 55 */ 56 /* 57 */ 58 59 #ifndef _ARM_TRAP_H_ 60 #define _ARM_TRAP_H_ 61 62 /* 63 * Hardware trap vectors for ARM. 64 */ 65 66 #define T_RESET 0 67 #define T_UNDEF 1 68 #define T_SWI 2 69 #define T_PREFETCH_ABT 3 70 #define T_DATA_ABT 4 71 #define T_IRQ 6 72 #define T_FIQ 7 73 #define T_PMU 8 74 75 76 #define TRAP_NAMES "reset", "undefined instruction", "software interrupt", \ 77 "prefetch abort", "data abort", "irq interrupt", \ 78 "fast interrupt", "perfmon" 79 80 /* 81 * Page-fault trap codes. 82 */ 83 #define T_PF_PROT 0x1 /* protection violation */ 84 #define T_PF_WRITE 0x2 /* write access */ 85 #define T_PF_USER 0x4 /* from user state */ 86 87 #if defined(MACH_KERNEL_PRIVATE) 88 89 #if !defined(ASSEMBLER) && defined(MACH_KERNEL) 90 91 #include <arm/thread.h> 92 93 #define GDB_TRAP_INSTR1 0xe7ffdefe 94 #define GDB_TRAP_INSTR2 0xe7ffdeff 95 96 #define ARM_GDB_INSTR1 GDB_TRAP_INSTR1 97 #define ARM_GDB_INSTR2 GDB_TRAP_INSTR2 98 99 #define IS_ARM_GDB_TRAP(op) \ 100 (((op) == ARM_GDB_INSTR1) || ((op) == ARM_GDB_INSTR2)) 101 102 #define THUMB_GDB_INSTR1 (GDB_TRAP_INSTR1 & 0xFFFF) 103 #define THUMB_GDB_INSTR2 (GDB_TRAP_INSTR2 & 0xFFFF) 104 105 #define IS_THUMB_GDB_TRAP(op) \ 106 (((op) == THUMB_GDB_INSTR1) || ((op) == THUMB_GDB_INSTR2)) 107 108 109 #define ARM_STR 0x04000000 /* STR */ 110 #define ARM_STRH 0x000000B0 /* STRH */ 111 #define ARM_STRH_MASK 0x0E1000F0 /* STRH MASK */ 112 #define ARM_SDX_MASK 0x0C100000 /* SINGLE DATA TRANSFER */ 113 #define ARM_SNGL_DX_MASK 0x0C000000 /* SINGLE DATA TRANSFER MASK */ 114 #define ARM_SDX 0x04000000 115 116 #define ARM_STM 0x08000000 /* STM */ 117 #define ARM_BDX_MASK 0x0E100000 /* BLOCK DATA TRANSFER */ 118 #define ARM_BLK_MASK 0x0E000000 /* BLOCK DATA TRANSFER */ 119 #define ARM_BDX 0x08000000 /* BLOCK DATA TRANSFER */ 120 121 #define ARM_WRITE_BACK 0x00200000 122 #define ARM_BASE_REG 0x000F0000 123 #define ARM_INCREMENT 0x00800000 124 125 #define ARM_STC 0x0C000000 /* STC */ 126 #define ARM_CDX_MASK ARM_BDX_MASK /* COPROCESSOR DATA TRANSFER */ 127 #define ARM_CBLK_MASK ARM_BLK_MASK 128 #define ARM_CDX 0x0C000000 /* COPROCESSOR DATA TRANSFER */ 129 130 #define ARM_SWP 0x01000090 /* SWP */ 131 #define ARM_SWP_MASK 0x0FB00FF0 /* SWP */ 132 133 #define ARM_POST_INDEXING 0x01000000 134 #define ARM_IMMEDIATE 0x02000000 135 #define ARM_LSL 0 136 #define ARM_LSR 1 137 #define ARM_ASR 2 138 #define ARM_ROR 3 139 140 #define MCR_MASK 0x0F100F10 141 #define MCR_CP15 0x0E000F10 142 #define MCRR_MASK 0x0FF00F00 143 #define MCRR_CP15 0x0C400F00 144 145 #define arm_mcr_cp15(op) (((op)&MCR_MASK) == 0x0E000F10) 146 #define arm_mcrr_cp15(op) (((op)&0x0FF00F00) == 0x0C400F00) 147 148 #define IS_THUMB32(op) ( \ 149 (((op) & 0xE000) == 0xE000) && (((op) & 0x1800) != 0x0000)) 150 151 #define THUMB_LDR_1_MASK 0x8800 /* (1) forms of LD* instructions */ 152 #define THUMB_STR_1_MASK 0xF800 /* (1) forms of ST* instructions */ 153 #define THUMB_STR_2_MASK 0xFE00 /* (2) forms of ST* instructions */ 154 #define THUMB_STR_3_MASK 0xF800 /* (3) forms of ST* instructions */ 155 #define THUMB_PUSH_MASK 0xFE00 /* PUSH instruction */ 156 157 #define THUMB_LDRH_1 0x8800 /* LDRH(1) */ 158 #define THUMB_STMIA 0xC000 /* STMIA */ 159 #define THUMB_STR_1 0x6000 /* STR(1) */ 160 #define THUMB_STR_2 0x5000 /* STR(2) */ 161 #define THUMB_STR_3 0x9000 /* STR(3) */ 162 #define THUMB_STRB_1 0x7000 /* STRB(1) */ 163 #define THUMB_STRB_2 0x5400 /* STRB(2) */ 164 #define THUMB_STRH_1 0x8000 /* STRH(1) */ 165 #define THUMB_STRH_2 0x5200 /* STRH(2) */ 166 #define THUMB_PUSH 0xB400 /* PUSH */ 167 #define THUMB_LDMIA 0xC800 /* LDMIA */ 168 #define THUMB_POP 0xBC00 /* POP */ 169 170 171 /* 172 * Shifts, masks, and other values for load/store multiple decoding; largely needed for 173 * supporting misaligned accesses. 174 */ 175 #define THUMB_STR_1_BASE_OFFSET 8 /* Offset of the base register field */ 176 #define THUMB_PUSH_EXTRA_OFFSET 8 /* Offset of the "extra" register field */ 177 #define ARM_STM_BASE_OFFSET 16 /* Offset of the base register field */ 178 #define ARM_STM_LOAD_OFFSET 20 /* Offset of the load flag */ 179 #define ARM_STM_WBACK_OFFSET 21 /* Offset of the writeback flag */ 180 #define ARM_STM_INCR_OFFSET 23 /* Offset of the increment flag */ 181 #define ARM_STM_BEFORE_OFFSET 24 /* Offset of the pre-index flag */ 182 #define ARM_REG_LIST_LR_OFFSET 14 /* Offset of LR in the register list */ 183 #define ARM_REG_LIST_PC_OFFSET 15 /* Offset of PC in the register list */ 184 185 #define THUMB_STR_REG_LIST_MASK 0x000000FF /* Offset of the reg list is 0 */ 186 #define THUMB_STR_1_BASE_MASK 0x00000700 187 #define THUMB_PUSH_EXTRA_MASK 0x00000100 188 #define ARM_STM_REG_LIST_MASK 0x0000FFFF /* Offset of the reg list is 0 */ 189 #define ARM_STM_BASE_MASK 0x000F0000 190 #define ARM_STM_LOAD_MASK 0x00100000 191 #define ARM_STM_WBACK_MASK 0x00200000 192 #define ARM_STM_INCR_MASK 0x00800000 193 #define ARM_STM_BEFORE_MASK 0x01000000 194 #define ARM_COND_MASK 0xF0000000 /* Mask for the condition code */ 195 196 #define ARM_COND_UNCOND 0xF0000000 /* Instruction does not support condition codes */ 197 198 #define ARM_SIMD_MASK0 0xFE000000 199 #define ARM_SIMD_CODE0 0xF2000000 200 201 #define ARM_VFP_MASK0 0x0F000E10 202 #define ARM_VFP_CODE0 0x0E000A00 203 204 #define ARM_SIMD_VFP_MASK0 0x0E000E00 205 #define ARM_SIMD_VFP_CODE0 0x0C000A00 206 #define ARM_SIMD_VFP_MASK1 0xFF100000 207 #define ARM_SIMD_VFP_CODE1 0xF4000000 208 #define ARM_SIMD_VFP_MASK2 0x0F000E10 209 #define ARM_SIMD_VFP_CODE2 0x0E000A10 210 #define ARM_SIMD_VFP_MASK3 0x0FE00E00 211 #define ARM_SIMD_VFP_CODE3 0x0C400A00 212 213 #define IS_ARM_VFP(op) ( \ 214 (((op) & ARM_SIMD_MASK0) == ARM_SIMD_CODE0) \ 215 ||(((op) & ARM_VFP_MASK0) == ARM_VFP_CODE0) \ 216 ||(((op) & ARM_SIMD_VFP_MASK0) == ARM_SIMD_VFP_CODE0) \ 217 ||(((op) & ARM_SIMD_VFP_MASK1) == ARM_SIMD_VFP_CODE1) \ 218 ||(((op) & ARM_SIMD_VFP_MASK2) == ARM_SIMD_VFP_CODE2) \ 219 || (((op) & ARM_SIMD_VFP_MASK3) == ARM_SIMD_VFP_CODE3)) 220 221 #define THUMB_SIMD_MASK0 0xEF000000 222 #define THUMB_SIMD_CODE0 0xEF000000 223 224 #define THUMB_VFP_MASK0 0xEF000E10 225 #define THUMB_VFP_CODE0 0xEE000A00 226 227 #define THUMB_SIMD_VFP_MASK0 0xEE000E00 228 #define THUMB_SIMD_VFP_CODE0 0xEC000A00 229 #define THUMB_SIMD_VFP_MASK1 0xFF100000 230 #define THUMB_SIMD_VFP_CODE1 0xF9000000 231 #define THUMB_SIMD_VFP_MASK2 0xEF000E10 232 #define THUMB_SIMD_VFP_CODE2 0xEE000A10 233 #define THUMB_SIMD_VFP_MASK3 0xEFE00E00 234 #define THUMB_SIMD_VFP_CODE3 0xEC400A00 235 236 #define IS_THUMB_VFP(op) ( \ 237 (((op) & THUMB_SIMD_MASK0) == THUMB_SIMD_CODE0 ) \ 238 || (((op) & THUMB_VFP_MASK0) == THUMB_VFP_CODE0 ) \ 239 || (((op) & THUMB_SIMD_VFP_MASK0) == THUMB_SIMD_VFP_CODE0 ) \ 240 || (((op) & THUMB_SIMD_VFP_MASK1) == THUMB_SIMD_VFP_CODE1 ) \ 241 || (((op) & THUMB_SIMD_VFP_MASK2) == THUMB_SIMD_VFP_CODE2 ) \ 242 || (((op) & THUMB_SIMD_VFP_MASK3) == THUMB_SIMD_VFP_CODE3)) 243 244 extern boolean_t arm_force_fast_fault(ppnum_t, vm_prot_t, int, void *); 245 extern kern_return_t arm_fast_fault(pmap_t, vm_map_address_t, vm_prot_t, bool, bool); 246 247 /* 248 * Determines if the aborted instruction is read or write operation 249 */ 250 #define arm_fault_type(op, spsr, vaddr) \ 251 (((((op)&ARM_CDX_MASK) == ARM_STC) || \ 252 (((op)&ARM_STRH_MASK) == ARM_STRH) || \ 253 (((op)&ARM_BDX_MASK) == ARM_STM) || \ 254 (((op)&ARM_SDX_MASK) == ARM_STR)) ? \ 255 (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ)) 256 257 #define thumb_fault_type(op, spsr, vaddr) \ 258 (((((op)&THUMB_STR_1_MASK) == THUMB_STMIA) || \ 259 (((op)&THUMB_STR_1_MASK) == THUMB_STR_1) || \ 260 (((op)&THUMB_STR_2_MASK) == THUMB_STR_2) || \ 261 (((op)&THUMB_STR_3_MASK) == THUMB_STR_3) || \ 262 (((op)&THUMB_STR_1_MASK) == THUMB_STRB_1) || \ 263 (((op)&THUMB_STR_2_MASK) == THUMB_STRB_2) || \ 264 (((op)&THUMB_STR_1_MASK) == THUMB_STRH_1) || \ 265 (((op)&THUMB_STR_2_MASK) == THUMB_STRH_2) || \ 266 (((op)&THUMB_PUSH_MASK) == THUMB_PUSH)) ? \ 267 (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ)) 268 269 typedef kern_return_t (*perfCallback)( 270 int trapno, 271 struct arm_saved_state *ss, 272 int, 273 int); 274 275 #endif /* !ASSEMBLER && MACH_KERNEL */ 276 277 #endif /* MACH_KERNEL_PRIVATE */ 278 279 #endif /* _ARM_TRAP_H_ */ 280