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Searched refs:wrmsr64 (Results 1 – 15 of 15) sorted by relevance

/xnu-11417.121.6/osfmk/x86_64/
H A Dmonotonic_x86_64.c112 wrmsr64(S3_2_C15_C0_0_WR, count); in mt_core_set_snap()
115 wrmsr64(S3_2_C15_C1_0_WR, count); in mt_core_set_snap()
118 wrmsr64(S3_2_C15_C2_0_WR, count); in mt_core_set_snap()
121 wrmsr64(S3_2_C15_C3_0_WR, count); in mt_core_set_snap()
157 wrmsr64(MSR_IA32_PERF_FIXED_CTR_CTRL, mask); in mt_fixed_counter_set_ctrl_mask()
198 wrmsr64(GLOBAL_CTRL, global_en); in enable_counters()
204 wrmsr64(GLOBAL_CTRL, 0); in disable_counters()
H A Dkpc_x86.c78 return wrmsr64(MSR_IA32_PERF_FIXED_CTR0 + ctr, value); in wrIA32_FIXED_CTRx()
95 return wrmsr64(MSR_IA32_PERFCTR0 + ctr, value); in wrIA32_PMCx()
107 wrmsr64(MSR_IA32_EVNTSEL0 + ctr, value); in wrIA32_PERFEVTSELx()
243 wrmsr64( MSR_IA32_PERF_FIXED_CTR_CTRL, fixed_ctrl ); in set_running_fixed()
259 wrmsr64(MSR_IA32_PERF_GLOBAL_CTRL, global); in set_running_fixed()
287 wrmsr64(MSR_IA32_PERF_GLOBAL_CTRL, global); in set_running_configurable()
543 wrmsr64(MSR_IA32_PERF_GLOBAL_OVF_CTRL, 1ull << i); in kpc_set_reload_mp_call()
690 wrmsr64(MSR_IA32_PERF_GLOBAL_OVF_CTRL, 1ull << ctr); in kpc_pmi_handler()
/xnu-11417.121.6/osfmk/i386/
H A Dpcb_native.c198 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) & ~DEBUGCTL_LBR_ENA); in i386_lbr_disable()
214 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) | DEBUGCTL_LBR_ENA); in i386_lbr_enable()
287 wrmsr64(MSR_IA32_LBR_SELECT, LBR_SELECT_CPL_EQ_0); in i386_lbr_init()
291 wrmsr64(MSR_IA32_LBR_SELECT, 0); in i386_lbr_init()
293 wrmsr64(MSR_IA32_LBR_SELECT, LBR_SELECT_CPL_NEQ_0); in i386_lbr_init()
303 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) | DEBUGCTL_LBR_ENA); in i386_lbr_init()
492 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from, new_pcb->lbrs.lbrs[i].from_rip); in i386_switch_lbrs()
493 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to, new_pcb->lbrs.lbrs[i].to_rip); in i386_switch_lbrs()
494 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_info, new_pcb->lbrs.lbrs[i].info); in i386_switch_lbrs()
504 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from, in i386_switch_lbrs()
[all …]
H A Dmtrr.c155 wrmsr64(MSR_IA32_MTRR_PHYSBASE(i), range[i].base); in mtrr_set_var_ranges()
156 wrmsr64(MSR_IA32_MTRR_PHYSMASK(i), range[i].mask); in mtrr_set_var_ranges()
186 wrmsr64(MSR_IA32_MTRR_FIX64K_00000, range[0].types); in mtrr_set_fix_ranges()
187 wrmsr64(MSR_IA32_MTRR_FIX16K_80000, range[1].types); in mtrr_set_fix_ranges()
188 wrmsr64(MSR_IA32_MTRR_FIX16K_A0000, range[2].types); in mtrr_set_fix_ranges()
190 wrmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i, range[3 + i].types); in mtrr_set_fix_ranges()
360 wrmsr64(MSR_IA32_CR_PAT, pat); in mtrr_update_action()
365 wrmsr64(MSR_IA32_MTRR_DEF_TYPE, in mtrr_update_action()
379 wrmsr64(MSR_IA32_MTRR_DEF_TYPE, in mtrr_update_action()
H A Dmp_desc.c475 wrmsr64(MSR_IA32_GS_BASE, (uintptr_t) cdp); in cpu_desc_load()
477 wrmsr64(MSR_IA32_KERNEL_GS_BASE, (uintptr_t) cdp); in cpu_desc_load()
512 wrmsr64(MSR_IA32_SYSENTER_CS, SYSENTER_CS); in cpu_syscall_init()
513 wrmsr64(MSR_IA32_SYSENTER_EIP, DBLMAP((uintptr_t) hi64_sysenter)); in cpu_syscall_init()
514 wrmsr64(MSR_IA32_SYSENTER_ESP, current_cpu_datap()->cpu_desc_index.cdi_sstku); in cpu_syscall_init()
516 wrmsr64(MSR_IA32_EFER, rdmsr64(MSR_IA32_EFER) | MSR_IA32_EFER_SCE); in cpu_syscall_init()
523 wrmsr64(MSR_IA32_LSTAR, DBLMAP((uintptr_t) hi64_syscall)); in cpu_syscall_init()
524 wrmsr64(MSR_IA32_STAR, (((uint64_t)USER_CS) << 48) | (((uint64_t)KERNEL64_CS) << 32)); in cpu_syscall_init()
532 wrmsr64(MSR_IA32_FMASK, EFL_DF | EFL_IF | EFL_TF | EFL_NT); in cpu_syscall_init()
801 wrmsr64(MSR_IA32_GS_BASE, (uintptr_t) cdp); in cpu_data_realloc()
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H A Dmachine_check.c133 wrmsr64(IA32_MCG_CTL, IA32_MCG_CTL_ENABLE); in mca_cpu_init()
140 wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL); in mca_cpu_init()
145 wrmsr64(IA32_MCi_STATUS(i), 0ULL); in mca_cpu_init()
151 wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL); in mca_cpu_init()
156 wrmsr64(IA32_MCi_STATUS(i), 0ULL); in mca_cpu_init()
H A DDiagnostics.c409 wrmsr64(0x38F, 0x70000000FULL); in cpu_pmc_control()
410 wrmsr64(0x38D, 0x333); in cpu_pmc_control()
413 wrmsr64(0x38F, 0); in cpu_pmc_control()
414 wrmsr64(0x38D, 0); in cpu_pmc_control()
H A Dlapic_native.c162 wrmsr64(MSR_IA32_APIC_BASE, ((uint64_t)hi) << 32 | lo); in legacy_init()
163 wrmsr64(MSR_IA32_APIC_BASE, ((uint64_t)hi) << 32 | lo | MSR_IA32_APIC_BASE_ENABLE); in legacy_init()
801 wrmsr64(MSR_IA32_TSC_DEADLINE, deadline); in lapic_set_tsc_deadline_timer()
1168 wrmsr64(MSR_IA32_TSC_DEADLINE, 0); in lapic_disable_timer()
H A Ducode.c59 wrmsr64(IA32_BIOS_UPDT_TRIG, (uint64_t)(uintptr_t)&global_update->data); in update_microcode()
H A Dcpuid.c274 wrmsr64(MSR_IA32_TSX_CTRL, MSR_IA32_TSXCTRL_TSX_CPU_CLEAR | MSR_IA32_TSXCTRL_RTM_DISABLE); in do_cwas()
277 wrmsr64(MSR_IA32_TSX_FORCE_ABORT, in do_cwas()
287 wrmsr64(MSR_IA32_MCU_OPT_CTRL, mcuoptctrl); in do_cwas()
659 wrmsr64(MSR_IA32_BIOS_SIGN_ID, 0); in cpuid_set_generic_info()
1649 wrmsr64(MSR_IA32_TSX_CTRL, MSR_IA32_TSXCTRL_TSX_CPU_CLEAR | MSR_IA32_TSXCTRL_RTM_DISABLE); in cpuid_do_precpuid_was()
H A Dpal_routines.c287 wrmsr64(MSR_IA32_KERNEL_GS_BASE, in pal_efi_call_in_32bit_mode()
H A Dproc_reg.h509 wrmsr64(uint32_t msr, uint64_t val) in wrmsr64() function
H A Di386_init.c716 wrmsr64(MSR_IA32_GS_BASE, EARLY_GSBASE_MAGIC); in vstart()
/xnu-11417.121.6/osfmk/i386/vmx/
H A Dvmx_cpu.c109 wrmsr64(MSR_IA32_FEATURE_CONTROL, in vmx_enable()
/xnu-11417.121.6/osfmk/kdp/ml/i386/
H A Dkdp_x86_common.c411 wrmsr64(msr, *value); in kdp_machine_msr64_write()