1 /* 2 * Copyright (c) 2007-2024 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 /* CMU_ENDHIST */ 32 /* 33 * Mach Operating System 34 * Copyright (c) 1991,1990 Carnegie Mellon University 35 * All Rights Reserved. 36 * 37 * Permission to use, copy, modify and distribute this software and its 38 * documentation is hereby granted, provided that both the copyright 39 * notice and this permission notice appear in all copies of the 40 * software, derivative works or modified versions, and any portions 41 * thereof, and that both notices appear in supporting documentation. 42 * 43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * Carnegie Mellon requests users of this software to return to 48 * 49 * Software Distribution Coordinator or [email protected] 50 * School of Computer Science 51 * Carnegie Mellon University 52 * Pittsburgh PA 15213-3890 53 * 54 * any improvements or extensions that they make and grant Carnegie Mellon 55 * the rights to redistribute these changes. 56 */ 57 58 /* 59 * Processor registers for ARM/ARM64 60 */ 61 #ifndef _ARM64_PROC_REG_H_ 62 #define _ARM64_PROC_REG_H_ 63 64 #if !defined(KERNEL_PRIVATE) && !defined(SPTM_TESTING_PRIVATE) 65 /** 66 * This file is only exported into the internal userspace SDK exclusively for 67 * usage by the SPTM userspace testing system. Let's enforce this by error'ing 68 * the build if an SPTM-specific define is not set. If your userspace project is 69 * not the SPTM testing system, then do not use these files! 70 * 71 * This check does not apply to the kernel itself, or when this file is exported 72 * into Kernel.framework. 73 */ 74 #error This file is only included in the userspace internal SDK for the SPTM project 75 #endif /* !defined(KERNEL_PRIVATE) && !defined(SPTM_TESTING_PRIVATE) */ 76 77 #if defined (__arm64__) 78 #include <pexpert/arm64/board_config.h> 79 #elif defined (__arm__) 80 #include <pexpert/arm/board_config.h> 81 #endif 82 83 /* 84 * Processor registers for ARM 85 */ 86 #if __ARM_42BIT_PA_SPACE__ 87 /* For now, force the issue! */ 88 /* We need more VA space for the identity map to bootstrap the MMU */ 89 #undef __ARM64_PMAP_SUBPAGE_L1__ 90 #endif /* __ARM_42BIT_PA_SPACE__ */ 91 92 /* For arm platforms, create one pset per cluster */ 93 #define MAX_PSETS MAX_CPU_CLUSTERS 94 95 96 /* Thread groups are enabled on all ARM platforms (irrespective of scheduler) */ 97 #define CONFIG_THREAD_GROUPS 1 98 99 #ifdef XNU_KERNEL_PRIVATE 100 101 #if __ARM_VFP__ 102 #define ARM_VFP_DEBUG 0 103 #endif /* __ARM_VFP__ */ 104 105 #endif /* XNU_KERNEL_PRIVATE */ 106 107 /* 108 * FSR registers 109 * 110 * CPSR: Current Program Status Register 111 * SPSR: Saved Program Status Registers 112 * 113 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0 114 * +-----------------------------------------------------------+ 115 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE | 116 * +-----------------------------------------------------------+ 117 */ 118 119 /* 120 * Flags 121 */ 122 #define PSR_NF 0x80000000 /* Negative/Less than */ 123 #define PSR_ZF 0x40000000 /* Zero */ 124 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */ 125 #define PSR_VF 0x10000000 /* Overflow */ 126 127 /* 128 * Modified execution mode flags 129 */ 130 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */ 131 132 /* 133 * CPU mode 134 */ 135 #define PSR_USER_MODE 0x00000010 /* User mode */ 136 137 #define PSR_MODE_MASK 0x0000001F 138 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE) 139 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE) 140 141 #define PSR_USERDFLT PSR_USER_MODE 142 143 #define PSR_BTYPE_SHIFT (10) 144 #define PSR_BTYPE_MASK (0x3 << PSR_BTYPE_SHIFT) 145 146 /* 147 * Cache configuration 148 */ 149 150 #if defined (APPLETYPHOON) 151 152 /* I-Cache */ 153 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 154 155 /* D-Cache */ 156 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ 157 158 #elif defined (APPLETWISTER) 159 160 /* I-Cache */ 161 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 162 163 /* D-Cache */ 164 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 165 166 #elif defined (APPLEHURRICANE) 167 168 /* I-Cache */ 169 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 170 171 /* D-Cache */ 172 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 173 174 #elif defined (APPLEMONSOON) 175 176 /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */ 177 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 178 179 /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */ 180 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 181 182 #elif defined (APPLEVORTEX) 183 184 /* I-Cache, 128KB 8-way for Vortex, 48KB 6-way for Tempest. */ 185 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 186 187 /* D-Cache, 128KB 8-way for Vortex, 32KB 4-way for Tempest. */ 188 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 189 190 #elif defined (APPLELIGHTNING) 191 192 /* I-Cache, 192KB for Lightning, 96KB for Thunder, 6-way. */ 193 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 194 195 /* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */ 196 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 197 198 #elif defined (APPLEFIRESTORM) 199 200 /* I-Cache, 256KB for Firestorm, 128KB for Icestorm, 6-way. */ 201 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 202 203 /* D-Cache, 160KB for Firestorm, 8-way. 64KB for Icestorm, 6-way. */ 204 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 205 206 #elif defined (APPLEAVALANCHE) 207 208 /* I-Cache, 192KB for Avalanche, 128KB for Blizzard, 6-way. */ 209 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 210 211 /* D-Cache, 128KB for Avalanche, 8-way. 64KB for Blizzard, 8-way. */ 212 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 213 214 #elif defined (APPLEEVEREST) 215 216 /* I-Cache, 192KB for Everest, 128KB for SawTooth, 6-way. */ 217 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 218 219 /* D-Cache, 128KB for Everest, 8-way. 64KB for SawTooth, 8-way. */ 220 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 221 222 #elif defined (APPLEH16) 223 224 /* I-Cache, 192KB for AppleH16 PCore, 128KB for ECore, 6-way. */ 225 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 226 227 /* D-Cache, 128KB for AppleH16 PCore, 8-way. 64KB for ECore, 8-way. */ 228 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 229 230 #elif defined (VMAPPLE) 231 232 /* I-Cache. */ 233 #define MMU_I_CLINE 6 234 235 /* D-Cache. */ 236 #define MMU_CLINE 6 237 238 #else 239 #error processor not supported 240 #endif 241 242 #define MAX_L2_CLINE_BYTES (1 << MAX_L2_CLINE) 243 244 /* 245 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers 246 */ 247 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */ 248 #define ARM_DBG_VR_ADDRESS_MASK64 0xFFFFFFFFFFFFFFFCull /* BVR & WVR */ 249 250 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */ 251 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */ 252 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */ 253 #define ARM_DBGBCR_TYPE_IVA (0 << 21) 254 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */ 255 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20) 256 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14) 257 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13) 258 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */ 259 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */ 260 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */ 261 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */ 262 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */ 263 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */ 264 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0) 265 266 /* 267 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR) 268 */ 269 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55 270 271 /* ARM Debug registers of interest */ 272 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310) 273 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0) 274 275 /* 276 * Main ID Register (MIDR) 277 * 278 * 31 24 23 20 19 16 15 4 3 0 279 * +-----+-----+------+------+-----+ 280 * | IMP | VAR | ARCH | PNUM | REV | 281 * +-----+-----+------+------+-----+ 282 * 283 * where: 284 * IMP: Implementor code 285 * VAR: Variant number 286 * ARCH: Architecture code 287 * PNUM: Primary part number 288 * REV: Minor revision number 289 */ 290 #define MIDR_REV_SHIFT 0 291 #define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT) 292 #define MIDR_VAR_SHIFT 20 293 #define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT) 294 295 296 #if __ARM_KERNEL_PROTECT__ 297 /* 298 * __ARM_KERNEL_PROTECT__ is a feature intended to guard against potential 299 * architectural or microarchitectural vulnerabilities that could allow cores to 300 * read/access EL1-only mappings while in EL0 mode. This is achieved by 301 * removing as many mappings as possible when the core transitions to EL0 mode 302 * from EL1 mode, and restoring those mappings when the core transitions to EL1 303 * mode from EL0 mode. 304 * 305 * At the moment, this is achieved through use of ASIDs and TCR_EL1. TCR_EL1 is 306 * used to map and unmap the ordinary kernel mappings, by contracting and 307 * expanding translation zone size for TTBR1 when exiting and entering EL1, 308 * respectively: 309 * 310 * Kernel EL0 Mappings: TTBR1 mappings that must remain mapped while the core is 311 * is in EL0. 312 * Kernel EL1 Mappings: TTBR1 mappings that must be mapped while the core is in 313 * EL1. 314 * 315 * T1SZ_USER: T1SZ_BOOT + 1 316 * TTBR1_EL1_BASE_BOOT: (2^64) - (2^(64 - T1SZ_BOOT) 317 * TTBR1_EL1_BASE_USER: (2^64) - (2^(64 - T1SZ_USER) 318 * TTBR1_EL1_MAX: (2^64) - 1 319 * 320 * When in EL1, we program TCR_EL1 (specifically, TCR_EL1.T1SZ) to give the 321 * the following TTBR1 layout: 322 * 323 * TTBR1_EL1_BASE_BOOT TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 324 * +---------------------------------------------------------+ 325 * | Kernel EL0 Mappings | Kernel EL1 Mappings | 326 * +---------------------------------------------------------+ 327 * 328 * And when in EL0, we program TCR_EL1 to give the following TTBR1 layout: 329 * 330 * TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 331 * +---------------------------------------------------------+ 332 * | Kernel EL0 Mappings | 333 * +---------------------------------------------------------+ 334 * 335 * With the current implementation, both the EL0 and EL1 mappings for the kernel 336 * use otherwise empty translation tables for mapping the exception vectors (so 337 * that we do not need to TLB flush the exception vector address when switching 338 * between EL0 and EL1). The rationale here is that the TLBI would require a 339 * DSB, and DSBs can be extremely expensive. 340 * 341 * Each pmap is given two ASIDs: (n & ~1) as an EL0 ASID, and (n | 1) as an EL1 342 * ASID. The core switches between ASIDs on EL transitions, so that the TLB 343 * does not need to be fully invalidated on an EL transition. 344 * 345 * Most kernel mappings will be marked non-global in this configuration, as 346 * global mappings would be visible to userspace unless we invalidate them on 347 * eret. 348 */ 349 #if XNU_MONITOR 350 /* 351 * Please note that because we indirect through the thread register in order to 352 * locate the kernel, and because we unmap most of the kernel, the security 353 * model of the PPL is undermined by __ARM_KERNEL_PROTECT__, as we rely on 354 * kernel controlled data to direct codeflow in the exception vectors. 355 * 356 * If we want to ship XNU_MONITOR paired with __ARM_KERNEL_PROTECT__, we will 357 * need to find a performant solution to this problem. 358 */ 359 #endif 360 #endif /* __ARM_KERNEL_PROTECT */ 361 362 #if ARM_PARAMETERIZED_PMAP 363 /* 364 * ARM_PARAMETERIZED_PMAP configures the kernel to get the characteristics of 365 * the page tables (number of levels, size of the root allocation) from the 366 * pmap data structure, rather than treating them as compile-time constants. 367 * This allows the pmap code to dynamically adjust how it deals with page 368 * tables. 369 */ 370 #endif /* ARM_PARAMETERIZED_PMAP */ 371 372 #if __ARM_MIXED_PAGE_SIZE__ 373 /* 374 * __ARM_MIXED_PAGE_SIZE__ configures the kernel to support page tables that do 375 * not use the kernel page size. This is primarily meant to support running 376 * 4KB page processes on a 16KB page kernel. 377 * 378 * This only covers support in the pmap/machine dependent layers. Any support 379 * elsewhere in the kernel must be managed separately. 380 */ 381 #if !ARM_PARAMETERIZED_PMAP 382 /* 383 * Page tables that use non-kernel page sizes require us to reprogram TCR based 384 * on the page tables we are switching to. This means that the parameterized 385 * pmap support is required. 386 */ 387 #error __ARM_MIXED_PAGE_SIZE__ requires ARM_PARAMETERIZED_PMAP 388 #endif /* !ARM_PARAMETERIZED_PMAP */ 389 #if __ARM_KERNEL_PROTECT__ 390 /* 391 * Because switching the page size requires updating TCR based on the pmap, and 392 * __ARM_KERNEL_PROTECT__ relies on TCR being programmed with constants, XNU 393 * does not currently support support configurations that use both 394 * __ARM_KERNEL_PROTECT__ and __ARM_MIXED_PAGE_SIZE__. 395 */ 396 #error __ARM_MIXED_PAGE_SIZE__ and __ARM_KERNEL_PROTECT__ are mutually exclusive 397 #endif /* __ARM_KERNEL_PROTECT__ */ 398 #endif /* __ARM_MIXED_PAGE_SIZE__ */ 399 400 /* 401 * 64-bit Program Status Register (PSR64) 402 * 403 * 31 27 23 22 21 20 19 10 9 5 4 0 404 * +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+ 405 * |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M | 406 * +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+ 407 * 408 * where: 409 * NZCV: Comparison flags 410 * PAN: Privileged Access Never 411 * SS: Single step 412 * IL: Illegal state 413 * DAIF: Interrupt masks 414 * M: Mode field 415 */ 416 417 #define PSR64_NZCV_SHIFT 28 418 #define PSR64_NZCV_WIDTH 4 419 #define PSR64_NZCV_MASK (0xF << PSR64_NZCV_SHIFT) 420 421 #define PSR64_N_SHIFT 31 422 #define PSR64_N (1 << PSR64_N_SHIFT) 423 424 #define PSR64_Z_SHIFT 30 425 #define PSR64_Z (1 << PSR64_Z_SHIFT) 426 427 #define PSR64_C_SHIFT 29 428 #define PSR64_C (1 << PSR64_C_SHIFT) 429 430 #define PSR64_V_SHIFT 28 431 #define PSR64_V (1 << PSR64_V_SHIFT) 432 433 #define PSR64_TCO_SHIFT 25 434 #define PSR64_TCO (1 << PSR64_TCO_SHIFT) 435 436 #define PSR64_DIT_SHIFT 24 437 #define PSR64_DIT (1 << PSR64_DIT_SHIFT) 438 439 #define PSR64_UAO_SHIFT 23 440 #define PSR64_UAO (1 << PSR64_UAO_SHIFT) 441 442 #define PSR64_PAN_SHIFT 22 443 #define PSR64_PAN (1 << PSR64_PAN_SHIFT) 444 445 #define PSR64_SS_SHIFT 21 446 #define PSR64_SS (1 << PSR64_SS_SHIFT) 447 448 #define PSR64_IL_SHIFT 20 449 #define PSR64_IL (1 << PSR64_IL_SHIFT) 450 451 /* 452 * SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR 453 * I do not want to talk about it! 454 */ 455 #define PSR64_SSBS_SHIFT_32 23 456 #define PSR64_SSBS_SHIFT_64 12 457 #define PSR64_SSBS_32 (1 << PSR64_SSBS_SHIFT_32) 458 #define PSR64_SSBS_64 (1 << PSR64_SSBS_SHIFT_64) 459 460 /* 461 * msr DAIF, Xn and mrs Xn, DAIF transfer into 462 * and out of bits 9:6 463 */ 464 #define DAIF_DEBUG_SHIFT 9 465 #define DAIF_DEBUGF (1 << DAIF_DEBUG_SHIFT) 466 467 #define DAIF_ASYNC_SHIFT 8 468 #define DAIF_ASYNCF (1 << DAIF_ASYNC_SHIFT) 469 470 #define DAIF_IRQF_SHIFT 7 471 #define DAIF_IRQF (1 << DAIF_IRQF_SHIFT) 472 473 #define DAIF_FIQF_SHIFT 6 474 #define DAIF_FIQF (1 << DAIF_FIQF_SHIFT) 475 476 #define DAIF_ALL (DAIF_DEBUGF | DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 477 #define DAIF_STANDARD_DISABLE (DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 478 479 #define SPSR_INTERRUPTS_ENABLED(x) (!(x & DAIF_FIQF)) 480 481 #if HAS_ARM_FEAT_SSBS2 482 #define PSR64_SSBS_U32_DEFAULT PSR64_SSBS_32 483 #define PSR64_SSBS_U64_DEFAULT PSR64_SSBS_64 484 #define PSR64_SSBS_KRN_DEFAULT PSR64_SSBS_64 485 #else 486 #define PSR64_SSBS_U32_DEFAULT (0) 487 #define PSR64_SSBS_U64_DEFAULT (0) 488 #define PSR64_SSBS_KRN_DEFAULT (0) 489 #endif 490 491 /* 492 * msr DAIFSet, Xn, and msr DAIFClr, Xn transfer 493 * from bits 3:0. 494 */ 495 #define DAIFSC_DEBUGF (1 << 3) 496 #define DAIFSC_ASYNCF (1 << 2) 497 #define DAIFSC_IRQF (1 << 1) 498 #define DAIFSC_FIQF (1 << 0) 499 #define DAIFSC_ALL (DAIFSC_DEBUGF | DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 500 #define DAIFSC_STANDARD_DISABLE (DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 501 #define DAIFSC_NOASYNC (DAIFSC_DEBUGF | DAIFSC_IRQF | DAIFSC_FIQF) 502 503 /* 504 * ARM64_TODO: unify with ARM? 505 */ 506 #define PSR64_CF 0x20000000 /* Carry/Borrow/Extend */ 507 508 #define PSR64_MODE_MASK 0x1F 509 510 #define PSR64_USER_MASK PSR64_NZCV_MASK 511 512 #define PSR64_MODE_USER32_THUMB 0x20 513 514 #define PSR64_MODE_RW_SHIFT 4 515 #define PSR64_MODE_RW_64 0 516 #define PSR64_MODE_RW_32 (0x1 << PSR64_MODE_RW_SHIFT) 517 518 #define PSR64_MODE_EL_SHIFT 2 519 #define PSR64_MODE_EL_MASK (0x3 << PSR64_MODE_EL_SHIFT) 520 #define PSR64_MODE_EL3 (0x3 << PSR64_MODE_EL_SHIFT) 521 #define PSR64_MODE_EL2 (0x2 << PSR64_MODE_EL_SHIFT) 522 #define PSR64_MODE_EL1 (0x1 << PSR64_MODE_EL_SHIFT) 523 #define PSR64_MODE_EL0 0 524 525 #define PSR64_MODE_EL_KERNEL (PSR64_MODE_EL1) 526 527 #define PSR64_MODE_SPX 0x1 528 #define PSR64_MODE_SP0 0 529 530 #define PSR64_USER32_DEFAULT (PSR64_MODE_RW_32 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U32_DEFAULT) 531 #define PSR64_USER64_DEFAULT (PSR64_MODE_RW_64 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U64_DEFAULT) 532 #define PSR64_KERNEL_STANDARD (DAIF_STANDARD_DISABLE | PSR64_MODE_RW_64 | PSR64_MODE_EL1 | PSR64_MODE_SP0 | PSR64_SSBS_KRN_DEFAULT) 533 #if __ARM_PAN_AVAILABLE__ 534 #define PSR64_KERNEL_DEFAULT (PSR64_KERNEL_STANDARD | PSR64_PAN) 535 #else 536 #define PSR64_KERNEL_DEFAULT PSR64_KERNEL_STANDARD 537 #endif 538 539 #define PSR64_IS_KERNEL(x) ((x & PSR64_MODE_EL_MASK) > PSR64_MODE_EL0) 540 #define PSR64_IS_USER(x) ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL0) 541 542 #define PSR64_IS_USER32(x) (PSR64_IS_USER(x) && (x & PSR64_MODE_RW_32)) 543 #define PSR64_IS_USER64(x) (PSR64_IS_USER(x) && !(x & PSR64_MODE_RW_32)) 544 545 546 547 /* 548 * System Control Register (SCTLR) 549 */ 550 551 552 #if HAS_ARM_FEAT_SME 553 // 60 EnTP2 Enable TPIDR2_EL0 at EL0 554 #define SCTLR_OTHER (1ULL << 60) 555 #else 556 #define SCTLR_OTHER (0) 557 #endif 558 559 #define SCTLR_EPAN_ENABLED (1ULL << 57) 560 561 #define SCTLR_DSSBS (1ULL << 44) 562 563 564 #define SCTLR_EXTRA (0) 565 566 567 #define SCTLR_RESERVED ((3ULL << 28) | (1ULL << 20)) 568 #if defined(HAS_APPLE_PAC) 569 570 // 31 PACIA_ENABLED AddPACIA and AuthIA functions enabled 571 #define SCTLR_PACIA_ENABLED_SHIFT 31 572 #define SCTLR_PACIA_ENABLED (1ULL << SCTLR_PACIA_ENABLED_SHIFT) 573 // 30 PACIB_ENABLED AddPACIB and AuthIB functions enabled 574 #define SCTLR_PACIB_ENABLED (1ULL << 30) 575 // 29:28 RES1 11 576 // 27 PACDA_ENABLED AddPACDA and AuthDA functions enabled 577 #define SCTLR_PACDA_ENABLED (1ULL << 27) 578 // 13 PACDB_ENABLED AddPACDB and AuthDB functions enabled 579 #define SCTLR_PACDB_ENABLED (1ULL << 13) 580 581 #define SCTLR_PAC_KEYS_ENABLED (SCTLR_PACIA_ENABLED | SCTLR_PACIB_ENABLED | SCTLR_PACDA_ENABLED | SCTLR_PACDB_ENABLED) 582 #endif /* defined(HAS_APPLE_PAC) */ 583 584 // 36 BT1 PACIxSP acts as a BTI C landing pad rather than BTI JC at EL1 585 #define SCTLR_BT1_ENABLED (1ULL << 36) 586 587 // 35 BT0 PACIxSP acts as a BTI C landing pad rather than BTI JC at EL0 588 #define SCTLR_BT0_ENABLED (1ULL << 35) 589 590 // 26 UCI User Cache Instructions 591 #define SCTLR_UCI_ENABLED (1ULL << 26) 592 593 // 25 EE Exception Endianness 594 #define SCTLR_EE_BIG_ENDIAN (1ULL << 25) 595 596 // 24 E0E EL0 Endianness 597 #define SCTLR_E0E_BIG_ENDIAN (1ULL << 24) 598 599 // 23 SPAN Set PAN 600 #define SCTLR_PAN_UNCHANGED (1ULL << 23) 601 602 // 22 EIS Taking an exception is a context synchronization event 603 #define SCTLR_EIS (1ULL << 22) 604 605 // 21 RES0 0 606 // 20 RES1 1 607 608 // 19 WXN Writeable implies eXecute Never 609 #define SCTLR_WXN_ENABLED (1ULL << 19) 610 611 // 18 nTWE Not trap WFE from EL0 612 #define SCTLR_nTWE_WFE_ENABLED (1ULL << 18) 613 614 // 17 RES0 0 615 616 // 16 nTWI Not trap WFI from EL0 617 #define SCTRL_nTWI_WFI_ENABLED (1ULL << 16) 618 619 // 15 UCT User Cache Type register (CTR_EL0) 620 #define SCTLR_UCT_ENABLED (1ULL << 15) 621 622 // 14 DZE User Data Cache Zero (DC ZVA) 623 #define SCTLR_DZE_ENABLED (1ULL << 14) 624 625 // 12 I Instruction cache enable 626 #define SCTLR_I_ENABLED (1ULL << 12) 627 628 // 11 EOS Exception return is a context synchronization event 629 #define SCTLR_EOS (1ULL << 11) 630 631 // 10 EnRCTX EL0 Access to FEAT_SPECRES speculation restriction instructions 632 #define SCTLR_EnRCTX (1ULL << 10) 633 634 // 9 UMA User Mask Access 635 #define SCTLR_UMA_ENABLED (1ULL << 9) 636 637 // 8 SED SETEND Disable 638 #define SCTLR_SED_DISABLED (1ULL << 8) 639 640 // 7 ITD IT Disable 641 #define SCTLR_ITD_DISABLED (1ULL << 7) 642 643 // 6 RES0 0 644 645 // 5 CP15BEN CP15 Barrier ENable 646 #define SCTLR_CP15BEN_ENABLED (1ULL << 5) 647 648 // 4 SA0 Stack Alignment check for EL0 649 #define SCTLR_SA0_ENABLED (1ULL << 4) 650 651 // 3 SA Stack Alignment check 652 #define SCTLR_SA_ENABLED (1ULL << 3) 653 654 // 2 C Cache enable 655 #define SCTLR_C_ENABLED (1ULL << 2) 656 657 // 1 A Alignment check 658 #define SCTLR_A_ENABLED (1ULL << 1) 659 660 // 0 M MMU enable 661 #define SCTLR_M_ENABLED (1ULL << 0) 662 663 #if APPLEVIRTUALPLATFORM 664 #define SCTLR_EPAN_DEFAULT 0 665 /* xnu tries to set SCTLR_EL1.EPAN = 1, but it may be RaZ/WI on some hosts */ 666 #define SCTLR_EPAN_OPTIONAL SCTLR_EPAN_ENABLED 667 #elif HAS_ARM_FEAT_PAN3 668 #define SCTLR_EPAN_DEFAULT SCTLR_EPAN_ENABLED 669 #define SCTLR_EPAN_OPTIONAL 0 670 #else 671 #define SCTLR_EPAN_DEFAULT 0 672 #define SCTLR_EPAN_OPTIONAL 0 673 #endif 674 675 #if __ARM_ARCH_8_5__ 676 #define SCTLR_EIS_DEFAULT (0) 677 #define SCTLR_DSSBS_DEFAULT SCTLR_DSSBS 678 #else 679 #define SCTLR_EIS_DEFAULT (SCTLR_EIS) 680 #define SCTLR_DSSBS_DEFAULT (0) 681 #endif 682 683 #if ERET_IS_NOT_CONTEXT_SYNCHRONIZING 684 #define SCTLR_EOS_DEFAULT (0) 685 #else 686 #define SCTLR_EOS_DEFAULT (SCTLR_EOS) 687 #endif 688 689 #if HAS_APPLE_PAC 690 #define SCTLR_PAC_KEYS_DEFAULT SCTLR_PAC_KEYS_ENABLED 691 #else /* !HAS_APPLE_PAC */ 692 #define SCTLR_PAC_KEYS_DEFAULT 0 693 #endif 694 695 #if BTI_ENFORCED 696 /* In the kernel, we want PACIxSP to behave only as a BTI C */ 697 #define SCTLR_BT_DEFAULT SCTLR_BT1_ENABLED 698 #else 699 #define SCTLR_BT_DEFAULT 0 700 #endif /* BTI_ENFORCED */ 701 702 #define SCTLR_EL1_REQUIRED \ 703 (SCTLR_RESERVED | SCTLR_UCI_ENABLED | SCTLR_nTWE_WFE_ENABLED | SCTLR_DZE_ENABLED | \ 704 SCTLR_I_ENABLED | SCTLR_SED_DISABLED | SCTLR_CP15BEN_ENABLED | SCTLR_BT_DEFAULT | \ 705 SCTLR_SA0_ENABLED | SCTLR_SA_ENABLED | SCTLR_C_ENABLED | SCTLR_M_ENABLED | \ 706 SCTLR_EPAN_DEFAULT | SCTLR_EIS_DEFAULT | SCTLR_EOS_DEFAULT | SCTLR_DSSBS_DEFAULT | \ 707 SCTLR_PAC_KEYS_DEFAULT | SCTLR_OTHER) 708 709 #define SCTLR_EL1_OPTIONAL \ 710 (SCTLR_EPAN_OPTIONAL) 711 712 #define SCTLR_EL1_DEFAULT \ 713 (SCTLR_EL1_REQUIRED | SCTLR_EL1_OPTIONAL) 714 715 /* 716 * Coprocessor Access Control Register (CPACR) 717 * 718 * 31 28 27 22 21 20 19 0 719 * +---+---+------+------+--------------------+ 720 * |000|TTA|000000| FPEN |00000000000000000000| 721 * +---+---+------+------+--------------------+ 722 * 723 * where: 724 * TTA: Trace trap 725 * FPEN: Floating point enable 726 */ 727 #define CPACR_TTA_SHIFT 28 728 #define CPACR_TTA (1 << CPACR_TTA_SHIFT) 729 730 #if HAS_ARM_FEAT_SME 731 #define CPACR_SMEN_SHIFT 24 732 #define CPACR_SMEN_MASK (0x3 << CPACR_SMEN_SHIFT) 733 #define CPACR_SMEN_EL0_TRAP (0x1 << CPACR_SMEN_SHIFT) 734 #define CPACR_SMEN_ENABLE (0x3 << CPACR_SMEN_SHIFT) 735 #endif /* HAS_ARM_FEAT_SME */ 736 737 #define CPACR_FPEN_SHIFT 20 738 #define CPACR_FPEN_EL0_TRAP (0x1 << CPACR_FPEN_SHIFT) 739 #define CPACR_FPEN_ENABLE (0x3 << CPACR_FPEN_SHIFT) 740 741 #if HAS_ARM_FEAT_SME 742 #define CPACR_ZEN_SHIFT 16 743 #define CPACR_ZEN_MASK (0x3 << CPACR_ZEN_SHIFT) 744 #define CPACR_ZEN_EL0_TRAP (0x1 << CPACR_ZEN_SHIFT) 745 #define CPACR_ZEN_ENABLE (0x3 << CPACR_ZEN_SHIFT) 746 #endif /* HAS_ARM_FEAT_SME */ 747 748 /* 749 * FPSR: Floating Point Status Register 750 * 751 * 31 30 29 28 27 26 7 6 4 3 2 1 0 752 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 753 * | N| Z| C| V|QC|0000000000000000000|IDC|00|IXC|UFC|OFC|DZC|IOC| 754 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 755 */ 756 757 #define FPSR_N_SHIFT 31 758 #define FPSR_Z_SHIFT 30 759 #define FPSR_C_SHIFT 29 760 #define FPSR_V_SHIFT 28 761 #define FPSR_QC_SHIFT 27 762 #define FPSR_IDC_SHIFT 7 763 #define FPSR_IXC_SHIFT 4 764 #define FPSR_UFC_SHIFT 3 765 #define FPSR_OFC_SHIFT 2 766 #define FPSR_DZC_SHIFT 1 767 #define FPSR_IOC_SHIFT 0 768 #define FPSR_N (1 << FPSR_N_SHIFT) 769 #define FPSR_Z (1 << FPSR_Z_SHIFT) 770 #define FPSR_C (1 << FPSR_C_SHIFT) 771 #define FPSR_V (1 << FPSR_V_SHIFT) 772 #define FPSR_QC (1 << FPSR_QC_SHIFT) 773 #define FPSR_IDC (1 << FPSR_IDC_SHIFT) 774 #define FPSR_IXC (1 << FPSR_IXC_SHIFT) 775 #define FPSR_UFC (1 << FPSR_UFC_SHIFT) 776 #define FPSR_OFC (1 << FPSR_OFC_SHIFT) 777 #define FPSR_DZC (1 << FPSR_DZC_SHIFT) 778 #define FPSR_IOC (1 << FPSR_IOC_SHIFT) 779 780 /* 781 * A mask for all for all of the bits that are not RAZ for FPSR; this 782 * is primarily for converting between a 32-bit view of NEON state 783 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 784 */ 785 #define FPSR_MASK \ 786 (FPSR_N | FPSR_Z | FPSR_C | FPSR_V | FPSR_QC | FPSR_IDC | FPSR_IXC | \ 787 FPSR_UFC | FPSR_OFC | FPSR_DZC | FPSR_IOC) 788 789 /* 790 * FPCR: Floating Point Control Register 791 * 792 * 31 26 25 24 23 21 19 18 15 14 12 11 10 9 8 7 0 793 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 794 * |00000|AHP|DN|FZ|RMODE|STRIDE| 0|LEN|IDE|00|IXE|UFE|OFE|DZE|IOE|00000000| 795 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 796 */ 797 798 #define FPCR_AHP_SHIFT 26 799 #define FPCR_DN_SHIFT 25 800 #define FPCR_FZ_SHIFT 24 801 #define FPCR_RMODE_SHIFT 22 802 #define FPCR_STRIDE_SHIFT 20 803 #define FPCR_LEN_SHIFT 16 804 #define FPCR_IDE_SHIFT 15 805 #define FPCR_IXE_SHIFT 12 806 #define FPCR_UFE_SHIFT 11 807 #define FPCR_OFE_SHIFT 10 808 #define FPCR_DZE_SHIFT 9 809 #define FPCR_IOE_SHIFT 8 810 #define FPCR_AHP (1 << FPCR_AHP_SHIFT) 811 #define FPCR_DN (1 << FPCR_DN_SHIFT) 812 #define FPCR_FZ (1 << FPCR_FZ_SHIFT) 813 #define FPCR_RMODE (0x3 << FPCR_RMODE_SHIFT) 814 #define FPCR_STRIDE (0x3 << FPCR_STRIDE_SHIFT) 815 #define FPCR_LEN (0x7 << FPCR_LEN_SHIFT) 816 #define FPCR_IDE (1 << FPCR_IDE_SHIFT) 817 #define FPCR_IXE (1 << FPCR_IXE_SHIFT) 818 #define FPCR_UFE (1 << FPCR_UFE_SHIFT) 819 #define FPCR_OFE (1 << FPCR_OFE_SHIFT) 820 #define FPCR_DZE (1 << FPCR_DZE_SHIFT) 821 #define FPCR_IOE (1 << FPCR_IOE_SHIFT) 822 #define FPCR_DEFAULT (0) 823 #define FPCR_DEFAULT_32 (FPCR_DN|FPCR_FZ) 824 825 /* 826 * A mask for all for all of the bits that are not RAZ for FPCR; this 827 * is primarily for converting between a 32-bit view of NEON state 828 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 829 */ 830 #define FPCR_MASK \ 831 (FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE | FPCR_STRIDE | FPCR_LEN | \ 832 FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE) 833 834 /* 835 * Translation Control Register (TCR) 836 * 837 * Legacy: 838 * 839 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 840 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 841 * | zero |TBI1|TBI0|AS|z| IPS |z|TG1| SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ |z|TG0| SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 842 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 843 * 844 * Current (with 16KB granule support): 845 * 846 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 847 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 848 * | zero |TBI1|TBI0|AS|z| IPS | TG1 | SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ | TG0 | SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 849 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 850 * 851 * TBI1: Top Byte Ignored for TTBR1 region 852 * TBI0: Top Byte Ignored for TTBR0 region 853 * AS: ASID Size 854 * IPS: Physical Address Size limit 855 * TG1: Granule Size for TTBR1 region 856 * SH1: Shareability for TTBR1 region 857 * ORGN1: Outer Cacheability for TTBR1 region 858 * IRGN1: Inner Cacheability for TTBR1 region 859 * EPD1: Translation table walk disable for TTBR1 860 * A1: ASID selection from TTBR1 enable 861 * T1SZ: Virtual address size for TTBR1 862 * TG0: Granule Size for TTBR0 region 863 * SH0: Shareability for TTBR0 region 864 * ORGN0: Outer Cacheability for TTBR0 region 865 * IRGN0: Inner Cacheability for TTBR0 region 866 * T0SZ: Virtual address size for TTBR0 867 */ 868 869 #define TCR_T0SZ_SHIFT 0ULL 870 #define TCR_TSZ_BITS 6ULL 871 #define TCR_TSZ_MASK ((1ULL << TCR_TSZ_BITS) - 1ULL) 872 873 #define TCR_IRGN0_SHIFT 8ULL 874 #define TCR_IRGN0_DISABLED (0ULL << TCR_IRGN0_SHIFT) 875 #define TCR_IRGN0_WRITEBACK (1ULL << TCR_IRGN0_SHIFT) 876 #define TCR_IRGN0_WRITETHRU (2ULL << TCR_IRGN0_SHIFT) 877 #define TCR_IRGN0_WRITEBACKNO (3ULL << TCR_IRGN0_SHIFT) 878 879 #define TCR_ORGN0_SHIFT 10ULL 880 #define TCR_ORGN0_DISABLED (0ULL << TCR_ORGN0_SHIFT) 881 #define TCR_ORGN0_WRITEBACK (1ULL << TCR_ORGN0_SHIFT) 882 #define TCR_ORGN0_WRITETHRU (2ULL << TCR_ORGN0_SHIFT) 883 #define TCR_ORGN0_WRITEBACKNO (3ULL << TCR_ORGN0_SHIFT) 884 885 #define TCR_SH0_SHIFT 12ULL 886 #define TCR_SH0_NONE (0ULL << TCR_SH0_SHIFT) 887 #define TCR_SH0_OUTER (2ULL << TCR_SH0_SHIFT) 888 #define TCR_SH0_INNER (3ULL << TCR_SH0_SHIFT) 889 890 #define TCR_TG0_GRANULE_SHIFT (14ULL) 891 #define TCR_TG0_GRANULE_BITS (2ULL) 892 #define TCR_TG0_GRANULE_MASK ((1ULL << TCR_TG0_GRANULE_BITS) - 1ULL) 893 894 #define TCR_TG0_GRANULE_4KB (0ULL << TCR_TG0_GRANULE_SHIFT) 895 #define TCR_TG0_GRANULE_64KB (1ULL << TCR_TG0_GRANULE_SHIFT) 896 #define TCR_TG0_GRANULE_16KB (2ULL << TCR_TG0_GRANULE_SHIFT) 897 898 #if __ARM_16K_PG__ 899 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_16KB) 900 #else 901 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_4KB) 902 #endif 903 904 #define TCR_T1SZ_SHIFT 16ULL 905 906 #define TCR_A1_ASID1 (1ULL << 22ULL) 907 #define TCR_EPD1_TTBR1_DISABLED (1ULL << 23ULL) 908 909 #define TCR_IRGN1_SHIFT 24ULL 910 #define TCR_IRGN1_DISABLED (0ULL << TCR_IRGN1_SHIFT) 911 #define TCR_IRGN1_WRITEBACK (1ULL << TCR_IRGN1_SHIFT) 912 #define TCR_IRGN1_WRITETHRU (2ULL << TCR_IRGN1_SHIFT) 913 #define TCR_IRGN1_WRITEBACKNO (3ULL << TCR_IRGN1_SHIFT) 914 915 #define TCR_ORGN1_SHIFT 26ULL 916 #define TCR_ORGN1_DISABLED (0ULL << TCR_ORGN1_SHIFT) 917 #define TCR_ORGN1_WRITEBACK (1ULL << TCR_ORGN1_SHIFT) 918 #define TCR_ORGN1_WRITETHRU (2ULL << TCR_ORGN1_SHIFT) 919 #define TCR_ORGN1_WRITEBACKNO (3ULL << TCR_ORGN1_SHIFT) 920 921 #define TCR_SH1_SHIFT 28ULL 922 #define TCR_SH1_NONE (0ULL << TCR_SH1_SHIFT) 923 #define TCR_SH1_OUTER (2ULL << TCR_SH1_SHIFT) 924 #define TCR_SH1_INNER (3ULL << TCR_SH1_SHIFT) 925 926 #define TCR_TG1_GRANULE_SHIFT 30ULL 927 #define TCR_TG1_GRANULE_BITS (2ULL) 928 #define TCR_TG1_GRANULE_MASK ((1ULL << TCR_TG1_GRANULE_BITS) - 1ULL) 929 930 #define TCR_TG1_GRANULE_16KB (1ULL << TCR_TG1_GRANULE_SHIFT) 931 #define TCR_TG1_GRANULE_4KB (2ULL << TCR_TG1_GRANULE_SHIFT) 932 #define TCR_TG1_GRANULE_64KB (3ULL << TCR_TG1_GRANULE_SHIFT) 933 934 #if __ARM_16K_PG__ 935 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_16KB) 936 #else 937 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_4KB) 938 #endif 939 940 #define TCR_IPS_SHIFT 32ULL 941 #define TCR_IPS_BITS 3ULL 942 #define TCR_IPS_MASK ((1ULL << TCR_IPS_BITS) - 1ULL) 943 #define TCR_IPS_32BITS (0ULL << TCR_IPS_SHIFT) 944 #define TCR_IPS_36BITS (1ULL << TCR_IPS_SHIFT) 945 #define TCR_IPS_40BITS (2ULL << TCR_IPS_SHIFT) 946 #define TCR_IPS_42BITS (3ULL << TCR_IPS_SHIFT) 947 #define TCR_IPS_44BITS (4ULL << TCR_IPS_SHIFT) 948 #define TCR_IPS_48BITS (5ULL << TCR_IPS_SHIFT) 949 950 #define TCR_AS_16BIT_ASID (1ULL << 36) 951 #define TCR_TBI0_TOPBYTE_IGNORED (1ULL << 37) 952 #define TCR_TBI1_TOPBYTE_IGNORED (1ULL << 38) 953 #define TCR_TBID0_TBI_DATA_ONLY (1ULL << 51) 954 #define TCR_TBID1_TBI_DATA_ONLY (1ULL << 52) 955 956 #if defined(HAS_APPLE_PAC) 957 #define TCR_TBID0_ENABLE TCR_TBID0_TBI_DATA_ONLY 958 #define TCR_TBID1_ENABLE TCR_TBID1_TBI_DATA_ONLY 959 #else 960 #define TCR_TBID0_ENABLE 0 961 #define TCR_TBID1_ENABLE 0 962 #endif 963 964 #define TCR_E0PD0_BIT (1ULL << 55) 965 #define TCR_E0PD1_BIT (1ULL << 56) 966 967 #if defined(HAS_E0PD) 968 #define TCR_E0PD_VALUE (TCR_E0PD1_BIT) 969 #else 970 #define TCR_E0PD_VALUE 0 971 #endif 972 973 974 #define TCR_EL1_EXTRA 0 975 976 977 /* 978 * Multiprocessor Affinity Register (MPIDR_EL1) 979 * 980 * +64-----------------------------31+30+29-25+24+23-16+15-8+7--0+ 981 * |000000000000000000000000000000001| U|00000|MT| Aff2|Aff1|Aff0| 982 * +---------------------------------+--+-----+--+-----+----+----+ 983 * 984 * where 985 * U: Uniprocessor 986 * MT: Multi-threading at lowest affinity level 987 * Aff2: "1" - PCORE, "0" - ECORE 988 * Aff1: Cluster ID 989 * Aff0: CPU ID 990 */ 991 #define MPIDR_AFF0_SHIFT 0 992 #define MPIDR_AFF0_WIDTH 8 993 #define MPIDR_AFF0_MASK (((1 << MPIDR_AFF0_WIDTH) - 1) << MPIDR_AFF0_SHIFT) 994 #define MPIDR_AFF1_SHIFT 8 995 #define MPIDR_AFF1_WIDTH 8 996 #define MPIDR_AFF1_MASK (((1 << MPIDR_AFF1_WIDTH) - 1) << MPIDR_AFF1_SHIFT) 997 #define MPIDR_AFF2_SHIFT 16 998 #define MPIDR_AFF2_WIDTH 8 999 #define MPIDR_AFF2_MASK (((1 << MPIDR_AFF2_WIDTH) - 1) << MPIDR_AFF2_SHIFT) 1000 1001 /* 1002 * TXSZ indicates the size of the range a TTBR covers. Currently, 1003 * we support the following: 1004 * 1005 * 4KB pages, full page L1: 39 bit range. 1006 * 4KB pages, sub-page L1: 38 bit range. 1007 * 16KB pages, full page L1: 47 bit range. 1008 * 16KB pages, sub-page L1: 39 bit range. 1009 * 16KB pages, two level page tables: 36 bit range. 1010 */ 1011 #if __ARM_KERNEL_PROTECT__ 1012 /* 1013 * If we are configured to use __ARM_KERNEL_PROTECT__, the first half of the 1014 * address space is used for the mappings that will remain in place when in EL0. 1015 * As a result, 1 bit less of address space is available to the rest of the 1016 * the kernel. 1017 */ 1018 #endif /* __ARM_KERNEL_PROTECT__ */ 1019 #ifdef __ARM_16K_PG__ 1020 #if __ARM64_PMAP_SUBPAGE_L1__ 1021 #define T0SZ_BOOT 25ULL 1022 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1023 #define T0SZ_BOOT 17ULL 1024 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1025 #else /* __ARM_16K_PG__ */ 1026 #if __ARM64_PMAP_SUBPAGE_L1__ 1027 #define T0SZ_BOOT 26ULL 1028 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1029 #define T0SZ_BOOT 25ULL 1030 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1031 #endif /* __ARM_16K_PG__ */ 1032 1033 #if defined(APPLE_ARM64_ARCH_FAMILY) 1034 /* T0SZ must be the same as T1SZ */ 1035 #define T1SZ_BOOT T0SZ_BOOT 1036 #else /* defined(APPLE_ARM64_ARCH_FAMILY) */ 1037 #ifdef __ARM_16K_PG__ 1038 #if __ARM64_PMAP_SUBPAGE_L1__ 1039 #define T1SZ_BOOT 25ULL 1040 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1041 #define T1SZ_BOOT 17ULL 1042 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1043 #else /* __ARM_16K_PG__ */ 1044 #if __ARM64_PMAP_SUBPAGE_L1__ 1045 #define T1SZ_BOOT 26ULL 1046 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1047 #define T1SZ_BOOT 25ULL 1048 #endif /*__ARM64_PMAP_SUBPAGE_L1__*/ 1049 #endif /* __ARM_16K_PG__ */ 1050 #endif /* defined(APPLE_ARM64_ARCH_FAMILY) */ 1051 1052 #if __ARM_42BIT_PA_SPACE__ 1053 #define TCR_IPS_VALUE TCR_IPS_42BITS 1054 #else /* !__ARM_42BIT_PA_SPACE__ */ 1055 #define TCR_IPS_VALUE TCR_IPS_40BITS 1056 #endif /* !__ARM_42BIT_PA_SPACE__ */ 1057 1058 #if CONFIG_KERNEL_TBI 1059 #define TCR_EL1_DTBI (TCR_TBI1_TOPBYTE_IGNORED | TCR_TBID1_ENABLE) 1060 #else /* CONFIG_KERNEL_TBI */ 1061 #define TCR_EL1_DTBI 0 1062 #endif /* CONFIG_KERNEL_TBI */ 1063 1064 #if HAS_16BIT_ASID 1065 #define TCR_EL1_ASID TCR_AS_16BIT_ASID 1066 #else /* HAS_16BIT_ASID */ 1067 #define TCR_EL1_ASID 0 1068 #endif /* HAS_16BIT_ASID */ 1069 1070 #define TCR_EL1_BASE \ 1071 (TCR_IPS_VALUE | TCR_SH0_OUTER | TCR_ORGN0_WRITEBACK | \ 1072 TCR_IRGN0_WRITEBACK | (T0SZ_BOOT << TCR_T0SZ_SHIFT) | \ 1073 TCR_SH1_OUTER | TCR_ORGN1_WRITEBACK | \ 1074 TCR_IRGN1_WRITEBACK | (TCR_TG1_GRANULE_SIZE) | \ 1075 TCR_TBI0_TOPBYTE_IGNORED | (TCR_TBID0_ENABLE) | TCR_E0PD_VALUE | \ 1076 TCR_EL1_DTBI | TCR_EL1_ASID | TCR_EL1_EXTRA) 1077 1078 #if __ARM_KERNEL_PROTECT__ 1079 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1080 #define T1SZ_USER (T1SZ_BOOT + 1) 1081 #define TCR_EL1_USER (TCR_EL1_BASE | (T1SZ_USER << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1082 #else 1083 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1084 #endif /* __ARM_KERNEL_PROTECT__ */ 1085 1086 #define TCR_EL1_4KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_4KB)) 1087 #define TCR_EL1_16KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_16KB)) 1088 1089 1090 1091 1092 /* 1093 * Monitor Debug System Control Register (MDSCR) 1094 */ 1095 1096 #define MDSCR_TFO_SHIFT 31 1097 #define MDSCR_TFO (1ULL << MDSCR_TFO_SHIFT) 1098 #define MDSCR_RXFULL_SHIFT 30 1099 #define MDSCR_RXFULL (1ULL << MDSCR_RXFULL_SHIFT) 1100 #define MDSCR_TXFULL_SHIFT 29 1101 #define MDSCR_TXFULL (1ULL << MDSCR_TXFULL_SHIFT) 1102 #define MDSCR_RXO_SHIFT 27 1103 #define MDSCR_RXO (1ULL << MDSCR_RXO_SHIFT) 1104 #define MDSCR_TXU_SHIFT 26 1105 #define MDSCR_TXU (1ULL << MDSCR_TXU_SHIFT) 1106 #define MDSCR_INTDIS_SHIFT 22 1107 #define MDSCR_INTDIS_MASK (0x2U << MDSCR_INTDIS_SHIFT) 1108 #define MDSCR_TDA_SHIFT 21 1109 #define MDSCR_TDA (1ULL << MDSCR_TDA_SHIFT) 1110 #define MDSCR_SC2_SHIFT 19 1111 #define MDSCR_SC2 (1ULL << MDSCR_SC2_SHIFT) 1112 #define MDSCR_MDE_SHIFT 15 1113 #define MDSCR_MDE (1ULL << MDSCR_MDE_SHIFT) 1114 #define MDSCR_HDE_SHIFT 14 1115 #define MDSCR_HDE (1ULL << MDSCR_HDE_SHIFT) 1116 #define MDSCR_KDE_SHIFT 13 1117 #define MDSCR_KDE (1ULL << MDSCR_KDE_SHIFT) 1118 #define MDSCR_TDCC_SHIFT 12 1119 #define MDSCR_TDCC (1ULL << MDSCR_TDCC_SHIFT) 1120 #define MDSCR_ERR_SHIFT 6 1121 #define MDSCR_ERR (1ULL << MDSCR_ERR_SHIFT) 1122 #define MDSCR_SS_SHIFT 0 1123 #define MDSCR_SS (1ULL << MDSCR_SS_SHIFT) 1124 1125 /* 1126 * Translation Table Base Register (TTBR) 1127 * 1128 * 63 48 47 x x-1 0 1129 * +--------+------------------+------+ 1130 * | ASID | Base Address | zero | 1131 * +--------+------------------+------+ 1132 * 1133 */ 1134 #define TTBR_ASID_SHIFT 48 1135 #define TTBR_ASID_MASK 0xffff000000000000 1136 1137 #define TTBR_BADDR_MASK 0x0000ffffffffffff 1138 1139 /* 1140 * Memory Attribute Indirection Register 1141 * 1142 * 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 1143 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1144 * | Attr7 | Attr6 | Attr5 | Attr4 | Attr3 | Attr2 | Attr1 | Attr0 | 1145 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1146 * 1147 */ 1148 1149 #define MAIR_ATTR_SHIFT(x) (8*(x)) 1150 1151 /* Strongly ordered or device memory attributes */ 1152 #define MAIR_OUTER_STRONGLY_ORDERED 0x0 1153 #define MAIR_OUTER_DEVICE 0x0 1154 1155 #define MAIR_INNER_STRONGLY_ORDERED 0x0 1156 #define MAIR_INNER_DEVICE 0x4 1157 1158 /* Normal memory attributes */ 1159 #define MAIR_OUTER_NON_CACHEABLE 0x40 1160 #define MAIR_OUTER_WRITE_THROUGH 0x80 1161 #define MAIR_OUTER_WRITE_BACK 0xc0 1162 1163 #define MAIR_INNER_NON_CACHEABLE 0x4 1164 #define MAIR_INNER_WRITE_THROUGH 0x8 1165 #define MAIR_INNER_WRITE_BACK 0xc 1166 1167 /* Allocate policy for cacheable memory */ 1168 #define MAIR_OUTER_WRITE_ALLOCATE 0x10 1169 #define MAIR_OUTER_READ_ALLOCATE 0x20 1170 1171 #define MAIR_INNER_WRITE_ALLOCATE 0x1 1172 #define MAIR_INNER_READ_ALLOCATE 0x2 1173 1174 /* Memory Atribute Encoding */ 1175 1176 /* 1177 * Device memory types: 1178 * G (gathering): multiple reads/writes can be combined 1179 * R (reordering): reads or writes may reach device out of program order 1180 * E (early-acknowledge): writes may return immediately (e.g. PCIe posted writes) 1181 */ 1182 #if HAS_FEAT_XS 1183 1184 #define MAIR_DISABLE_XS 0x00 /* Device Memory, nGnRnE (strongly ordered), XS=1 */ 1185 #define MAIR_DISABLE 0x01 /* Device Memory, nGnRnE (strongly ordered), XS=0 */ 1186 #define MAIR_POSTED_COMBINED_REORDERED_XS 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=1 */ 1187 #define MAIR_POSTED_COMBINED_REORDERED 0x0D /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=0 */ 1188 #define MAIR_WRITECOMB 0x40 /* Normal Memory, Non-Cacheable, XS=0 */ 1189 #define MAIR_WRITETHRU 0xA0 /* Normal Memory, Write-through, XS=0 */ 1190 #define MAIR_WRITEBACK 0xFF /* Normal Memory, Write-back, XS=0 */ 1191 1192 1193 /* 1194 * Memory Attribute Index. If these values change, please also update the pmap 1195 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1196 */ 1197 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1198 #define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1199 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1200 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1201 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory), XS = 0 */ 1202 #define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1203 #define CACHE_ATTRINDX_DISABLE_XS 0x5 /* no cache, no buffer (device memory), XS = 1 */ 1204 /** 1205 * Posted mappings use XS by default, and on newer Apple SoCs there is no fabric-level distinction 1206 * between early-ack and non-early-ack, so just alias POSTED to DISABLE_XS to save a MAIR index. 1207 */ 1208 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE_XS 1209 #define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE /* no need for device-nGRE on newer SoCs, fallback to nGnRnE */ 1210 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x6 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=0 */ 1211 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED_XS 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=1 */ 1212 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1213 #define CACHE_ATTRINDX_N_INDICES (8ULL) 1214 1215 #else 1216 1217 #define MAIR_DISABLE 0x00 /* Device Memory, nGnRnE (strongly ordered) */ 1218 #define MAIR_POSTED 0x04 /* Device Memory, nGnRE (strongly ordered, posted writes) */ 1219 #define MAIR_POSTED_REORDERED 0x08 /* Device Memory, nGRE (reorderable, posted writes) */ 1220 #define MAIR_POSTED_COMBINED_REORDERED 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes) */ 1221 #define MAIR_WRITECOMB 0x44 /* Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable */ 1222 #define MAIR_WRITETHRU 0xBB /* Normal Memory, Outer Write-through, Inner Write-through */ 1223 #define MAIR_WRITEBACK 0xFF /* Normal Memory, Outer Write-back, Inner Write-back */ 1224 1225 /* 1226 * Memory Attribute Index. If these values change, please also update the pmap 1227 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1228 */ 1229 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1230 #define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1231 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1232 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1233 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory) */ 1234 #define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1235 #define CACHE_ATTRINDX_POSTED 0x5 /* no cache, no buffer, posted writes (device memory) */ 1236 #define CACHE_ATTRINDX_POSTED_REORDERED 0x6 /* no cache, reorderable access, posted writes (device memory) */ 1237 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory) */ 1238 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1239 #define CACHE_ATTRINDX_N_INDICES (8ULL) 1240 1241 #endif /* HAS_FEAT_XS */ 1242 1243 #if HAS_UCNORMAL_MEM || APPLEVIRTUALPLATFORM 1244 #define CACHE_ATTRINDX_RT CACHE_ATTRINDX_WRITECOMB 1245 #else 1246 #define CACHE_ATTRINDX_RT CACHE_ATTRINDX_DISABLE 1247 #endif /* HAS_UCNORMAL_MEM || APPLEVIRTUALPLATFORM */ 1248 1249 1250 1251 /* 1252 * Access protection bit values (TTEs and PTEs), stage 1 1253 * 1254 * Bit 1 controls access type (1=RO, 0=RW), bit 0 controls user (1=access, 0=no access) 1255 */ 1256 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */ 1257 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */ 1258 #define AP_RONA 0x2 /* priv=read-only, user=no-access */ 1259 #define AP_RORO 0x3 /* priv=read-only, user=read-only */ 1260 #define AP_MASK 0x3 /* mask to find ap bits */ 1261 1262 /* 1263 * Shareability attributes 1264 */ 1265 #define SH_NONE 0x0 /* Non shareable */ 1266 #define SH_NONE 0x0 /* Device shareable */ 1267 #define SH_DEVICE 0x2 /* Normal memory Inner non shareable - Outer non shareable */ 1268 #define SH_OUTER_MEMORY 0x2 /* Normal memory Inner shareable - Outer shareable */ 1269 #define SH_INNER_MEMORY 0x3 /* Normal memory Inner shareable - Outer non shareable */ 1270 1271 1272 /* 1273 * ARM Page Granule 1274 */ 1275 #ifdef __ARM_16K_PG__ 1276 #define ARM_PGSHIFT 14 1277 #else 1278 #define ARM_PGSHIFT 12 1279 #endif 1280 #define ARM_PGBYTES (1 << ARM_PGSHIFT) 1281 #define ARM_PGMASK (ARM_PGBYTES-1) 1282 1283 /* 1284 * L0 Translation table 1285 * 1286 * 4KB granule size: 1287 * Each translation table is 4KB 1288 * 512 64-bit entries of 512GB (2^39) of address space. 1289 * Covers 256TB (2^48) of address space. 1290 * 1291 * 16KB granule size: 1292 * Each translation table is 16KB 1293 * 2 64-bit entries of 128TB (2^47) of address space. 1294 * Covers 256TB (2^48) of address space. 1295 */ 1296 1297 /* 16K L0 */ 1298 #define ARM_16K_TT_L0_SIZE 0x0000800000000000ULL /* size of area covered by a tte */ 1299 #define ARM_16K_TT_L0_OFFMASK 0x00007fffffffffffULL /* offset within an L0 entry */ 1300 #define ARM_16K_TT_L0_SHIFT 47 /* page descriptor shift */ 1301 #define ARM_16K_TT_L0_INDEX_MASK 0x0000800000000000ULL /* mask for getting index in L0 table from virtual address */ 1302 1303 /* 4K L0 */ 1304 #define ARM_4K_TT_L0_SIZE 0x0000008000000000ULL /* size of area covered by a tte */ 1305 #define ARM_4K_TT_L0_OFFMASK 0x0000007fffffffffULL /* offset within an L0 entry */ 1306 #define ARM_4K_TT_L0_SHIFT 39 /* page descriptor shift */ 1307 #define ARM_4K_TT_L0_INDEX_MASK 0x0000ff8000000000ULL /* mask for getting index in L0 table from virtual address */ 1308 1309 /* 1310 * L1 Translation table 1311 * 1312 * 4KB granule size: 1313 * Each translation table is 4KB 1314 * 512 64-bit entries of 1GB (2^30) of address space. 1315 * Covers 512GB (2^39) of address space. 1316 * 1317 * 16KB granule size: 1318 * Each translation table is 16KB 1319 * 2048 64-bit entries of 64GB (2^36) of address space. 1320 * Covers 128TB (2^47) of address space. 1321 */ 1322 1323 /* 16K L1 */ 1324 #define ARM_16K_TT_L1_SIZE 0x0000001000000000ULL /* size of area covered by a tte */ 1325 #define ARM_16K_TT_L1_OFFMASK 0x0000000fffffffffULL /* offset within an L1 entry */ 1326 #define ARM_16K_TT_L1_SHIFT 36 /* page descriptor shift */ 1327 #if __ARM64_PMAP_SUBPAGE_L1__ && __ARM_16K_PG__ 1328 /* This config supports 512GB per TTBR. */ 1329 #define ARM_16K_TT_L1_INDEX_MASK 0x0000007000000000ULL /* mask for getting index into L1 table from virtual address */ 1330 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1331 #define ARM_16K_TT_L1_INDEX_MASK 0x00007ff000000000ULL /* mask for getting index into L1 table from virtual address */ 1332 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1333 1334 /* 4K L1 */ 1335 #define ARM_4K_TT_L1_SIZE 0x0000000040000000ULL /* size of area covered by a tte */ 1336 #define ARM_4K_TT_L1_OFFMASK 0x000000003fffffffULL /* offset within an L1 entry */ 1337 #define ARM_4K_TT_L1_SHIFT 30 /* page descriptor shift */ 1338 #if __ARM64_PMAP_SUBPAGE_L1__ && !__ARM_16K_PG__ 1339 /* This config supports 256GB per TTBR. */ 1340 #define ARM_4K_TT_L1_INDEX_MASK 0x0000003fc0000000ULL /* mask for getting index into L1 table from virtual address */ 1341 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1342 /* IPA[38:30] mask for getting index into L1 table from virtual address */ 1343 #define ARM_4K_TT_L1_INDEX_MASK 0x0000007fc0000000ULL 1344 #if __ARM_42BIT_PA_SPACE__ 1345 /* IPA[39:30] mask for getting index into L1 concatenated table from virtual address */ 1346 #define ARM_4K_TT_L1_40_BIT_CONCATENATED_INDEX_MASK 0x000000ffc0000000ULL 1347 #endif /* __ARM_42BIT_PA_SPACE__ */ 1348 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1349 1350 /* some sugar for getting pointers to page tables and entries */ 1351 1352 #define L1_TABLE_INDEX(va) (((va) & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT) 1353 #define L2_TABLE_INDEX(va) (((va) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT) 1354 #define L3_TABLE_INDEX(va) (((va) & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT) 1355 1356 #define L2_TABLE_VA(tte) ((tt_entry_t*) phystokv((*(tte)) & ARM_TTE_TABLE_MASK)) 1357 #define L3_TABLE_VA(tte2) ((pt_entry_t*) phystokv((*(tte2)) & ARM_TTE_TABLE_MASK)) 1358 1359 /* 1360 * L2 Translation table 1361 * 1362 * 4KB granule size: 1363 * Each translation table is 4KB 1364 * 512 64-bit entries of 2MB (2^21) of address space. 1365 * Covers 1GB (2^30) of address space. 1366 * 1367 * 16KB granule size: 1368 * Each translation table is 16KB 1369 * 2048 64-bit entries of 32MB (2^25) of address space. 1370 * Covers 64GB (2^36) of address space. 1371 */ 1372 1373 /* 16K L2 */ 1374 #define ARM_16K_TT_L2_SIZE 0x0000000002000000ULL /* size of area covered by a tte */ 1375 #define ARM_16K_TT_L2_OFFMASK 0x0000000001ffffffULL /* offset within an L2 entry */ 1376 #define ARM_16K_TT_L2_SHIFT 25 /* page descriptor shift */ 1377 #define ARM_16K_TT_L2_INDEX_MASK 0x0000000ffe000000ULL /* mask for getting index in L2 table from virtual address */ 1378 1379 /* 4K L2 */ 1380 #define ARM_4K_TT_L2_SIZE 0x0000000000200000ULL /* size of area covered by a tte */ 1381 #define ARM_4K_TT_L2_OFFMASK 0x00000000001fffffULL /* offset within an L2 entry */ 1382 #define ARM_4K_TT_L2_SHIFT 21 /* page descriptor shift */ 1383 #define ARM_4K_TT_L2_INDEX_MASK 0x000000003fe00000ULL /* mask for getting index in L2 table from virtual address */ 1384 1385 /* 1386 * L3 Translation table 1387 * 1388 * 4KB granule size: 1389 * Each translation table is 4KB 1390 * 512 64-bit entries of 4KB (2^12) of address space. 1391 * Covers 2MB (2^21) of address space. 1392 * 1393 * 16KB granule size: 1394 * Each translation table is 16KB 1395 * 2048 64-bit entries of 16KB (2^14) of address space. 1396 * Covers 32MB (2^25) of address space. 1397 */ 1398 1399 /* 16K L3 */ 1400 #define ARM_16K_TT_L3_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 1401 #define ARM_16K_TT_L3_OFFMASK 0x0000000000003fffULL /* offset within L3 PTE */ 1402 #define ARM_16K_TT_L3_SHIFT 14 /* page descriptor shift */ 1403 #define ARM_16K_TT_L3_INDEX_MASK 0x0000000001ffc000ULL /* mask for page descriptor index */ 1404 1405 /* 4K L3 */ 1406 #define ARM_4K_TT_L3_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 1407 #define ARM_4K_TT_L3_OFFMASK 0x0000000000000fffULL /* offset within L3 PTE */ 1408 #define ARM_4K_TT_L3_SHIFT 12 /* page descriptor shift */ 1409 #define ARM_4K_TT_L3_INDEX_MASK 0x00000000001ff000ULL /* mask for page descriptor index */ 1410 1411 #ifdef __ARM_16K_PG__ 1412 1413 /* Native L0 defines */ 1414 #define ARM_TT_L0_SIZE ARM_16K_TT_L0_SIZE 1415 #define ARM_TT_L0_OFFMASK ARM_16K_TT_L0_OFFMASK 1416 #define ARM_TT_L0_SHIFT ARM_16K_TT_L0_SHIFT 1417 #define ARM_TT_L0_INDEX_MASK ARM_16K_TT_L0_INDEX_MASK 1418 1419 /* Native L1 defines */ 1420 #define ARM_TT_L1_SIZE ARM_16K_TT_L1_SIZE 1421 #define ARM_TT_L1_OFFMASK ARM_16K_TT_L1_OFFMASK 1422 #define ARM_TT_L1_SHIFT ARM_16K_TT_L1_SHIFT 1423 #define ARM_TT_L1_INDEX_MASK ARM_16K_TT_L1_INDEX_MASK 1424 1425 /* Native L2 defines */ 1426 #define ARM_TT_L2_SIZE ARM_16K_TT_L2_SIZE 1427 #define ARM_TT_L2_OFFMASK ARM_16K_TT_L2_OFFMASK 1428 #define ARM_TT_L2_SHIFT ARM_16K_TT_L2_SHIFT 1429 #define ARM_TT_L2_INDEX_MASK ARM_16K_TT_L2_INDEX_MASK 1430 1431 /* Native L3 defines */ 1432 #define ARM_TT_L3_SIZE ARM_16K_TT_L3_SIZE 1433 #define ARM_TT_L3_OFFMASK ARM_16K_TT_L3_OFFMASK 1434 #define ARM_TT_L3_SHIFT ARM_16K_TT_L3_SHIFT 1435 #define ARM_TT_L3_INDEX_MASK ARM_16K_TT_L3_INDEX_MASK 1436 1437 #else /* !__ARM_16K_PG__ */ 1438 1439 /* Native L0 defines */ 1440 #define ARM_TT_L0_SIZE ARM_4K_TT_L0_SIZE 1441 #define ARM_TT_L0_OFFMASK ARM_4K_TT_L0_OFFMASK 1442 #define ARM_TT_L0_SHIFT ARM_4K_TT_L0_SHIFT 1443 #define ARM_TT_L0_INDEX_MASK ARM_4K_TT_L0_INDEX_MASK 1444 1445 /* Native L1 defines */ 1446 #define ARM_TT_L1_SIZE ARM_4K_TT_L1_SIZE 1447 #define ARM_TT_L1_OFFMASK ARM_4K_TT_L1_OFFMASK 1448 #define ARM_TT_L1_SHIFT ARM_4K_TT_L1_SHIFT 1449 #define ARM_TT_L1_INDEX_MASK ARM_4K_TT_L1_INDEX_MASK 1450 1451 /* Native L2 defines */ 1452 #define ARM_TT_L2_SIZE ARM_4K_TT_L2_SIZE 1453 #define ARM_TT_L2_OFFMASK ARM_4K_TT_L2_OFFMASK 1454 #define ARM_TT_L2_SHIFT ARM_4K_TT_L2_SHIFT 1455 #define ARM_TT_L2_INDEX_MASK ARM_4K_TT_L2_INDEX_MASK 1456 1457 /* Native L3 defines */ 1458 #define ARM_TT_L3_SIZE ARM_4K_TT_L3_SIZE 1459 #define ARM_TT_L3_OFFMASK ARM_4K_TT_L3_OFFMASK 1460 #define ARM_TT_L3_SHIFT ARM_4K_TT_L3_SHIFT 1461 #define ARM_TT_L3_INDEX_MASK ARM_4K_TT_L3_INDEX_MASK 1462 1463 #endif /* !__ARM_16K_PG__ */ 1464 1465 /* 1466 * Convenience definitions for: 1467 * ARM_TT_LEAF: The last level of the configured page table format. 1468 * ARM_TT_TWIG: The second to last level of the configured page table format. 1469 * ARM_TT_ROOT: The first level of the configured page table format. 1470 * 1471 * My apologies to any botanists who may be reading this. 1472 */ 1473 #define ARM_TT_LEAF_SIZE ARM_TT_L3_SIZE 1474 #define ARM_TT_LEAF_OFFMASK ARM_TT_L3_OFFMASK 1475 #define ARM_TT_LEAF_SHIFT ARM_TT_L3_SHIFT 1476 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L3_INDEX_MASK 1477 1478 #define ARM_TT_TWIG_SIZE ARM_TT_L2_SIZE 1479 #define ARM_TT_TWIG_OFFMASK ARM_TT_L2_OFFMASK 1480 #define ARM_TT_TWIG_SHIFT ARM_TT_L2_SHIFT 1481 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L2_INDEX_MASK 1482 1483 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE 1484 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK 1485 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT 1486 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK 1487 1488 /* 1489 * 4KB granule size: 1490 * 1491 * Level 0 Translation Table Entry 1492 * 1493 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1494 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1495 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 1496 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1497 * 1498 * Level 1 Translation Table Entry 1499 * 1500 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1501 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1502 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 1503 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1504 * 1505 * Level 1 Translation Block Entry 1506 * 1507 * 63 59 58 55 54 53 52 51 48 47 30 29 12 11 10 9 8 7 6 5 4 2 1 0 1508 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1509 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:30] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1510 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1511 * 1512 * Level 2 Translation Table Entry 1513 * 1514 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1515 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1516 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 1517 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1518 * 1519 * Level 2 Translation Block Entry 1520 * 1521 * 63 59 58 55 54 53 52 51 48 47 21 20 12 11 10 9 8 7 6 5 4 2 1 0 1522 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1523 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:21] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1524 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1525 * 1526 * 16KB granule size: 1527 * 1528 * Level 0 Translation Table Entry 1529 * 1530 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1531 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1532 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 1533 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1534 * 1535 * Level 1 Translation Table Entry 1536 * 1537 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1538 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1539 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 1540 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1541 * 1542 * Level 2 Translation Table Entry 1543 * 1544 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1545 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1546 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 1547 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1548 * 1549 * Level 2 Translation Block Entry 1550 * 1551 * 63 59 58 55 54 53 52 51 48 47 25 24 12 11 10 9 8 7 6 5 4 2 1 0 1552 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1553 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:25] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1554 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1555 * 1556 * where: 1557 * nG: notGlobal bit 1558 * SH: Shareability field 1559 * AP: access protection 1560 * XN: eXecute Never bit 1561 * PXN: Privilege eXecute Never bit 1562 * NS: Non-Secure bit 1563 * HINT: 16 entry continuguous output hint 1564 * AttrIdx: Memory Attribute Index 1565 */ 1566 1567 #define TTE_SHIFT 3 /* shift width of a tte (sizeof(tte) == (1 << TTE_SHIFT)) */ 1568 #ifdef __ARM_16K_PG__ 1569 #define TTE_PGENTRIES (16384 >> TTE_SHIFT) /* number of ttes per page */ 1570 #else 1571 #define TTE_PGENTRIES (4096 >> TTE_SHIFT) /* number of ttes per page */ 1572 #endif 1573 1574 #define ARM_TTE_MAX (TTE_PGENTRIES) 1575 1576 #define ARM_TTE_EMPTY 0x0000000000000000ULL /* unasigned - invalid entry */ 1577 #define ARM_TTE_TYPE_FAULT 0x0000000000000000ULL /* unasigned - invalid entry */ 1578 1579 #define ARM_TTE_VALID 0x0000000000000001ULL /* valid entry */ 1580 1581 #define ARM_TTE_TYPE_MASK 0x0000000000000002ULL /* mask for extracting the type */ 1582 #define ARM_TTE_TYPE_TABLE 0x0000000000000002ULL /* page table type */ 1583 #define ARM_TTE_TYPE_BLOCK 0x0000000000000000ULL /* block entry type */ 1584 #define ARM_TTE_TYPE_L3BLOCK 0x0000000000000002ULL 1585 1586 #ifdef __ARM_16K_PG__ 1587 /* 1588 * Note that L0/L1 block entries are disallowed for the 16KB granule size; what 1589 * are we doing with these? 1590 */ 1591 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 16KB L3 TTE entry */ 1592 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 128TB section */ 1593 #define ARM_TTE_BLOCK_L1_MASK 0x0000fff000000000ULL /* mask to extract phys address from L1 block entry */ 1594 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 64GB section */ 1595 #define ARM_TTE_BLOCK_L2_MASK 0x0000fffffe000000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 1596 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 32MB section */ 1597 #else 1598 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 4KB L3 TTE entry */ 1599 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 2048GB section */ 1600 #define ARM_TTE_BLOCK_L1_MASK 0x0000ffffc0000000ULL /* mask to extract phys address from L1 block entry */ 1601 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 1GB section */ 1602 #define ARM_TTE_BLOCK_L2_MASK 0x0000ffffffe00000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 1603 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 2MB section */ 1604 #endif 1605 1606 #define ARM_TTE_BLOCK_APSHIFT 6 1607 #define ARM_TTE_BLOCK_AP(x) ((x)<<ARM_TTE_BLOCK_APSHIFT) /* access protection */ 1608 #define ARM_TTE_BLOCK_APMASK (0x3 << ARM_TTE_BLOCK_APSHIFT) 1609 1610 #define ARM_TTE_BLOCK_ATTRINDX(x) ((x) << 2) /* memory attributes index */ 1611 #define ARM_TTE_BLOCK_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */ 1612 1613 #define ARM_TTE_BLOCK_SH(x) ((x) << 8) /* access shared */ 1614 #define ARM_TTE_BLOCK_SHMASK (0x3ULL << 8) /* mask access shared */ 1615 1616 #define ARM_TTE_BLOCK_AF 0x0000000000000400ULL /* value for access */ 1617 #define ARM_TTE_BLOCK_AFMASK 0x0000000000000400ULL /* access mask */ 1618 1619 #define ARM_TTE_BLOCK_NG 0x0000000000000800ULL /* value for a global mapping */ 1620 #define ARM_TTE_BLOCK_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 1621 1622 #define ARM_TTE_BLOCK_NS 0x0000000000000020ULL /* value for a secure mapping */ 1623 #define ARM_TTE_BLOCK_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 1624 1625 #define ARM_TTE_BLOCK_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 1626 #define ARM_TTE_BLOCK_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 1627 1628 #define ARM_TTE_BLOCK_NX 0x0040000000000000ULL /* value for no execute */ 1629 #define ARM_TTE_BLOCK_NXMASK 0x0040000000000000ULL /* no execute mask */ 1630 1631 #define ARM_TTE_BLOCK_WIRED 0x0400000000000000ULL /* value for software wired bit */ 1632 #define ARM_TTE_BLOCK_WIREDMASK 0x0400000000000000ULL /* software wired mask */ 1633 1634 #define ARM_TTE_BLOCK_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 1635 #define ARM_TTE_BLOCK_WRITEABLEMASK 0x0800000000000000ULL /* software writeable mask */ 1636 1637 #define ARM_TTE_TABLE_MASK 0x0000fffffffff000ULL /* mask for extracting pointer to next table (works at any level) */ 1638 1639 #define ARM_TTE_TABLE_APSHIFT 61 1640 #define ARM_TTE_TABLE_AP_NO_EFFECT 0x0ULL 1641 #define ARM_TTE_TABLE_AP_USER_NA 0x1ULL 1642 #define ARM_TTE_TABLE_AP_RO 0x2ULL 1643 #define ARM_TTE_TABLE_AP_KERN_RO 0x3ULL 1644 #define ARM_TTE_TABLE_AP(x) ((x) << ARM_TTE_TABLE_APSHIFT) /* access protection */ 1645 1646 #define ARM_TTE_TABLE_NS 0x8000000000000020ULL /* value for a secure mapping */ 1647 #define ARM_TTE_TABLE_NS_MASK 0x8000000000000020ULL /* notSecure mapping mask */ 1648 1649 #define ARM_TTE_TABLE_XN 0x1000000000000000ULL /* value for no execute */ 1650 #define ARM_TTE_TABLE_XNMASK 0x1000000000000000ULL /* no execute mask */ 1651 1652 #define ARM_TTE_TABLE_PXN 0x0800000000000000ULL /* value for privilege no execute bit */ 1653 #define ARM_TTE_TABLE_PXNMASK 0x0800000000000000ULL /* privilege execute mask */ 1654 1655 #if __ARM_KERNEL_PROTECT__ 1656 #define ARM_TTE_BOOT_BLOCK_LOWER \ 1657 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 1658 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF | ARM_TTE_BLOCK_NG) 1659 #else /* __ARM_KERNEL_PROTECT__ */ 1660 #define ARM_TTE_BOOT_BLOCK_LOWER \ 1661 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 1662 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF) 1663 #endif /* __ARM_KERNEL_PROTECT__ */ 1664 #define ARM_TTE_BOOT_BLOCK_UPPER ARM_TTE_BLOCK_NX 1665 1666 #define ARM_TTE_BOOT_TABLE (ARM_TTE_TYPE_TABLE | ARM_TTE_VALID ) 1667 /* 1668 * L3 Translation table 1669 * 1670 * 4KB granule size: 1671 * Each translation table is 4KB 1672 * 512 64-bit entries of 4KB (2^12) of address space. 1673 * Covers 2MB (2^21) of address space. 1674 * 1675 * 16KB granule size: 1676 * Each translation table is 16KB 1677 * 2048 64-bit entries of 16KB (2^14) of address space. 1678 * Covers 32MB (2^25) of address space. 1679 */ 1680 1681 #ifdef __ARM_16K_PG__ 1682 #define ARM_PTE_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 1683 #define ARM_PTE_OFFMASK 0x0000000000003fffULL /* offset within pte area */ 1684 #define ARM_PTE_SHIFT 14 /* page descriptor shift */ 1685 #define ARM_PTE_MASK 0x0000ffffffffc000ULL /* mask for output address in PTE */ 1686 #else 1687 #define ARM_PTE_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 1688 #define ARM_PTE_OFFMASK 0x0000000000000fffULL /* offset within pte area */ 1689 #define ARM_PTE_SHIFT 12 /* page descriptor shift */ 1690 #define ARM_PTE_MASK 0x0000fffffffff000ULL /* mask for output address in PTE */ 1691 #endif 1692 1693 #define ARM_TTE_PA_MASK 0x0000fffffffff000ULL 1694 1695 /* 1696 * L3 Page table entries 1697 * 1698 * The following page table entry types are possible: 1699 * 1700 * fault page entry 1701 * 63 2 0 1702 * +------------------------------+--+ 1703 * | ignored |00| 1704 * +------------------------------+--+ 1705 * 1706 * 1707 * 63 59 58 55 54 53 52 51 50 47 48 12 11 10 9 8 7 6 5 4 2 1 0 1708 * +-----+------+--+---+----+---+--+----+----------------------+--+--+----+----+--+-------+-+-+ 1709 * | ign |sw use|XN|PXN|HINT|DBM|GP|zero| OutputAddress[47:12] |nG|AF| SH | AP |NS|AttrIdx|1|V| 1710 * +-----+------+--+---+----+---+--+----+----------------------+--+--+----+----+--+-------+-+-+ 1711 * 1712 * where: 1713 * nG: notGlobal bit 1714 * SH: Shareability field 1715 * AP: access protection 1716 * XN: eXecute Never bit 1717 * PXN: Privilege eXecute Never bit 1718 * NS: Non-Secure bit 1719 * HINT: 16 entry continuguous output hint 1720 * DBM: Dirty Bit Modifier 1721 * GP: Guraded Page 1722 * AttrIdx: Memory Attribute Index 1723 */ 1724 1725 #define PTE_SHIFT 3 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */ 1726 #ifdef __ARM_16K_PG__ 1727 #define PTE_PGENTRIES (16384 >> PTE_SHIFT) /* number of ptes per page */ 1728 #else 1729 #define PTE_PGENTRIES (4096 >> PTE_SHIFT) /* number of ptes per page */ 1730 #endif 1731 1732 #define ARM_PTE_EMPTY 0x0000000000000000ULL /* unassigned - invalid entry */ 1733 1734 /* markers for (invalid) PTE for a page sent to compressor */ 1735 #define ARM_PTE_COMPRESSED 0x8000000000000000ULL /* compressed... */ 1736 #define ARM_PTE_COMPRESSED_ALT 0x4000000000000000ULL /* ... and was "alt_acct" */ 1737 #define ARM_PTE_COMPRESSED_MASK 0xC000000000000000ULL 1738 1739 #define ARM_PTE_TYPE_VALID 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */ 1740 #define ARM_PTE_TYPE_FAULT 0x0000000000000000ULL /* invalid L3 entry */ 1741 #define ARM_PTE_TYPE_MASK 0x0000000000000003ULL /* mask to get pte type */ 1742 1743 /* This mask works for both 16K and 4K pages because bits 12-13 will be zero in 16K pages */ 1744 #define ARM_PTE_PAGE_MASK 0x0000FFFFFFFFF000ULL /* output address mask for page */ 1745 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for the output address in the entry */ 1746 1747 #define ARM_PTE_AP(x) ((x) << 6) /* access protections */ 1748 #define ARM_PTE_APMASK (0x3ULL << 6) /* mask access protections */ 1749 #define ARM_PTE_EXTRACT_AP(x) (((x) >> 6) & 0x3ULL) /* extract access protections from PTE */ 1750 1751 #define ARM_PTE_ATTRINDX(x) (uint64_t)((x) << 2) /* memory attributes index */ 1752 #define ARM_PTE_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */ 1753 #define ARM_PTE_EXTRACT_ATTRINDX(x) (((x) >> 2) & 0x7ULL) /* extract memory attributes index */ 1754 1755 #define ARM_PTE_SH(x) ((x) << 8) /* access shared */ 1756 #define ARM_PTE_SHMASK (0x3ULL << 8) /* mask access shared */ 1757 1758 #define ARM_PTE_AF 0x0000000000000400ULL /* value for access */ 1759 #define ARM_PTE_AFMASK 0x0000000000000400ULL /* access mask */ 1760 1761 #define ARM_PTE_NG 0x0000000000000800ULL /* value for a global mapping */ 1762 #define ARM_PTE_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 1763 1764 #define ARM_PTE_NS 0x0000000000000020ULL /* value for a secure mapping */ 1765 #define ARM_PTE_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 1766 1767 #define ARM_PTE_HINT 0x0010000000000000ULL /* value for contiguous entries hint */ 1768 #define ARM_PTE_HINT_MASK 0x0010000000000000ULL /* mask for contiguous entries hint */ 1769 1770 #define ARM_PTE_GP 0x0004000000000000ULL /* value marking a guarded page */ 1771 #define ARM_PTE_GP_MASK 0x0004000000000000ULL /* mask for a guarded page mark */ 1772 1773 #if __ARM_16K_PG__ 1774 #define ARM_PTE_HINT_ENTRIES 128ULL /* number of entries the hint covers */ 1775 #define ARM_PTE_HINT_ENTRIES_SHIFT 7ULL /* shift to construct the number of entries */ 1776 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFE00000ULL /* mask to extract the starting hint address */ 1777 #define ARM_PTE_HINT_ADDR_SHIFT 21 /* shift for the hint address */ 1778 #define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFE00000ULL /* mask to extract the starting hint address */ 1779 #else 1780 #define ARM_PTE_HINT_ENTRIES 16ULL /* number of entries the hint covers */ 1781 #define ARM_PTE_HINT_ENTRIES_SHIFT 4ULL /* shift to construct the number of entries */ 1782 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFFF0000ULL /* mask to extract the starting hint address */ 1783 #define ARM_PTE_HINT_ADDR_SHIFT 16 /* shift for the hint address */ 1784 #define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFFF0000ULL /* mask to extract the starting hint address */ 1785 #endif 1786 1787 #define ARM_PTE_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 1788 #define ARM_PTE_PXN ARM_PTE_PNX 1789 #define ARM_PTE_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 1790 1791 #define ARM_PTE_NX 0x0040000000000000ULL /* value for no execute bit */ 1792 #define ARM_PTE_XN ARM_PTE_NX 1793 #define ARM_PTE_NXMASK 0x0040000000000000ULL /* no execute mask */ 1794 1795 #define ARM_PTE_XMASK (ARM_PTE_PNXMASK | ARM_PTE_NXMASK) 1796 1797 #define ARM_PTE_GUARDED 0x0004000000000000ULL /* value for "guarded"/BTI enforcing code page */ 1798 #define ARM_PTE_GUARDED_MASK (PTE_GUARDED) 1799 1800 #define ARM_PTE_WIRED 0x0400000000000000ULL /* value for software wired bit */ 1801 #define ARM_PTE_WIRED_MASK 0x0400000000000000ULL /* software wired mask */ 1802 1803 #define ARM_PTE_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 1804 #define ARM_PTE_WRITABLE ARM_PTE_WRITEABLE 1805 #define ARM_PTE_WRITEABLE_MASK 0x0800000000000000ULL /* software writeable mask */ 1806 1807 #define ARM_PTE_SW_RESERVED_MASK (ARM_PTE_WIRED_MASK | ARM_PTE_WRITEABLE_MASK) 1808 1809 #define ARM_PTE_BOOT_PAGE_BASE \ 1810 (ARM_PTE_TYPE_VALID | ARM_PTE_SH(SH_OUTER_MEMORY) | \ 1811 ARM_PTE_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_PTE_AF) 1812 1813 #if __ARM_KERNEL_PROTECT__ 1814 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE | ARM_PTE_NG) 1815 #else /* __ARM_KERNEL_PROTECT__ */ 1816 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE) 1817 #endif /* __ARM_KERNEL_PROTECT__ */ 1818 1819 /* 1820 * TLBI appers to only deal in 4KB page addresses, so give 1821 * it an explicit shift of 12. 1822 */ 1823 #define TLBI_ADDR_SHIFT (0) 1824 #define TLBI_ADDR_SIZE (44) 1825 #define TLBI_ADDR_MASK ((1ULL << TLBI_ADDR_SIZE) - 1) 1826 #define TLBI_IPA_SHIFT (0) 1827 #define TLBI_IPA_SIZE (36) 1828 #define TLBI_IPA_MASK ((1ULL << TLBI_IPA_SIZE) - 1) 1829 #define TLBI_ASID_SHIFT (48) 1830 #define TLBI_ASID_SIZE (16) 1831 #define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1)) 1832 1833 #define RTLBI_ADDR_SIZE (37) 1834 #define RTLBI_ADDR_MASK ((1ULL << RTLBI_ADDR_SIZE) - 1) 1835 #define RTLBI_ADDR_SHIFT ARM_TT_L3_SHIFT 1836 #define RTLBI_TG(_page_shift_) ((uint64_t)((((_page_shift_) - 12) >> 1) + 1) << 46) 1837 #define RTLBI_SCALE_SHIFT (44) 1838 #define RTLBI_NUM_SHIFT (39) 1839 1840 /* 1841 * RCTX instruction operand fields. 1842 */ 1843 #define RCTX_EL_SHIFT (24) 1844 #define RCTX_EL_SIZE (2) 1845 #define RCTX_EL_MASK (((1ULL << RCTX_EL_SIZE) - 1) << RCTX_EL_SHIFT) 1846 #define RCTX_EL(x) ((x << RCTX_EL_SHIFT) & RCTX_EL_MASK) 1847 #define RCTX_ASID_SHIFT (0) 1848 #define RCTX_ASID_SIZE (16) 1849 #define RCTX_ASID_MASK (((1ULL << RCTX_ASID_SIZE) - 1) << RCTX_ASID_SHIFT) 1850 #define RCTX_ASID(x) ((x << RCTX_ASID_SHIFT) & RCTX_ASID_MASK) 1851 1852 /* 1853 * Exception Syndrome Register 1854 * 1855 * 63 56 55 32 31 26 25 24 0 1856 * +------+------+------+--+------------------+ 1857 * | RES0 | ISS2 | EC |IL| ISS | 1858 * +------+------+------+--+------------------+ 1859 * 1860 * RES0 - Reserved bits. 1861 * ISS2 - Instruction Specific Syndrome 2. 1862 * EC - Exception Class 1863 * IL - Instruction Length 1864 * ISS - Instruction Specific Syndrome 1865 * 1866 * Note: The ISS can have many forms. These are defined separately below. 1867 */ 1868 1869 #define ESR_EC_SHIFT 26 1870 #define ESR_EC_WIDTH 6 1871 #define ESR_EC_MASK (0x3FULL << ESR_EC_SHIFT) 1872 #define ESR_EC(x) ((x & ESR_EC_MASK) >> ESR_EC_SHIFT) 1873 1874 #define ESR_IL_SHIFT 25 1875 #define ESR_IL (1 << ESR_IL_SHIFT) 1876 1877 #define ESR_INSTR_IS_2BYTES(x) (!(x & ESR_IL)) 1878 1879 #define ESR_ISS_MASK 0x01FFFFFF 1880 #define ESR_ISS(x) (x & ESR_ISS_MASK) 1881 1882 1883 #ifdef __ASSEMBLER__ 1884 /* Define only the classes we need to test in the exception vectors. */ 1885 #define ESR_EC_UNCATEGORIZED 0x00 1886 #define ESR_EC_BTI_FAIL 0x0D 1887 #define ESR_EC_SVC_64 0x15 1888 #define ESR_EC_HVC_64 0x16 1889 #define ESR_EC_PAC_FAIL 0x1C 1890 #define ESR_EC_IABORT_EL1 0x21 1891 #define ESR_EC_DABORT_EL1 0x25 1892 #define ESR_EC_SP_ALIGN 0x26 1893 #define ESR_EC_BRK_AARCH64 0x3C 1894 #else 1895 typedef enum { 1896 ESR_EC_UNCATEGORIZED = 0x00, 1897 ESR_EC_WFI_WFE = 0x01, 1898 ESR_EC_MCR_MRC_CP15_TRAP = 0x03, 1899 ESR_EC_MCRR_MRRC_CP15_TRAP = 0x04, 1900 ESR_EC_MCR_MRC_CP14_TRAP = 0x05, 1901 ESR_EC_LDC_STC_CP14_TRAP = 0x06, 1902 ESR_EC_TRAP_SIMD_FP = 0x07, 1903 ESR_EC_PTRAUTH_INSTR_TRAP = 0x09, 1904 ESR_EC_MCRR_MRRC_CP14_TRAP = 0x0c, 1905 ESR_EC_BTI_FAIL = 0x0d, 1906 ESR_EC_ILLEGAL_INSTR_SET = 0x0e, 1907 ESR_EC_SVC_32 = 0x11, 1908 ESR_EC_HVC_32 = 0x12, 1909 ESR_EC_SVC_64 = 0x15, 1910 ESR_EC_HVC_64 = 0x16, 1911 ESR_EC_MSR_TRAP = 0x18, 1912 #if __has_feature(ptrauth_calls) 1913 ESR_EC_PAC_FAIL = 0x1C, 1914 #endif /* __has_feature(ptrauth_calls) */ 1915 #if HAS_ARM_FEAT_SME 1916 ESR_EC_SME = 0x1D, 1917 #endif 1918 ESR_EC_IABORT_EL0 = 0x20, 1919 ESR_EC_IABORT_EL1 = 0x21, 1920 ESR_EC_PC_ALIGN = 0x22, 1921 ESR_EC_DABORT_EL0 = 0x24, 1922 ESR_EC_DABORT_EL1 = 0x25, 1923 ESR_EC_SP_ALIGN = 0x26, 1924 ESR_EC_FLOATING_POINT_32 = 0x28, 1925 ESR_EC_FLOATING_POINT_64 = 0x2C, 1926 ESR_EC_SERROR_INTERRUPT = 0x2F, 1927 ESR_EC_BKPT_REG_MATCH_EL0 = 0x30, // Breakpoint Debug event taken to the EL from a lower EL. 1928 ESR_EC_BKPT_REG_MATCH_EL1 = 0x31, // Breakpoint Debug event taken to the EL from the EL. 1929 ESR_EC_SW_STEP_DEBUG_EL0 = 0x32, // Software Step Debug event taken to the EL from a lower EL. 1930 ESR_EC_SW_STEP_DEBUG_EL1 = 0x33, // Software Step Debug event taken to the EL from the EL. 1931 ESR_EC_WATCHPT_MATCH_EL0 = 0x34, // Watchpoint Debug event taken to the EL from a lower EL. 1932 ESR_EC_WATCHPT_MATCH_EL1 = 0x35, // Watchpoint Debug event taken to the EL from the EL. 1933 ESR_EC_BKPT_AARCH32 = 0x38, 1934 ESR_EC_BRK_AARCH64 = 0x3C, 1935 } esr_exception_class_t; 1936 1937 typedef enum { 1938 FSC_TRANSLATION_FAULT_L0 = 0x04, 1939 FSC_TRANSLATION_FAULT_L1 = 0x05, 1940 FSC_TRANSLATION_FAULT_L2 = 0x06, 1941 FSC_TRANSLATION_FAULT_L3 = 0x07, 1942 FSC_ACCESS_FLAG_FAULT_L1 = 0x09, 1943 FSC_ACCESS_FLAG_FAULT_L2 = 0x0A, 1944 FSC_ACCESS_FLAG_FAULT_L3 = 0x0B, 1945 FSC_PERMISSION_FAULT_L1 = 0x0D, 1946 FSC_PERMISSION_FAULT_L2 = 0x0E, 1947 FSC_PERMISSION_FAULT_L3 = 0x0F, 1948 FSC_SYNC_EXT_ABORT = 0x10, 1949 FSC_SYNC_EXT_ABORT_TT_L1 = 0x15, 1950 FSC_SYNC_EXT_ABORT_TT_L2 = 0x16, 1951 FSC_SYNC_EXT_ABORT_TT_L3 = 0x17, 1952 FSC_SYNC_PARITY = 0x18, 1953 FSC_ASYNC_PARITY = 0x19, 1954 FSC_SYNC_PARITY_TT_L1 = 0x1D, 1955 FSC_SYNC_PARITY_TT_L2 = 0x1E, 1956 FSC_SYNC_PARITY_TT_L3 = 0x1F, 1957 FSC_ALIGNMENT_FAULT = 0x21, 1958 FSC_DEBUG_FAULT = 0x22, 1959 } fault_status_t; 1960 #endif /* ASSEMBLER */ 1961 1962 /* 1963 * SVC event 1964 * 24 16 15 0 1965 * +---------+-----+ 1966 * |000000000| IMM | 1967 * +---------+-----+ 1968 * 1969 * where: 1970 * IMM: Immediate value 1971 */ 1972 1973 #define ISS_SVC_IMM_MASK 0xffff 1974 #define ISS_SVC_IMM(x) ((x) & ISS_SVC_IMM_MASK) 1975 1976 /* 1977 * HVC event 1978 * 24 16 15 0 1979 * +---------+-----+ 1980 * |000000000| IMM | 1981 * +---------+-----+ 1982 * 1983 * where: 1984 * IMM: Immediate value 1985 */ 1986 1987 #define ISS_HVC_IMM_MASK 0xffff 1988 #define ISS_HVC_IMM(x) ((x) & ISS_HVC_IMM_MASK) 1989 1990 1991 /* 1992 * Software step debug event ISS (EL1) 1993 * 24 23 6 5 0 1994 * +---+-----------------+--+------+ 1995 * |ISV|00000000000000000|EX| IFSC | 1996 * +---+-----------------+--+------+ 1997 * 1998 * where: 1999 * ISV: Instruction syndrome valid 2000 * EX: Exclusive access 2001 * IFSC: Instruction Fault Status Code 2002 */ 2003 2004 #define ISS_SSDE_ISV_SHIFT 24 2005 #define ISS_SSDE_ISV (0x1 << ISS_SSDE_ISV_SHIFT) 2006 2007 #define ISS_SSDE_EX_SHIFT 6 2008 #define ISS_SSDE_EX (0x1 << ISS_SSDE_EX_SHIFT) 2009 2010 #define ISS_SSDE_FSC_MASK 0x3F 2011 #define ISS_SSDE_FSC(x) (x & ISS_SSDE_FSC_MASK) 2012 2013 /* 2014 * Instruction Abort ISS (EL1) 2015 * 24 10 9 5 0 2016 * +--------------+---+--+---+------+ 2017 * |00000000000000|FnV|EA|000| IFSC | 2018 * +--------------+---+--+---+------+ 2019 * 2020 * where: 2021 * FnV: FAR not Valid 2022 * EA: External Abort type 2023 * IFSC: Instruction Fault Status Code 2024 */ 2025 2026 #define ISS_IA_FNV_SHIFT 10 2027 #define ISS_IA_FNV (0x1 << ISS_IA_FNV_SHIFT) 2028 2029 #define ISS_IA_EA_SHIFT 9 2030 #define ISS_IA_EA (0x1 << ISS_IA_EA_SHIFT) 2031 2032 #define ISS_IA_FSC_MASK 0x3F 2033 #define ISS_IA_FSC(x) (x & ISS_IA_FSC_MASK) 2034 2035 2036 /* 2037 * Data Abort ISS (EL1) 2038 * 2039 * 24 10 9 8 7 6 5 0 2040 * +--------------+---+--+--+-----+---+----+ 2041 * |00000000000000|FnV|EA|CM|S1PTW|WnR|DFSC| 2042 * +--------------+---+--+--+-----+---+----+ 2043 * 2044 * where: 2045 * FnV: FAR not Valid 2046 * EA: External Abort type 2047 * CM: Cache Maintenance operation 2048 * WnR: Write not Read 2049 * S1PTW: Stage 2 exception on Stage 1 page table walk 2050 * DFSC: Data Fault Status Code 2051 */ 2052 #define ISS_DA_FNV_SHIFT 10 2053 #define ISS_DA_FNV (0x1 << ISS_DA_FNV_SHIFT) 2054 2055 #define ISS_DA_EA_SHIFT 9 2056 #define ISS_DA_EA (0x1 << ISS_DA_EA_SHIFT) 2057 2058 #define ISS_DA_CM_SHIFT 8 2059 #define ISS_DA_CM (0x1 << ISS_DA_CM_SHIFT) 2060 2061 #define ISS_DA_WNR_SHIFT 6 2062 #define ISS_DA_WNR (0x1 << ISS_DA_WNR_SHIFT) 2063 2064 #define ISS_DA_S1PTW_SHIFT 7 2065 #define ISS_DA_S1PTW (0x1 << ISS_DA_S1PTW_SHIFT) 2066 2067 #define ISS_DA_FSC_MASK 0x3F 2068 #define ISS_DA_FSC(x) (x & ISS_DA_FSC_MASK) 2069 2070 /* 2071 * Floating Point Exception ISS (EL1) 2072 * 2073 * 24 23 22 8 7 4 3 2 1 0 2074 * +-+---+---------------+---+--+---+---+---+---+---+ 2075 * |0|TFV|000000000000000|IDF|00|IXF|UFF|OFF|DZF|IOF| 2076 * +-+---+---------------+---+--+---+---+---+---+---+ 2077 * 2078 * where: 2079 * TFV: Trapped Fault Valid 2080 * IDF: Input Denormal Exception 2081 * IXF: Input Inexact Exception 2082 * UFF: Underflow Exception 2083 * OFF: Overflow Exception 2084 * DZF: Divide by Zero Exception 2085 * IOF: Invalid Operation Exception 2086 */ 2087 #define ISS_FP_TFV_SHIFT 23 2088 #define ISS_FP_TFV (0x1 << ISS_FP_TFV_SHIFT) 2089 2090 #define ISS_FP_IDF_SHIFT 7 2091 #define ISS_FP_IDF (0x1 << ISS_FP_IDF_SHIFT) 2092 2093 #define ISS_FP_IXF_SHIFT 4 2094 #define ISS_FP_IXF (0x1 << ISS_FP_IXF_SHIFT) 2095 2096 #define ISS_FP_UFF_SHIFT 3 2097 #define ISS_FP_UFF (0x1 << ISS_FP_UFF_SHIFT) 2098 2099 #define ISS_FP_OFF_SHIFT 2 2100 #define ISS_FP_OFF (0x1 << ISS_FP_OFF_SHIFT) 2101 2102 #define ISS_FP_DZF_SHIFT 1 2103 #define ISS_FP_DZF (0x1 << ISS_FP_DZF_SHIFT) 2104 2105 #define ISS_FP_IOF_SHIFT 0 2106 #define ISS_FP_IOF (0x1 << ISS_FP_IOF_SHIFT) 2107 2108 /* 2109 * Breakpoint Exception ISS (EL1) 2110 * 24 16 0 2111 * +---------+---------+ 2112 * |000000000| Comment | 2113 * +---------+---------+ 2114 * 2115 * where: 2116 * Comment: Instruction Comment Field Value 2117 */ 2118 #define ISS_BRK_COMMENT_MASK 0xFFFF 2119 #define ISS_BRK_COMMENT(x) (x & ISS_BRK_COMMENT_MASK) 2120 2121 2122 2123 /* 2124 * SError Interrupt, IDS=1 2125 * 24 23 0 2126 * +---+------------------------+ 2127 * |IDS| IMPLEMENTATION DEFINED | 2128 * +---+------------------------+ 2129 * 2130 * where: 2131 * IDS: Implementation-defined syndrome (1) 2132 */ 2133 2134 #define ISS_SEI_IDS_SHIFT 24 2135 #define ISS_SEI_IDS (0x1 << ISS_SEI_IDS_SHIFT) 2136 2137 2138 #if HAS_UCNORMAL_MEM 2139 #define ISS_UC 0x11 2140 #endif /* HAS_UCNORMAL_MEM */ 2141 2142 2143 2144 #if HAS_ARM_FEAT_SME 2145 2146 /* 2147 * SME ISS (EL1) 2148 * 2149 * 24 3 2 0 2150 * +----------------------+----+ 2151 * |0000000000000000000000|SMTC| 2152 * +----------------------+----+ 2153 * 2154 * where: 2155 * SMTC: SME Trap Code 2156 */ 2157 #define ISS_SME_SMTC_CAPCR 0x0 2158 #define ISS_SME_SMTC_MASK 0x7 2159 #define ISS_SME_SMTC(x) ((x) & ISS_SME_SMTC_MASK) 2160 2161 2162 /* 2163 * SME Control Register (EL1) 2164 * 31 30 29 4 3 0 2165 * +----+----+--------------------------+---+ 2166 * |FA64|EZT0|00000000000000000000000000|LEN| 2167 * +----+----+--------------------------+---+ 2168 * 2169 * where: 2170 * FA64: Enable FEAT_SME_FA64 2171 * EZT0: Enable ZT0 2172 * LEN: Effective SVL = (LEN + 1) * 128 2173 */ 2174 2175 #define SMCR_EL1_LEN_MASK 0xf 2176 #if HAS_ARM_FEAT_SME2 2177 #define SMCR_EL1_EZT0 (1ULL << 30) 2178 #endif 2179 #define SMCR_EL1_LEN(x) ((x) & SMCR_EL1_LEN_MASK) 2180 2181 #define SMPRI_EL1_PRIORITY_MASK 0xf 2182 #define SMPRI_EL1_PRIORITY(x) ((x) & SMPRI_EL1_PRIORITY_MASK) 2183 2184 /* 2185 * Streaming Vector Control Register (SVCR) 2186 */ 2187 #define SVCR_ZA_SHIFT (1) 2188 #define SVCR_ZA (1ULL << SVCR_ZA_SHIFT) 2189 #define SVCR_SM_SHIFT (0) 2190 #define SVCR_SM (1ULL << SVCR_SM_SHIFT) 2191 2192 #endif /* HAS_ARM_FEAT_SME */ 2193 2194 /* 2195 * Branch Target Indication Exception ISS 2196 * 24 3 2 0 2197 * +----+-----+ 2198 * |res0|BTYPE| 2199 * +----+-----+ 2200 */ 2201 #define ISS_BTI_BTYPE_SHIFT (0) 2202 #define ISS_BTI_BTYPE_MASK (0x3 << ISS_BTI_BTYPE_SHIFT) 2203 2204 /* 2205 * Physical Address Register (EL1) 2206 */ 2207 #define PAR_F_SHIFT 0 2208 #define PAR_F (0x1 << PAR_F_SHIFT) 2209 2210 #define PLATFORM_SYSCALL_TRAP_NO 0x80000000 2211 2212 #define ARM64_SYSCALL_CODE_REG_NUM (16) 2213 2214 #define ARM64_CLINE_SHIFT 6 2215 2216 #if defined(APPLE_ARM64_ARCH_FAMILY) 2217 #define L2CERRSTS_DATSBEESV (1ULL << 2) /* L2C data single bit ECC error */ 2218 #define L2CERRSTS_DATDBEESV (1ULL << 4) /* L2C data double bit ECC error */ 2219 #endif 2220 2221 /* 2222 * Timer definitions. 2223 */ 2224 #define CNTKCTL_EL1_PL0PTEN (0x1 << 9) /* 1: EL0 access to physical timer regs permitted */ 2225 #define CNTKCTL_EL1_PL0VTEN (0x1 << 8) /* 1: EL0 access to virtual timer regs permitted */ 2226 #define CNTKCTL_EL1_EVENTI_MASK (0x000000f0) /* Mask for bits describing which bit to use for triggering event stream */ 2227 #define CNTKCTL_EL1_EVENTI_SHIFT (0x4) /* Shift for same */ 2228 #define CNTKCTL_EL1_EVENTDIR (0x1 << 3) /* 1: one-to-zero transition of specified bit causes event */ 2229 #define CNTKCTL_EL1_EVNTEN (0x1 << 2) /* 1: enable event stream */ 2230 #define CNTKCTL_EL1_PL0VCTEN (0x1 << 1) /* 1: EL0 access to virtual timebase + frequency reg enabled */ 2231 #define CNTKCTL_EL1_PL0PCTEN (0x1 << 0) /* 1: EL0 access to physical timebase + frequency reg enabled */ 2232 2233 #define CNTV_CTL_EL0_ISTATUS (0x1 << 2) /* (read only): whether interrupt asserted */ 2234 #define CNTV_CTL_EL0_IMASKED (0x1 << 1) /* 1: interrupt masked */ 2235 #define CNTV_CTL_EL0_ENABLE (0x1 << 0) /* 1: virtual timer enabled */ 2236 2237 #define CNTP_CTL_EL0_ISTATUS CNTV_CTL_EL0_ISTATUS 2238 #define CNTP_CTL_EL0_IMASKED CNTV_CTL_EL0_IMASKED 2239 #define CNTP_CTL_EL0_ENABLE CNTV_CTL_EL0_ENABLE 2240 2241 #define MIDR_EL1_REV_SHIFT 0 2242 #define MIDR_EL1_REV_MASK (0xf << MIDR_EL1_REV_SHIFT) 2243 #define MIDR_EL1_PNUM_SHIFT 4 2244 #define MIDR_EL1_PNUM_MASK (0xfff << MIDR_EL1_PNUM_SHIFT) 2245 #define MIDR_EL1_ARCH_SHIFT 16 2246 #define MIDR_EL1_ARCH_MASK (0xf << MIDR_EL1_ARCH_SHIFT) 2247 #define MIDR_EL1_VAR_SHIFT 20 2248 #define MIDR_EL1_VAR_MASK (0xf << MIDR_EL1_VAR_SHIFT) 2249 #define MIDR_EL1_IMP_SHIFT 24 2250 #define MIDR_EL1_IMP_MASK (0xff << MIDR_EL1_IMP_SHIFT) 2251 2252 #define MIDR_FIJI (0x002 << MIDR_EL1_PNUM_SHIFT) 2253 #define MIDR_CAPRI (0x003 << MIDR_EL1_PNUM_SHIFT) 2254 #define MIDR_MAUI (0x004 << MIDR_EL1_PNUM_SHIFT) 2255 #define MIDR_ELBA (0x005 << MIDR_EL1_PNUM_SHIFT) 2256 #define MIDR_CAYMAN (0x006 << MIDR_EL1_PNUM_SHIFT) 2257 #define MIDR_MYST (0x007 << MIDR_EL1_PNUM_SHIFT) 2258 #define MIDR_SKYE_MONSOON (0x008 << MIDR_EL1_PNUM_SHIFT) 2259 #define MIDR_SKYE_MISTRAL (0x009 << MIDR_EL1_PNUM_SHIFT) 2260 #define MIDR_CYPRUS_VORTEX (0x00B << MIDR_EL1_PNUM_SHIFT) 2261 #define MIDR_CYPRUS_TEMPEST (0x00C << MIDR_EL1_PNUM_SHIFT) 2262 #define MIDR_M9 (0x00F << MIDR_EL1_PNUM_SHIFT) 2263 #define MIDR_ARUBA_VORTEX (0x010 << MIDR_EL1_PNUM_SHIFT) 2264 #define MIDR_ARUBA_TEMPEST (0x011 << MIDR_EL1_PNUM_SHIFT) 2265 2266 #ifdef APPLELIGHTNING 2267 #define MIDR_CEBU_LIGHTNING (0x012 << MIDR_EL1_PNUM_SHIFT) 2268 #define MIDR_CEBU_THUNDER (0x013 << MIDR_EL1_PNUM_SHIFT) 2269 #define MIDR_TURKS (0x026 << MIDR_EL1_PNUM_SHIFT) 2270 #endif 2271 2272 #ifdef APPLEFIRESTORM 2273 #define MIDR_SICILY_ICESTORM (0x020 << MIDR_EL1_PNUM_SHIFT) 2274 #define MIDR_SICILY_FIRESTORM (0x021 << MIDR_EL1_PNUM_SHIFT) 2275 #define MIDR_TONGA_ICESTORM (0x022 << MIDR_EL1_PNUM_SHIFT) 2276 #define MIDR_TONGA_FIRESTORM (0x023 << MIDR_EL1_PNUM_SHIFT) 2277 #define MIDR_JADE_CHOP_ICESTORM (0x024 << MIDR_EL1_PNUM_SHIFT) 2278 #define MIDR_JADE_CHOP_FIRESTORM (0x025 << MIDR_EL1_PNUM_SHIFT) 2279 #define MIDR_JADE_DIE_ICESTORM (0x028 << MIDR_EL1_PNUM_SHIFT) 2280 #define MIDR_JADE_DIE_FIRESTORM (0x029 << MIDR_EL1_PNUM_SHIFT) 2281 #endif 2282 2283 #ifdef APPLEAVALANCHE 2284 #define MIDR_ELLIS_BLIZZARD (0x030 << MIDR_EL1_PNUM_SHIFT) 2285 #define MIDR_ELLIS_AVALANCHE (0x031 << MIDR_EL1_PNUM_SHIFT) 2286 #endif 2287 #define MIDR_STATEN_BLIZZARD (0x032 << MIDR_EL1_PNUM_SHIFT) 2288 #define MIDR_STATEN_AVALANCHE (0x033 << MIDR_EL1_PNUM_SHIFT) 2289 #define MIDR_RHODES_CHOP_BLIZZARD (0x034 << MIDR_EL1_PNUM_SHIFT) 2290 #define MIDR_RHODES_CHOP_AVALANCHE (0x035 << MIDR_EL1_PNUM_SHIFT) 2291 #define MIDR_RHODES_DIE_BLIZZARD (0x038 << MIDR_EL1_PNUM_SHIFT) 2292 #define MIDR_RHODES_DIE_AVALANCHE (0x039 << MIDR_EL1_PNUM_SHIFT) 2293 2294 #if defined(APPLEEVEREST) 2295 #define MIDR_CRETE_SAWTOOTH (0x040 << MIDR_EL1_PNUM_SHIFT) 2296 #define MIDR_CRETE_EVEREST (0x041 << MIDR_EL1_PNUM_SHIFT) 2297 #define MIDR_IBIZA_ACCE (0x042 << MIDR_EL1_PNUM_SHIFT) 2298 #define MIDR_IBIZA_ACCP (0x043 << MIDR_EL1_PNUM_SHIFT) 2299 #define MIDR_LOBOS_ACCE (0x044 << MIDR_EL1_PNUM_SHIFT) 2300 #define MIDR_LOBOS_ACCP (0x045 << MIDR_EL1_PNUM_SHIFT) 2301 #define MIDR_CAICOS_ACCE (0x046 << MIDR_EL1_PNUM_SHIFT) 2302 #define MIDR_PALMA_ACCE (0x048 << MIDR_EL1_PNUM_SHIFT) 2303 #define MIDR_PALMA_ACCP (0x049 << MIDR_EL1_PNUM_SHIFT) 2304 #define MIDR_COLL_ACCE (0x050 << MIDR_EL1_PNUM_SHIFT) 2305 #define MIDR_COLL_ACCP (0x051 << MIDR_EL1_PNUM_SHIFT) 2306 #endif /* defined(APPLEEVEREST) */ 2307 2308 /*Donan*/ 2309 #define MIDR_DONAN_ACCE (0x052 << MIDR_EL1_PNUM_SHIFT) 2310 #define MIDR_DONAN_ACCP (0x053 << MIDR_EL1_PNUM_SHIFT) 2311 /*Brava*/ 2312 #define MIDR_BRAVA_ACCE (0x054 << MIDR_EL1_PNUM_SHIFT) 2313 #define MIDR_BRAVA_ACCP (0x055 << MIDR_EL1_PNUM_SHIFT) 2314 2315 2316 /* 2317 * Apple-ISA-Extensions ID Register. 2318 */ 2319 #define AIDR_MUL53 (1ULL << 0) 2320 #define AIDR_WKDM (1ULL << 1) 2321 #define AIDR_ARCHRETENTION (1ULL << 2) 2322 2323 2324 2325 2326 /* 2327 * CoreSight debug registers 2328 */ 2329 #define CORESIGHT_ED 0 2330 #define CORESIGHT_CTI 1 2331 #define CORESIGHT_PMU 2 2332 #define CORESIGHT_UTT 3 /* Not truly a coresight thing, but at a fixed convenient location right after the coresight region */ 2333 2334 #define CORESIGHT_OFFSET(x) ((x) * 0x10000) 2335 #define CORESIGHT_REGIONS 4 2336 #define CORESIGHT_SIZE 0x1000 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 /* 2348 * ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 2349 * 2350 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2351 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2352 * | rndr | tlb | ts | fhm | dp | sm4 | sm3 | sha3 | rdm | res0 | atomic | crc32 | sha2 | sha1 | aes | res0 | 2353 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2354 */ 2355 2356 #define ID_AA64ISAR0_EL1_TS_OFFSET 52 2357 #define ID_AA64ISAR0_EL1_TS_MASK (0xfull << ID_AA64ISAR0_EL1_TS_OFFSET) 2358 #define ID_AA64ISAR0_EL1_TS_FLAGM_EN (1ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2359 #define ID_AA64ISAR0_EL1_TS_FLAGM2_EN (2ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2360 2361 #define ID_AA64ISAR0_EL1_FHM_OFFSET 48 2362 #define ID_AA64ISAR0_EL1_FHM_MASK (0xfull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2363 #define ID_AA64ISAR0_EL1_FHM_8_2 (1ull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2364 2365 #define ID_AA64ISAR0_EL1_DP_OFFSET 44 2366 #define ID_AA64ISAR0_EL1_DP_MASK (0xfull << ID_AA64ISAR0_EL1_DP_OFFSET) 2367 #define ID_AA64ISAR0_EL1_DP_EN (1ull << ID_AA64ISAR0_EL1_DP_OFFSET) 2368 2369 #define ID_AA64ISAR0_EL1_SHA3_OFFSET 32 2370 #define ID_AA64ISAR0_EL1_SHA3_MASK (0xfull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2371 #define ID_AA64ISAR0_EL1_SHA3_EN (1ull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2372 2373 #define ID_AA64ISAR0_EL1_RDM_OFFSET 28 2374 #define ID_AA64ISAR0_EL1_RDM_MASK (0xfull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2375 #define ID_AA64ISAR0_EL1_RDM_EN (1ull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2376 2377 #define ID_AA64ISAR0_EL1_ATOMIC_OFFSET 20 2378 #define ID_AA64ISAR0_EL1_ATOMIC_MASK (0xfull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2379 #define ID_AA64ISAR0_EL1_ATOMIC_8_1 (2ull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2380 2381 #define ID_AA64ISAR0_EL1_CRC32_OFFSET 16 2382 #define ID_AA64ISAR0_EL1_CRC32_MASK (0xfull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2383 #define ID_AA64ISAR0_EL1_CRC32_EN (1ull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2384 2385 #define ID_AA64ISAR0_EL1_SHA2_OFFSET 12 2386 #define ID_AA64ISAR0_EL1_SHA2_MASK (0xfull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2387 #define ID_AA64ISAR0_EL1_SHA2_EN (1ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2388 #define ID_AA64ISAR0_EL1_SHA2_512_EN (2ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2389 2390 #define ID_AA64ISAR0_EL1_SHA1_OFFSET 8 2391 #define ID_AA64ISAR0_EL1_SHA1_MASK (0xfull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2392 #define ID_AA64ISAR0_EL1_SHA1_EN (1ull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2393 2394 #define ID_AA64ISAR0_EL1_AES_OFFSET 4 2395 #define ID_AA64ISAR0_EL1_AES_MASK (0xfull << ID_AA64ISAR0_EL1_AES_OFFSET) 2396 #define ID_AA64ISAR0_EL1_AES_EN (1ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2397 #define ID_AA64ISAR0_EL1_AES_PMULL_EN (2ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2398 2399 /* 2400 * ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 1 2401 * 2402 * 63 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2403 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2404 * | res0 | i8mm | dgh | bf16 | specres | sb | frintts | gpi | gpa | lrcpc | fcma | jscvt | api | apa | dpb | 2405 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2406 */ 2407 2408 #define ID_AA64ISAR1_EL1_I8MM_OFFSET 52 2409 #define ID_AA64ISAR1_EL1_I8MM_MASK (0xfull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2410 #define ID_AA64ISAR1_EL1_I8MM_EN (1ull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2411 2412 #define ID_AA64ISAR1_EL1_DGH_OFFSET 48 2413 #define ID_AA64ISAR1_EL1_DGH_MASK (0xfull << ID_AA64ISAR1_EL1_DGH_OFFSET) 2414 2415 #define ID_AA64ISAR1_EL1_BF16_OFFSET 44 2416 #define ID_AA64ISAR1_EL1_BF16_MASK (0xfull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2417 #define ID_AA64ISAR1_EL1_BF16_EN (1ull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2418 #define ID_AA64ISAR1_EL1_EBF16_EN (2ull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2419 2420 #define ID_AA64ISAR1_EL1_SPECRES_OFFSET 40 2421 #define ID_AA64ISAR1_EL1_SPECRES_MASK (0xfull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2422 #define ID_AA64ISAR1_EL1_SPECRES_EN (1ull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2423 #define ID_AA64ISAR1_EL1_SPECRES2_EN (2ull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2424 2425 #define ID_AA64ISAR1_EL1_SB_OFFSET 36 2426 #define ID_AA64ISAR1_EL1_SB_MASK (0xfull << ID_AA64ISAR1_EL1_SB_OFFSET) 2427 #define ID_AA64ISAR1_EL1_SB_EN (1ull << ID_AA64ISAR1_EL1_SB_OFFSET) 2428 2429 #define ID_AA64ISAR1_EL1_FRINTTS_OFFSET 32 2430 #define ID_AA64ISAR1_EL1_FRINTTS_MASK (0xfull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 2431 #define ID_AA64ISAR1_EL1_FRINTTS_EN (1ull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 2432 2433 #define ID_AA64ISAR1_EL1_GPI_OFFSET 28 2434 #define ID_AA64ISAR1_EL1_GPI_MASK (0xfull << ID_AA64ISAR1_EL1_GPI_OFFSET) 2435 #define ID_AA64ISAR1_EL1_GPI_EN (1ull << ID_AA64ISAR1_EL1_GPI_OFFSET) 2436 2437 #define ID_AA64ISAR1_EL1_GPA_OFFSET 24 2438 #define ID_AA64ISAR1_EL1_GPA_MASK (0xfull << ID_AA64ISAR1_EL1_GPA_OFFSET) 2439 2440 #define ID_AA64ISAR1_EL1_LRCPC_OFFSET 20 2441 #define ID_AA64ISAR1_EL1_LRCPC_MASK (0xfull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2442 #define ID_AA64ISAR1_EL1_LRCPC_EN (1ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2443 #define ID_AA64ISAR1_EL1_LRCP2C_EN (2ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2444 2445 #define ID_AA64ISAR1_EL1_FCMA_OFFSET 16 2446 #define ID_AA64ISAR1_EL1_FCMA_MASK (0xfull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 2447 #define ID_AA64ISAR1_EL1_FCMA_EN (1ull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 2448 2449 #define ID_AA64ISAR1_EL1_JSCVT_OFFSET 12 2450 #define ID_AA64ISAR1_EL1_JSCVT_MASK (0xfull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 2451 #define ID_AA64ISAR1_EL1_JSCVT_EN (1ull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 2452 2453 #define ID_AA64ISAR1_EL1_API_OFFSET 8 2454 #define ID_AA64ISAR1_EL1_API_MASK (0xfull << ID_AA64ISAR1_EL1_API_OFFSET) 2455 #define ID_AA64ISAR1_EL1_API_PAuth_EN (1ull << ID_AA64ISAR1_EL1_API_OFFSET) 2456 #define ID_AA64ISAR1_EL1_API_PAuth2_EN (3ull << ID_AA64ISAR1_EL1_API_OFFSET) 2457 #define ID_AA64ISAR1_EL1_API_FPAC_EN (4ull << ID_AA64ISAR1_EL1_API_OFFSET) 2458 #define ID_AA64ISAR1_EL1_API_FPACCOMBINE (5ull << ID_AA64ISAR1_EL1_API_OFFSET) 2459 2460 #define ID_AA64ISAR1_EL1_APA_OFFSET 4 2461 #define ID_AA64ISAR1_EL1_APA_MASK (0xfull << ID_AA64ISAR1_EL1_APA_OFFSET) 2462 2463 #define ID_AA64ISAR1_EL1_DPB_OFFSET 0 2464 #define ID_AA64ISAR1_EL1_DPB_MASK (0xfull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2465 #define ID_AA64ISAR1_EL1_DPB_EN (1ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2466 #define ID_AA64ISAR1_EL1_DPB2_EN (2ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2467 2468 /* 2469 * ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 2 2470 * 2471 * 63 56 55 52 51 24 23 20 19 8 7 4 3 0 2472 * +------+------+------+------+-------+-------+------+ 2473 * | res2 | CSSC | res1 | BC | res0 | RPRES | WFxT | 2474 * +------+------+------+------+-------+-------+------+ 2475 */ 2476 2477 #define ID_AA64ISAR2_EL1_CSSC_OFFSET 52 2478 #define ID_AA64ISAR2_EL1_CSSC_MASK (0xfull << ID_AA64ISAR2_EL1_CSSC_OFFSET) 2479 #define ID_AA64ISAR2_EL1_CSSC_EN (1ull << ID_AA64ISAR2_EL1_CSSC_OFFSET) 2480 2481 #define ID_AA64ISAR2_EL1_BC_OFFSET 20 2482 #define ID_AA64ISAR2_EL1_BC_MASK (0xfull << ID_AA64ISAR2_EL1_BC_OFFSET) 2483 #define ID_AA64ISAR2_EL1_BC_EN (1ull << ID_AA64ISAR2_EL1_BC_OFFSET) 2484 2485 #define ID_AA64ISAR2_EL1_RPRES_OFFSET 4 2486 #define ID_AA64ISAR2_EL1_RPRES_MASK (0xfull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 2487 #define ID_AA64ISAR2_EL1_RPRES_EN (1ull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 2488 2489 #define ID_AA64ISAR2_EL1_WFxT_OFFSET 0 2490 #define ID_AA64ISAR2_EL1_WFxT_MASK (0xfull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 2491 #define ID_AA64ISAR2_EL1_WFxT_EN (1ull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 2492 2493 /* 2494 * ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0 2495 * 63 60 59 56 55 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2496 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 2497 * | ECV | FGT | RES0 | ExS | TGran4_2 | TGran64_2 | TGran16_2 | TGran4 | TGran64 | TGran16 | BigEndEL0 | SNSMem | BigEnd | ASIDBits | PARange | 2498 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 2499 */ 2500 2501 #define ID_AA64MMFR0_EL1_ECV_OFFSET 60 2502 #define ID_AA64MMFR0_EL1_ECV_MASK (0xfull << ID_AA64MMFR0_EL1_ECV_OFFSET) 2503 #define ID_AA64MMFR0_EL1_ECV_EN (1ull << ID_AA64MMFR0_EL1_ECV_OFFSET) 2504 2505 /* 2506 * ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2 2507 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 14 8 7 4 3 0 2508 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 2509 * | E0PD | EVT | BBM | TTL | RES0 | FWB | IDS | AT | ST | NV | CCIDX | VARANGE | IESB | LSM | UAO | CnP | 2510 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 2511 */ 2512 2513 #define ID_AA64MMFR2_EL1_AT_OFFSET 32 2514 #define ID_AA64MMFR2_EL1_AT_MASK (0xfull << ID_AA64MMFR2_EL1_AT_OFFSET) 2515 #define ID_AA64MMFR2_EL1_AT_LSE2_EN (1ull << ID_AA64MMFR2_EL1_AT_OFFSET) 2516 #define ID_AA64MMFR2_EL1_VARANGE_OFFSET 16 2517 #define ID_AA64MMFR2_EL1_VARANGE_MASK (0xfull << ID_AA64MMFR2_EL1_VARANGE_OFFSET) 2518 2519 /* 2520 * ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 2521 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2522 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 2523 * | CSV3 | CSV2 | RES0 | DIT | AMU | MPAM | SEL2 | SVE | RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 | 2524 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 2525 */ 2526 2527 #define ID_AA64PFR0_EL1_CSV3_OFFSET 60 2528 #define ID_AA64PFR0_EL1_CSV3_MASK (0xfull << ID_AA64PFR0_EL1_CSV3_OFFSET) 2529 #define ID_AA64PFR0_EL1_CSV3_EN (1ull << ID_AA64PFR0_EL1_CSV3_OFFSET) 2530 2531 #define ID_AA64PFR0_EL1_CSV2_OFFSET 56 2532 #define ID_AA64PFR0_EL1_CSV2_MASK (0xfull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2533 #define ID_AA64PFR0_EL1_CSV2_EN (1ull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2534 #define ID_AA64PFR0_EL1_CSV2_2 (2ull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2535 2536 #define ID_AA64PFR0_EL1_DIT_OFFSET 48 2537 #define ID_AA64PFR0_EL1_DIT_MASK (0xfull << ID_AA64PFR0_EL1_DIT_OFFSET) 2538 #define ID_AA64PFR0_EL1_DIT_EN (1ull << ID_AA64PFR0_EL1_DIT_OFFSET) 2539 2540 #define ID_AA64PFR0_EL1_AdvSIMD_OFFSET 20 2541 #define ID_AA64PFR0_EL1_AdvSIMD_MASK (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2542 #define ID_AA64PFR0_EL1_AdvSIMD_HPFPCVT (0x0ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2543 #define ID_AA64PFR0_EL1_AdvSIMD_FP16 (0x1ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2544 #define ID_AA64PFR0_EL1_AdvSIMD_DIS (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2545 2546 /* 2547 * ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 2548 * 63 20 19 16 15 12 11 8 7 4 3 0 2549 * +----------------------------------+-----------+----------+-------+------+------+ 2550 * | RES0 | MPAM_frac | RAS_frac | MTE | SSBS | BT | 2551 * +----------------------------------+-----------+----------+-------+------+------+ 2552 */ 2553 2554 2555 2556 2557 #define ID_AA64PFR1_EL1_SME_OFFSET 24 2558 #define ID_AA64PFR1_EL1_SME_MASK (0xfull << ID_AA64PFR1_EL1_SME_OFFSET) 2559 #define ID_AA64PFR1_EL1_SME_EN (1ull << ID_AA64PFR1_EL1_SME_OFFSET) 2560 #define ID_AA64PFR1_EL1_CSV2_frac_OFFSET 32 2561 #define ID_AA64PFR1_EL1_CSV2_frac_MASK (0xfull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 2562 #define ID_AA64PFR1_EL1_CSV2_frac_1p1 (1ull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 2563 #define ID_AA64PFR1_EL1_CSV2_frac_1p2 (2ull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 2564 2565 2566 #define ID_AA64PFR1_EL1_SSBS_OFFSET 4 2567 #define ID_AA64PFR1_EL1_SSBS_MASK (0xfull << ID_AA64PFR1_EL1_SSBS_OFFSET) 2568 #define ID_AA64PFR1_EL1_SSBS_EN (1ull << ID_AA64PFR1_EL1_SSBS_OFFSET) 2569 2570 #define ID_AA64PFR1_EL1_BT_OFFSET 0 2571 #define ID_AA64PFR1_EL1_BT_MASK (0xfull << ID_AA64PFR1_EL1_BT_OFFSET) 2572 #define ID_AA64PFR1_EL1_BT_EN (1ull << ID_AA64PFR1_EL1_BT_OFFSET) 2573 2574 /* 2575 * ID_AA64PFR2_EL1 - AArch64 Processor Feature Register 2 2576 */ 2577 2578 2579 2580 2581 /* 2582 * ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1 2583 * 2584 * 63 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2585 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 2586 * | res0 | nTLBPA | AFP | HCX | ETS | TWED | XNX | SpecSEI | PAN | LO | HPDS | VH | VMIDBits | HAFDBS | 2587 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 2588 */ 2589 2590 #define ID_AA64MMFR1_EL1_AFP_OFFSET 44 2591 #define ID_AA64MMFR1_EL1_AFP_MASK (0xfull << ID_AA64MMFR1_EL1_AFP_OFFSET) 2592 #define ID_AA64MMFR1_EL1_AFP_EN (1ull << ID_AA64MMFR1_EL1_AFP_OFFSET) 2593 2594 #define ID_AA64MMFR1_EL1_HCX_OFFSET 40 2595 #define ID_AA64MMFR1_EL1_HCX_MASK (0xfull << ID_AA64MMFR1_EL1_HCX_OFFSET) 2596 #define ID_AA64MMFR1_EL1_HCX_EN (1ull << ID_AA64MMFR1_EL1_HCX_OFFSET) 2597 2598 /* 2599 * ID_AA64SMFR0_EL1 - SME Feature ID Register 0 2600 * 2601 * 63 62 60 59 56 55 52 51 49 48 47 44 43 40 39 36 35 34 33 32 31 0 2602 * +------+------+--------+--------+------+--------+--------+------+-------+--------+--------+---------+--------+------+ 2603 * | FA64 | res0 | SMEver | I16I64 | res0 | F64F64 | I16I32 | res0 | I8I32 | F16F32 | B16F32 | BI32I32 | F32F32 | res0 | 2604 * +------+------+--------+--------+------+--------+--------+------+-------+--------+--------+---------+--------+------+ 2605 */ 2606 2607 #define ID_AA64SMFR0_EL1_SMEver_OFFSET 56 2608 #define ID_AA64SMFR0_EL1_SMEver_MASK (0xfull << ID_AA64SMFR0_EL1_SMEver_OFFSET) 2609 #define ID_AA64SMFR0_EL1_SMEver_SME (0ull << ID_AA64SMFR0_EL1_SMEver_OFFSET) 2610 #define ID_AA64SMFR0_EL1_SMEver_SME2 (1ull << ID_AA64SMFR0_EL1_SMEver_OFFSET) 2611 2612 #define ID_AA64SMFR0_EL1_I16I64_OFFSET 52 2613 #define ID_AA64SMFR0_EL1_I16I64_MASK (0xfull << ID_AA64SMFR0_EL1_I16I64_OFFSET) 2614 #define ID_AA64SMFR0_EL1_I16I64_EN (0xfull << ID_AA64SMFR0_EL1_I16I64_OFFSET) 2615 2616 #define ID_AA64SMFR0_EL1_F64F64_OFFSET 48 2617 #define ID_AA64SMFR0_EL1_F64F64_MASK (1ull << ID_AA64SMFR0_EL1_F64F64_OFFSET) 2618 #define ID_AA64SMFR0_EL1_F64F64_EN (1ull << ID_AA64SMFR0_EL1_F64F64_OFFSET) 2619 2620 #define ID_AA64SMFR0_EL1_I16I32_OFFSET 44 2621 #define ID_AA64SMFR0_EL1_I16I32_MASK (0xfull << ID_AA64SMFR0_EL1_I16I32_OFFSET) 2622 #define ID_AA64SMFR0_EL1_I16I32_EN (0x5ull << ID_AA64SMFR0_EL1_I16I32_OFFSET) 2623 2624 2625 #define ID_AA64SMFR0_EL1_I8I32_OFFSET 36 2626 #define ID_AA64SMFR0_EL1_I8I32_MASK (0xfull << ID_AA64SMFR0_EL1_I8I32_OFFSET) 2627 #define ID_AA64SMFR0_EL1_I8I32_EN (0xfull << ID_AA64SMFR0_EL1_I8I32_OFFSET) 2628 2629 #define ID_AA64SMFR0_EL1_F16F32_OFFSET 35 2630 #define ID_AA64SMFR0_EL1_F16F32_MASK (1ull << ID_AA64SMFR0_EL1_F16F32_OFFSET) 2631 #define ID_AA64SMFR0_EL1_F16F32_EN (1ull << ID_AA64SMFR0_EL1_F16F32_OFFSET) 2632 2633 #define ID_AA64SMFR0_EL1_B16F32_OFFSET 34 2634 #define ID_AA64SMFR0_EL1_B16F32_MASK (1ull << ID_AA64SMFR0_EL1_B16F32_OFFSET) 2635 #define ID_AA64SMFR0_EL1_B16F32_EN (1ull << ID_AA64SMFR0_EL1_B16F32_OFFSET) 2636 2637 #define ID_AA64SMFR0_EL1_BI32I32_OFFSET 33 2638 #define ID_AA64SMFR0_EL1_BI32I32_MASK (1ull << ID_AA64SMFR0_EL1_BI32I32_OFFSET) 2639 #define ID_AA64SMFR0_EL1_BI32I32_EN (1ull << ID_AA64SMFR0_EL1_BI32I32_OFFSET) 2640 2641 #define ID_AA64SMFR0_EL1_F32F32_OFFSET 32 2642 #define ID_AA64SMFR0_EL1_F32F32_MASK (1ull << ID_AA64SMFR0_EL1_F32F32_OFFSET) 2643 #define ID_AA64SMFR0_EL1_F32F32_EN (1ull << ID_AA64SMFR0_EL1_F32F32_OFFSET) 2644 2645 2646 2647 2648 #define APSTATE_G_SHIFT (0) 2649 #define APSTATE_P_SHIFT (1) 2650 #define APSTATE_A_SHIFT (2) 2651 #define APSTATE_AP_MASK ((1ULL << APSTATE_A_SHIFT) | (1ULL << APSTATE_P_SHIFT)) 2652 2653 2654 #define ACTLR_EL1_EnTSO (1ULL << 1) 2655 #define ACTLR_EL1_EnAPFLG (1ULL << 4) 2656 #define ACTLR_EL1_EnAFP (1ULL << 5) 2657 #define ACTLR_EL1_EnPRSV (1ULL << 6) 2658 2659 2660 #if HAS_USAT_BIT 2661 #define ACTLR_EL1_USAT_OFFSET 0 2662 #define ACTLR_EL1_USAT_MASK (1ULL << ACTLR_EL1_USAT_OFFSET) 2663 #define ACTLR_EL1_USAT ACTLR_EL1_USAT_MASK 2664 #endif 2665 2666 2667 2668 2669 2670 2671 #ifdef HAS_DISDDHWP0 2672 #define ACTLR_EL1_DisDDHWP0_OFFSET 17 2673 #define ACTLR_EL1_DisDDHWP0_MASK (1ULL << ACTLR_EL1_DisDDHWP0_OFFSET) 2674 #define ACTLR_EL1_DisDDHWP0 ACTLR_EL1_DisDDHWP0_MASK 2675 #endif /* HAS_DISDDDHWP0 */ 2676 2677 2678 #if defined(HAS_APPLE_PAC) 2679 // The value of ptrauth_string_discriminator("recover"), hardcoded so it can be used from assembly code 2680 #define PAC_DISCRIMINATOR_RECOVER 0x1e02 2681 #endif 2682 2683 2684 #define CTR_EL0_L1Ip_OFFSET 14 2685 #define CTR_EL0_L1Ip_VIPT (2ULL << CTR_EL0_L1Ip_OFFSET) 2686 #define CTR_EL0_L1Ip_PIPT (3ULL << CTR_EL0_L1Ip_OFFSET) 2687 #define CTR_EL0_L1Ip_MASK (3ULL << CTR_EL0_L1Ip_OFFSET) 2688 2689 2690 #ifdef __ASSEMBLER__ 2691 2692 /* 2693 * Conditionally write to system/special-purpose register. 2694 * The register is written to only when the first two arguments 2695 * do not match. If they do match, the macro jumps to a 2696 * caller-provided label. 2697 * The _ISB variant also conditionally issues an ISB after the MSR. 2698 * 2699 * $0 - System/special-purpose register to modify 2700 * $1 - Register containing current FPCR value 2701 * $2 - Register containing expected value 2702 * $3 - Label to jump to when register is already set to expected value 2703 */ 2704 .macro CMSR 2705 cmp $1, $2 2706 2707 /* Skip expensive MSR if not required */ 2708 b.eq $3f 2709 msr $0, $2 2710 .endmacro 2711 2712 .macro CMSR_ISB 2713 CMSR $0, $1, $2, $3 2714 isb sy 2715 .endmacro 2716 2717 /* 2718 * Modify FPCR only if it does not contain the XNU default value. 2719 * $0 - Register containing current FPCR value 2720 * $1 - Scratch register 2721 * $2 - Label to jump to when FPCR is already set to default value 2722 */ 2723 .macro SANITIZE_FPCR 2724 mov $1, #FPCR_DEFAULT 2725 CMSR FPCR, $0, $1, $2 2726 .endmacro 2727 2728 /* 2729 * Family of macros that can be used to protect code sections such that they 2730 * are only executed on a particular SoC/Revision/CPU, and skipped otherwise. 2731 * All macros will forward-jump to 1f when the condition is not matched. 2732 * This label may be defined manually, or implicitly through the use of 2733 * the EXEC_END macro. 2734 * For cores, XX can be: EQ (equal), ALL (don't care). 2735 * For revisions, XX can be: EQ (equal), LO (lower than), HS (higher or same), ALL (don't care). 2736 */ 2737 2738 /* 2739 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 2740 * $1 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2741 * $2 - GPR containing MIDR_EL1 value 2742 * $3 - Scratch register 2743 */ 2744 .macro EXEC_COREEQ_REVEQ 2745 and $3, $2, #MIDR_EL1_PNUM_MASK 2746 cmp $3, $0 2747 b.ne 1f 2748 2749 mov $3, $2 2750 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2751 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2752 cmp $3, $1 2753 b.ne 1f 2754 .endmacro 2755 2756 .macro EXEC_COREEQ_REVLO 2757 and $3, $2, #MIDR_EL1_PNUM_MASK 2758 cmp $3, $0 2759 b.ne 1f 2760 2761 mov $3, $2 2762 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2763 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2764 cmp $3, $1 2765 b.pl 1f 2766 .endmacro 2767 2768 .macro EXEC_COREEQ_REVHS 2769 and $3, $2, #MIDR_EL1_PNUM_MASK 2770 cmp $3, $0 2771 b.ne 1f 2772 2773 mov $3, $2 2774 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2775 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2776 cmp $3, $1 2777 b.mi 1f 2778 .endmacro 2779 2780 /* 2781 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2782 * $1 - GPR containing MIDR_EL1 value 2783 * $2 - Scratch register 2784 */ 2785 .macro EXEC_COREALL_REVEQ 2786 mov $2, $1 2787 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2788 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2789 cmp $2, $0 2790 b.ne 1f 2791 .endmacro 2792 2793 .macro EXEC_COREALL_REVLO 2794 mov $2, $1 2795 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2796 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2797 cmp $2, $0 2798 b.pl 1f 2799 .endmacro 2800 2801 .macro EXEC_COREALL_REVHS 2802 mov $2, $1 2803 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2804 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2805 cmp $2, $0 2806 b.mi 1f 2807 .endmacro 2808 2809 .macro CMP_FOREACH reg, cc, label, car, cdr:vararg 2810 cmp \reg, \car 2811 b.\cc \label 2812 .ifnb \cdr 2813 CMP_FOREACH \reg, \cc, \label, \cdr 2814 .endif 2815 .endm 2816 2817 .macro EXEC_COREIN_REVALL midr_el1, scratch, midr_list:vararg 2818 and \scratch, \midr_el1, #MIDR_EL1_PNUM_MASK 2819 CMP_FOREACH \scratch, eq, Lmatch\@, \midr_list 2820 b 1f 2821 Lmatch\@: 2822 .endm 2823 2824 /* 2825 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 2826 * $1 - GPR containing MIDR_EL1 value 2827 * $2 - Scratch register 2828 */ 2829 .macro EXEC_COREEQ_REVALL 2830 and $2, $1, #MIDR_EL1_PNUM_MASK 2831 cmp $2, $0 2832 b.ne 1f 2833 .endmacro 2834 2835 /* 2836 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2837 * $1 - GPR containing MIDR_EL1 value 2838 * $2 - Scratch register 2839 */ 2840 .macro EXEC_PCORE_REVEQ 2841 ARM64_IS_PCORE $2 2842 cbz $2, 1f 2843 2844 mov $2, $1 2845 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2846 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2847 cmp $2, $0 2848 b.ne 1f 2849 .endmacro 2850 2851 .macro EXEC_PCORE_REVLO 2852 ARM64_IS_PCORE $2 2853 cbz $2, 1f 2854 2855 mov $2, $1 2856 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2857 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2858 cmp $2, $0 2859 b.pl 1f 2860 .endmacro 2861 2862 .macro EXEC_PCORE_REVHS 2863 ARM64_IS_PCORE $2 2864 cbz $2, 1f 2865 2866 mov $2, $1 2867 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2868 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2869 cmp $2, $0 2870 b.mi 1f 2871 .endmacro 2872 2873 .macro EXEC_ECORE_REVEQ 2874 ARM64_IS_ECORE $2 2875 cbz $2, 1f 2876 2877 mov $2, $1 2878 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2879 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2880 cmp $2, $0 2881 b.ne 1f 2882 .endmacro 2883 2884 .macro EXEC_ECORE_REVLO 2885 ARM64_IS_ECORE $2 2886 cbz $2, 1f 2887 2888 mov $2, $1 2889 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2890 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2891 cmp $2, $0 2892 b.pl 1f 2893 .endmacro 2894 2895 .macro EXEC_ECORE_REVHS 2896 ARM64_IS_ECORE $2 2897 cbz $2, 1f 2898 2899 mov $2, $1 2900 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2901 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2902 cmp $2, $0 2903 b.mi 1f 2904 .endmacro 2905 2906 /* 2907 * $0 - GPR containing MIDR_EL1 value 2908 * $1 - Scratch register 2909 */ 2910 .macro EXEC_PCORE_REVALL 2911 ARM64_IS_PCORE $1 2912 cbz $1, 1f 2913 .endmacro 2914 2915 .macro EXEC_ECORE_REVALL 2916 ARM64_IS_ECORE $1 2917 cbz $1, 1f 2918 .endmacro 2919 2920 /* 2921 * Macro that defines the label that all EXEC_COREXX_REVXX macros jump to. 2922 */ 2923 .macro EXEC_END 2924 1: 2925 .endmacro 2926 2927 /* 2928 * Wedges CPUs with a specified core that are below a specified revision. This 2929 * macro is intended for CPUs that have been deprecated in iBoot and may have 2930 * incorrect behavior if they continue running xnu. 2931 */ 2932 .macro DEPRECATE_COREEQ_REVLO core, rev, midr_el1, scratch 2933 EXEC_COREEQ_REVLO \core, \rev, \midr_el1, \scratch 2934 /* BEGIN IGNORE CODESTYLE */ 2935 b . 2936 /* END IGNORE CODESTYLE */ 2937 EXEC_END 2938 .endmacro 2939 2940 /* 2941 * Sets bits in an SPR register. 2942 * arg0: Name of the register to be accessed. 2943 * arg1: Mask of bits to be set. 2944 * arg2: Scratch register 2945 */ 2946 .macro HID_SET_BITS 2947 mrs $2, $0 2948 orr $2, $2, $1 2949 msr $0, $2 2950 .endmacro 2951 2952 /* 2953 * Clears bits in an SPR register. 2954 * arg0: Name of the register to be accessed. 2955 * arg1: Mask of bits to be cleared. 2956 * arg2: Scratch register 2957 */ 2958 .macro HID_CLEAR_BITS 2959 mrs $2, $0 2960 bic $2, $2, $1 2961 msr $0, $2 2962 .endmacro 2963 2964 /* 2965 * Combines the functionality of HID_CLEAR_BITS followed by HID_SET_BITS into 2966 * a single read-modify-write sequence. 2967 * arg0: Name of the register to be accessed. 2968 * arg1: Mask of bits to be cleared. 2969 * arg2: Value to insert 2970 * arg3: Scratch register 2971 */ 2972 .macro HID_INSERT_BITS 2973 mrs $3, $0 2974 bic $3, $3, $1 2975 orr $3, $3, $2 2976 msr $0, $3 2977 .endmacro 2978 2979 /* 2980 * Replaces the value of a field in an implementation-defined system register. 2981 * sreg: system register name 2982 * field: field name within the sysreg, where the assembler symbols 2983 * ARM64_REG_<field>_{shift,width} specify the bounds of the field 2984 * (note that preprocessor macros will not work here) 2985 * value: the value to insert 2986 * scr{1,2}: scratch regs 2987 */ 2988 .macro HID_WRITE_FIELD sreg, field, val, scr1, scr2 2989 mrs \scr1, \sreg 2990 mov \scr2, \val 2991 bfi \scr1, \scr2, ARM64_REG_\sreg\()_\field\()_shift, ARM64_REG_\sreg\()_\field\()_width 2992 msr \sreg, \scr1 2993 .endmacro 2994 2995 /* 2996 * This macro is a replacement for ERET with better security properties. 2997 * 2998 * It prevents "straight-line speculation" (an Arm term) past the ERET. 2999 */ 3000 .macro ERET_NO_STRAIGHT_LINE_SPECULATION 3001 eret 3002 #if __ARM_SB_AVAILABLE__ 3003 sb // Technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 3004 #else /* __ARM_SB_AVAILABLE__ */ 3005 isb // ISB technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 3006 nop // Sequence of six NOPs to pad out and terminate instruction decode group */ 3007 nop 3008 nop 3009 nop 3010 nop 3011 nop 3012 #endif /* !__ARM_SB_AVAILABLE__ */ 3013 .endmacro 3014 3015 3016 #endif /* __ASSEMBLER__ */ 3017 3018 #define MSR(reg, src) __asm__ volatile ("msr " reg ", %0" :: "r" (src)) 3019 #define MRS(dest, reg) __asm__ volatile ("mrs %0, " reg : "=r" (dest)) 3020 3021 #if XNU_MONITOR 3022 #define __ARM_PTE_PHYSMAP__ 1 3023 #define PPL_STATE_KERNEL 0 3024 #define PPL_STATE_DISPATCH 1 3025 #define PPL_STATE_PANIC 2 3026 #define PPL_STATE_EXCEPTION 3 3027 #endif 3028 3029 3030 #endif /* _ARM64_PROC_REG_H_ */ 3031