1 /* 2 * Copyright (c) 2019 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 29 #ifndef _PEXPERT_ARM64_VMAPPLE_H 30 #define _PEXPERT_ARM64_VMAPPLE_H 31 32 #define NO_MONITOR 1 33 #define NO_ECORE 1 34 35 #define VMAPPLE 1 36 #define APPLEVIRTUALPLATFORM 1 37 38 #define CPU_HAS_APPLE_PAC 1 39 #define HAS_PARAVIRTUALIZED_PAC 1 40 #define HAS_GIC_V3 1 41 #define HAS_ARM_FEAT_SSBS2 1 42 #define HAS_ARM_FEAT_SME 1 43 #define HAS_ARM_FEAT_SME2 1 44 #define HAS_ARM_FEAT_PAN3 1 45 46 #define __ARM_PAN_AVAILABLE__ 1 47 #define __ARM_16K_PG__ 1 48 #define __ARM_RANGE_TLBI__ 1 49 50 #define ARM_PARAMETERIZED_PMAP 1 51 #define __ARM_MIXED_PAGE_SIZE__ 1 52 53 #include <pexpert/arm64/apple_arm64_common.h> 54 #undef __ARM64_PMAP_SUBPAGE_L1__ 55 56 #ifndef ASSEMBLER 57 #define PL011_UART 58 #define PLATFORM_PANIC_LOG_DISABLED 59 #endif /* ! ASSEMBLER */ 60 61 62 #define GIC_SPURIOUS_IRQ 1023 // IRQ no. for GIC spurious interrupt 63 64 #define GICR_PE_SIZE 0x20000 // Size of each redistributor region 65 66 67 /* GICv3 reigster definitions; see GICv3 spec (Arm IHI 0069G) for more about these registers */ 68 #define GICD_CTLR 0x0 69 70 #define GICD_CTLR_ENABLEGRP0 0x1 71 72 #define GICR_TYPER 0x08 73 #define GICR_WAKER 0x14 74 #define GICR_IGROUPR0 0x10080 75 #define GICR_ISENABLER0 0x10100 76 77 #define GICR_TYPER_AFFINITY_VALUE_SHIFT 32 78 #define GICR_TYPER_LAST 0x10 79 80 #define GICR_WAKER_PROCESSORSLEEP 0x2 81 #define GICR_WAKER_CHILDRENASLEEP 0x4 82 83 #define ICC_CTLR_EOIMODE 0x1 84 85 #define ICC_SRE_SRE 0x1 86 /* End of GICv3 register definitions */ 87 88 #endif /* ! _PEXPERT_ARM64_VMAPPLE_H */ 89