Searched refs:MMU_I_CLINE (Results 1 – 2 of 2) sorted by relevance
153 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro161 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro169 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro177 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro185 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro193 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro201 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro209 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro217 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro225 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ macro[all …]
66 mov x9, #((1<<MMU_I_CLINE)-1) 71 lsr x1, x1, #MMU_I_CLINE // Set cache line counter74 add x0, x0, #1<<MMU_I_CLINE // Get next cache aligned addr