1 /* 2 * Copyright (c) 2007-2023 Apple Inc. All rights reserved. 3 * Copyright (c) 2005-2006 Apple Computer, Inc. All rights reserved. 4 */ 5 #ifndef _PEXPERT_ARM_BOARD_CONFIG_H 6 #define _PEXPERT_ARM_BOARD_CONFIG_H 7 8 #include <mach/machine.h> 9 10 /* 11 * Per-SoC configuration. General order is: 12 * 13 * CPU type 14 * CPU configuration 15 * CPU feature disables / workarounds 16 * CPU topology 17 * Other platform configuration (e.g. DARTs, PPL) 18 * 19 * This should answer the question: "what's unique about this SoC?" 20 * 21 * arm64/H*.h should answer the question: "what's unique about this CPU core?" 22 * 23 * For __ARM_AMP__ systems that have different cache line sizes on different 24 * clusters, MAX_L2_CLINE must reflect the largest L2 cache line size 25 * across all clusters. 26 */ 27 28 #ifdef ARM64_BOARD_CONFIG_T6000 29 #include <pexpert/arm64/H13.h> 30 31 32 #define MAX_L2_CLINE 7 33 #define MAX_CPUS 20 34 #define MAX_CPU_CLUSTERS 6 35 #define MAX_CPU_CLUSTER_PHY_ID 10 36 #define HAS_IOA 1 37 38 #define PMAP_CS 1 39 #define PMAP_CS_ENABLE 1 40 #define XNU_MONITOR 1 /* Secure pmap runtime */ 41 #define __ARM_42BIT_PA_SPACE__ 1 42 #define USE_APPLEARMSMP 1 43 44 45 #if DEVELOPMENT || DEBUG 46 #define XNU_ENABLE_PROCESSOR_EXIT 1 /* Enable xnu processor_exit() by default */ 47 #endif 48 #define XNU_HANDLE_MCC 1 /* This platform may support MCC error recovery */ 49 #endif /* ARM64_BOARD_CONFIG_T6000 */ 50 51 #ifdef ARM64_BOARD_CONFIG_T6020 52 #include <pexpert/arm64/H14.h> 53 54 #define MAX_L2_CLINE 7 55 #define MAX_CPUS 24 56 #define MAX_CPU_CLUSTERS 6 57 #define MAX_CPU_CLUSTER_PHY_ID 10 58 #define HAS_IOA 1 59 60 #ifndef CONFIG_SPTM 61 #define PMAP_CS 1 62 #define PMAP_CS_ENABLE 1 63 #define XNU_MONITOR 1 /* Secure pmap runtime */ 64 #endif /* CONFIG_SPTM */ 65 66 67 #define __ARM_42BIT_PA_SPACE__ 1 68 #define USE_APPLEARMSMP 1 69 #define XNU_CLUSTER_POWER_DOWN 1 /* Enable xnu cluster power down by default */ 70 #define RHODES_CLUSTER_POWERDOWN_WORKAROUND 1 /* Workaround for rdar://89107373 (Rhodes cluster power down: cannot manually power down and up a core multiple times without powering down the cluster) */ 71 #define XNU_PLATFORM_ERROR_HANDLER 1 /* This platform uses the platform error handler inside XNU rather than a kext */ 72 #ifndef CONFIG_SPTM 73 #define XNU_HANDLE_ECC 1 /* This platform may support ECC error recovery */ 74 #endif /* !CONFIG_SPTM */ 75 #define XNU_HANDLE_MCC 1 /* This platform may support MCC error recovery */ 76 #define EXTENDED_USER_VA_SUPPORT 1 /* On certain OSes, support larger user address spaces */ 77 #endif /* ARM64_BOARD_CONFIG_T6020 */ 78 79 80 81 82 83 84 85 86 #ifdef ARM64_BOARD_CONFIG_T8101 87 #include <pexpert/arm64/H13.h> 88 89 #define MAX_L2_CLINE 7 90 #define MAX_CPUS 8 91 #define MAX_CPU_CLUSTERS 2 92 93 #define PMAP_CS 1 94 #define PMAP_CS_ENABLE 1 95 #define XNU_MONITOR 1 /* Secure pmap runtime */ 96 #endif /* ARM64_BOARD_CONFIG_T8101 */ 97 98 #ifdef ARM64_BOARD_CONFIG_T8103 99 #include <pexpert/arm64/H13.h> 100 101 #define MAX_L2_CLINE 7 102 #define MAX_CPUS 8 103 #define MAX_CPU_CLUSTERS 2 104 105 #define PMAP_CS 1 106 #define PMAP_CS_ENABLE 1 107 #define XNU_MONITOR 1 /* Secure pmap runtime */ 108 #endif /* ARM64_BOARD_CONFIG_T8103 */ 109 110 111 #ifdef ARM64_BOARD_CONFIG_T8112 112 #include <pexpert/arm64/H14.h> 113 114 #define MAX_L2_CLINE 7 115 #define MAX_CPUS 8 /* Actually has 6 CPUs, see doc/xnu_build_consolidation.md for more info */ 116 #define MAX_CPU_CLUSTERS 2 117 118 #ifndef CONFIG_SPTM 119 #define PMAP_CS 1 120 #define PMAP_CS_ENABLE 1 121 #define XNU_MONITOR 1 /* Secure pmap runtime */ 122 #endif /* CONFIG_SPTM */ 123 124 #if CONFIG_SPTM 125 /* SPTM TODO: Add support for HWTRACE */ 126 #undef CPU_HAS_SW_TRACE_DATA 127 #endif 128 129 #define USE_APPLEARMSMP 1 130 #endif /* ARM64_BOARD_CONFIG_T8112 */ 131 132 133 #ifdef ARM64_BOARD_CONFIG_T8122_T8130 134 #include <pexpert/arm64/H15.h> 135 136 #define MAX_L2_CLINE 7 137 #define MAX_CPUS 8 138 #define MAX_CPU_CLUSTERS 2 139 #define HAS_IOA 1 140 141 #ifndef CONFIG_SPTM 142 #define PMAP_CS 1 143 #define PMAP_CS_ENABLE 1 144 #define XNU_MONITOR 1 /* Secure pmap runtime */ 145 #endif /* CONFIG_SPTM */ 146 147 148 #if CONFIG_SPTM 149 /* SPTM TODO: Add support for HWTRACE */ 150 #undef CPU_HAS_SW_TRACE_DATA 151 #endif 152 153 #define __ARM_42BIT_PA_SPACE__ 1 154 #define USE_APPLEARMSMP 1 155 #define XNU_PLATFORM_ERROR_HANDLER 1 /* This platform uses the platform error handler inside XNU rather than a kext */ 156 #define XNU_HANDLE_MCC 1 /* This platform may support MCC error recovery */ 157 #endif /* ARM64_BOARD_CONFIG_T8122_T8130 */ 158 159 #ifdef ARM64_BOARD_CONFIG_T8132 160 #include <pexpert/arm64/H16.h> 161 162 #define MAX_L2_CLINE 7 163 #define MAX_CPUS 10 164 #define MAX_CPU_CLUSTERS 2 165 166 #ifndef CONFIG_SPTM 167 #define PMAP_CS 1 168 #define PMAP_CS_ENABLE 1 169 #define XNU_MONITOR 1 /* Secure pmap runtime */ 170 #endif /* CONFIG_SPTM */ 171 172 #if CONFIG_SPTM 173 /* SPTM TODO: Add support for HWTRACE */ 174 #undef CPU_HAS_SW_TRACE_DATA 175 #endif 176 177 #define __ARM_42BIT_PA_SPACE__ 1 178 #define USE_APPLEARMSMP 1 179 #define XNU_PLATFORM_ERROR_HANDLER 1 /* This platform uses the platform error handler inside XNU rather than a kext */ 180 #define XNU_HANDLE_MCC 1 /* This platform may support MCC error recovery */ 181 #define NO_CPU_OVRD 1 /* CPU_OVRD register accesses are banned */ 182 183 184 185 #endif /* ARM64_BOARD_CONFIG_T8132 */ 186 187 188 189 190 191 192 #ifdef ARM64_BOARD_CONFIG_T6030 193 194 #include <pexpert/arm64/H15.h> 195 196 #define MAX_L2_CLINE 7 197 #define MAX_CPUS 12 198 #define MAX_CPU_CLUSTERS 2 199 #define HAS_IOA 1 200 201 #ifndef CONFIG_SPTM 202 #define PMAP_CS 1 203 #define PMAP_CS_ENABLE 1 204 #define XNU_MONITOR 1 /* Secure pmap runtime */ 205 #endif /* CONFIG_SPTM */ 206 207 #define __ARM_42BIT_PA_SPACE__ 1 208 #define USE_APPLEARMSMP 1 209 #define XNU_PLATFORM_ERROR_HANDLER 1 /* This platform uses the platform error handler inside XNU rather than a kext */ 210 #define XNU_HANDLE_MCC 1 /* This platform may support MCC error recovery */ 211 #endif /* ARM64_BOARD_CONFIG_T6030 */ 212 213 214 #ifdef ARM64_BOARD_CONFIG_T6031 215 216 #include <pexpert/arm64/H15.h> 217 218 #define MAX_L2_CLINE 7 219 #define MAX_CPUS 32 220 #define MAX_CPU_CLUSTERS 6 221 #define MAX_CPU_CLUSTER_PHY_ID 10 222 #define HAS_IOA 1 223 224 #ifndef CONFIG_SPTM 225 #define PMAP_CS 1 226 #define PMAP_CS_ENABLE 1 227 #define XNU_MONITOR 1 /* Secure pmap runtime */ 228 #endif /* CONFIG_SPTM */ 229 230 #define __ARM_42BIT_PA_SPACE__ 1 231 #define USE_APPLEARMSMP 1 232 #define XNU_CLUSTER_POWER_DOWN 1 /* Enable xnu cluster power down by default */ 233 #define RHODES_CLUSTER_POWERDOWN_WORKAROUND 1 /* Workaround for rdar://89107373 (Rhodes cluster power down: cannot manually power down and up a core multiple times without powering down the cluster) */ 234 #endif /* ARM64_BOARD_CONFIG_T6031 */ 235 236 237 238 239 240 #ifdef ARM64_BOARD_CONFIG_VMAPPLE 241 #include <pexpert/arm64/VMAPPLE.h> 242 243 #define MAX_L2_CLINE 7 244 #define MAX_CPUS 32 /* limited by CPU copy window size and cpu checkin mask */ 245 #define MAX_CPU_CLUSTERS 1 246 247 #define CORE_NCTRS 2 248 249 #define USE_APPLEARMSMP 1 250 251 #if XNU_TARGET_OS_WATCH 252 #define PREFER_ARM64_32_BINARIES 1 253 #endif 254 255 256 #endif /* ARM64_BOARD_CONFIG_VMAPPLE */ 257 258 259 260 #ifndef HAS_UNCORE_CTRS 261 #undef UNCORE_VERSION 262 #undef UNCORE_PER_CLUSTER 263 #undef UNCORE_NCTRS 264 #endif 265 266 #if MAX_CPU_CLUSTERS == 1 267 #undef __ARM_AMP__ 268 #endif 269 270 #ifndef MAX_CPU_CLUSTER_PHY_ID 271 #define MAX_CPU_CLUSTER_PHY_ID (MAX_CPU_CLUSTERS - 1) 272 #endif 273 274 #ifdef PREFER_ARM64_32_BINARIES 275 #define PREFERRED_USER_CPU_TYPE CPU_TYPE_ARM64_32 276 #define PREFERRED_USER_CPU_SUBTYPE CPU_SUBTYPE_ARM64_32_V8 277 #endif 278 279 280 /* 281 * Some platforms have very expensive timebase routines. An optimization 282 * is to avoid switching timers on kernel exit/entry, which results in all 283 * time billed to the system timer. However, when exposed to userspace, it's 284 * reported as user time to indicate that work was done on behalf of 285 * userspace. 286 */ 287 288 #if CONFIG_SKIP_PRECISE_USER_KERNEL_TIME 289 #define PRECISE_USER_KERNEL_TIME HAS_FAST_CNTVCT 290 #else /* CONFIG_SKIP_PRECISE_USER_KERNEL_TIME */ 291 #define PRECISE_USER_KERNEL_TIME 1 292 #endif /* !CONFIG_SKIP_PRECISE_USER_KERNEL_TIME */ 293 294 /** 295 * On supported hardware, debuggable builds make the HID bits read-only 296 * without locking them. This lets people manually modify HID bits while 297 * debugging, since they can use a debugging tool to first reset the HID 298 * bits back to read/write. However it will still catch xnu changes that 299 * accidentally write to HID bits after they've been made read-only. 300 */ 301 302 303 304 #endif /* ! _PEXPERT_ARM_BOARD_CONFIG_H */ 305