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Searched refs:MSR (Results 1 – 3 of 3) sorted by relevance

/xnu-11215.61.5/osfmk/arm64/
H A Dmachine_routines.c223 MSR("S3_5_C15_C0_0", x); in ml_cpu_signal_type()
227 MSR("S3_5_C15_C0_1", x); in ml_cpu_signal_type()
231 MSR("S3_5_C15_C0_1", x); in ml_cpu_signal_type()
283 MSR("S3_5_C15_C3_1", abstime); in ml_cpu_signal_deferred_adjust_timer()
H A Dproc_reg.h2916 #define MSR(reg, src) __asm__ volatile ("msr " reg ", %0" :: "r" (src)) macro
H A Dsleh.c2434 MSR("S3_5_C15_C1_1", ARM64_IPISR_IPI_PENDING); in sleh_fiq()