1 /* 2 * Copyright (c) 2007 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 /* 32 * Mach Operating System 33 * Copyright (c) 1991,1990 Carnegie Mellon University 34 * All Rights Reserved. 35 * 36 * Permission to use, copy, modify and distribute this software and its 37 * documentation is hereby granted, provided that both the copyright 38 * notice and this permission notice appear in all copies of the 39 * software, derivative works or modified versions, and any portions 40 * thereof, and that both notices appear in supporting documentation. 41 * 42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 45 * 46 * Carnegie Mellon requests users of this software to return to 47 * 48 * Software Distribution Coordinator or [email protected] 49 * School of Computer Science 50 * Carnegie Mellon University 51 * Pittsburgh PA 15213-3890 52 * 53 * any improvements or extensions that they make and grant Carnegie Mellon 54 * the rights to redistribute these changes. 55 */ 56 /* 57 */ 58 59 #ifndef _ARM_TRAP_INTERNAL_H_ 60 #define _ARM_TRAP_INTERNAL_H_ 61 62 #include <arm/trap.h> 63 #include <arm/thread.h> 64 65 #define GDB_TRAP_INSTR1 0xe7ffdefe 66 #define GDB_TRAP_INSTR2 0xe7ffdeff 67 68 #define ARM_GDB_INSTR1 GDB_TRAP_INSTR1 69 #define ARM_GDB_INSTR2 GDB_TRAP_INSTR2 70 71 #define IS_ARM_GDB_TRAP(op) \ 72 (((op) == ARM_GDB_INSTR1) || ((op) == ARM_GDB_INSTR2)) 73 74 #define THUMB_GDB_INSTR1 (GDB_TRAP_INSTR1 & 0xFFFF) 75 #define THUMB_GDB_INSTR2 (GDB_TRAP_INSTR2 & 0xFFFF) 76 77 #define IS_THUMB_GDB_TRAP(op) \ 78 (((op) == THUMB_GDB_INSTR1) || ((op) == THUMB_GDB_INSTR2)) 79 80 81 #define ARM_STR 0x04000000 /* STR */ 82 #define ARM_STRH 0x000000B0 /* STRH */ 83 #define ARM_STRH_MASK 0x0E1000F0 /* STRH MASK */ 84 #define ARM_SDX_MASK 0x0C100000 /* SINGLE DATA TRANSFER */ 85 #define ARM_SNGL_DX_MASK 0x0C000000 /* SINGLE DATA TRANSFER MASK */ 86 #define ARM_SDX 0x04000000 87 88 #define ARM_STM 0x08000000 /* STM */ 89 #define ARM_BDX_MASK 0x0E100000 /* BLOCK DATA TRANSFER */ 90 #define ARM_BLK_MASK 0x0E000000 /* BLOCK DATA TRANSFER */ 91 #define ARM_BDX 0x08000000 /* BLOCK DATA TRANSFER */ 92 93 #define ARM_WRITE_BACK 0x00200000 94 #define ARM_BASE_REG 0x000F0000 95 #define ARM_INCREMENT 0x00800000 96 97 #define ARM_STC 0x0C000000 /* STC */ 98 #define ARM_CDX_MASK ARM_BDX_MASK /* COPROCESSOR DATA TRANSFER */ 99 #define ARM_CBLK_MASK ARM_BLK_MASK 100 #define ARM_CDX 0x0C000000 /* COPROCESSOR DATA TRANSFER */ 101 102 #define ARM_SWP 0x01000090 /* SWP */ 103 #define ARM_SWP_MASK 0x0FB00FF0 /* SWP */ 104 105 #define ARM_POST_INDEXING 0x01000000 106 #define ARM_IMMEDIATE 0x02000000 107 #define ARM_LSL 0 108 #define ARM_LSR 1 109 #define ARM_ASR 2 110 #define ARM_ROR 3 111 112 #define MCR_MASK 0x0F100F10 113 #define MCR_CP15 0x0E000F10 114 #define MCRR_MASK 0x0FF00F00 115 #define MCRR_CP15 0x0C400F00 116 117 #define arm_mcr_cp15(op) (((op)&MCR_MASK) == 0x0E000F10) 118 #define arm_mcrr_cp15(op) (((op)&0x0FF00F00) == 0x0C400F00) 119 120 #define IS_THUMB32(op) ( \ 121 (((op) & 0xE000) == 0xE000) && (((op) & 0x1800) != 0x0000)) 122 123 #define THUMB_LDR_1_MASK 0x8800 /* (1) forms of LD* instructions */ 124 #define THUMB_STR_1_MASK 0xF800 /* (1) forms of ST* instructions */ 125 #define THUMB_STR_2_MASK 0xFE00 /* (2) forms of ST* instructions */ 126 #define THUMB_STR_3_MASK 0xF800 /* (3) forms of ST* instructions */ 127 #define THUMB_PUSH_MASK 0xFE00 /* PUSH instruction */ 128 129 #define THUMB_LDRH_1 0x8800 /* LDRH(1) */ 130 #define THUMB_STMIA 0xC000 /* STMIA */ 131 #define THUMB_STR_1 0x6000 /* STR(1) */ 132 #define THUMB_STR_2 0x5000 /* STR(2) */ 133 #define THUMB_STR_3 0x9000 /* STR(3) */ 134 #define THUMB_STRB_1 0x7000 /* STRB(1) */ 135 #define THUMB_STRB_2 0x5400 /* STRB(2) */ 136 #define THUMB_STRH_1 0x8000 /* STRH(1) */ 137 #define THUMB_STRH_2 0x5200 /* STRH(2) */ 138 #define THUMB_PUSH 0xB400 /* PUSH */ 139 #define THUMB_LDMIA 0xC800 /* LDMIA */ 140 #define THUMB_POP 0xBC00 /* POP */ 141 142 143 /* 144 * Shifts, masks, and other values for load/store multiple decoding; largely needed for 145 * supporting misaligned accesses. 146 */ 147 #define THUMB_STR_1_BASE_OFFSET 8 /* Offset of the base register field */ 148 #define THUMB_PUSH_EXTRA_OFFSET 8 /* Offset of the "extra" register field */ 149 #define ARM_STM_BASE_OFFSET 16 /* Offset of the base register field */ 150 #define ARM_STM_LOAD_OFFSET 20 /* Offset of the load flag */ 151 #define ARM_STM_WBACK_OFFSET 21 /* Offset of the writeback flag */ 152 #define ARM_STM_INCR_OFFSET 23 /* Offset of the increment flag */ 153 #define ARM_STM_BEFORE_OFFSET 24 /* Offset of the pre-index flag */ 154 #define ARM_REG_LIST_LR_OFFSET 14 /* Offset of LR in the register list */ 155 #define ARM_REG_LIST_PC_OFFSET 15 /* Offset of PC in the register list */ 156 157 #define THUMB_STR_REG_LIST_MASK 0x000000FF /* Offset of the reg list is 0 */ 158 #define THUMB_STR_1_BASE_MASK 0x00000700 159 #define THUMB_PUSH_EXTRA_MASK 0x00000100 160 #define ARM_STM_REG_LIST_MASK 0x0000FFFF /* Offset of the reg list is 0 */ 161 #define ARM_STM_BASE_MASK 0x000F0000 162 #define ARM_STM_LOAD_MASK 0x00100000 163 #define ARM_STM_WBACK_MASK 0x00200000 164 #define ARM_STM_INCR_MASK 0x00800000 165 #define ARM_STM_BEFORE_MASK 0x01000000 166 #define ARM_COND_MASK 0xF0000000 /* Mask for the condition code */ 167 168 #define ARM_COND_UNCOND 0xF0000000 /* Instruction does not support condition codes */ 169 170 #define ARM_SIMD_MASK0 0xFE000000 171 #define ARM_SIMD_CODE0 0xF2000000 172 173 #define ARM_VFP_MASK0 0x0F000E10 174 #define ARM_VFP_CODE0 0x0E000A00 175 176 #define ARM_SIMD_VFP_MASK0 0x0E000E00 177 #define ARM_SIMD_VFP_CODE0 0x0C000A00 178 #define ARM_SIMD_VFP_MASK1 0xFF100000 179 #define ARM_SIMD_VFP_CODE1 0xF4000000 180 #define ARM_SIMD_VFP_MASK2 0x0F000E10 181 #define ARM_SIMD_VFP_CODE2 0x0E000A10 182 #define ARM_SIMD_VFP_MASK3 0x0FE00E00 183 #define ARM_SIMD_VFP_CODE3 0x0C400A00 184 185 #define IS_ARM_VFP(op) ( \ 186 (((op) & ARM_SIMD_MASK0) == ARM_SIMD_CODE0) \ 187 ||(((op) & ARM_VFP_MASK0) == ARM_VFP_CODE0) \ 188 ||(((op) & ARM_SIMD_VFP_MASK0) == ARM_SIMD_VFP_CODE0) \ 189 ||(((op) & ARM_SIMD_VFP_MASK1) == ARM_SIMD_VFP_CODE1) \ 190 ||(((op) & ARM_SIMD_VFP_MASK2) == ARM_SIMD_VFP_CODE2) \ 191 || (((op) & ARM_SIMD_VFP_MASK3) == ARM_SIMD_VFP_CODE3)) 192 193 #define THUMB_SIMD_MASK0 0xEF000000 194 #define THUMB_SIMD_CODE0 0xEF000000 195 196 #define THUMB_VFP_MASK0 0xEF000E10 197 #define THUMB_VFP_CODE0 0xEE000A00 198 199 #define THUMB_SIMD_VFP_MASK0 0xEE000E00 200 #define THUMB_SIMD_VFP_CODE0 0xEC000A00 201 #define THUMB_SIMD_VFP_MASK1 0xFF100000 202 #define THUMB_SIMD_VFP_CODE1 0xF9000000 203 #define THUMB_SIMD_VFP_MASK2 0xEF000E10 204 #define THUMB_SIMD_VFP_CODE2 0xEE000A10 205 #define THUMB_SIMD_VFP_MASK3 0xEFE00E00 206 #define THUMB_SIMD_VFP_CODE3 0xEC400A00 207 208 #define IS_THUMB_VFP(op) ( \ 209 (((op) & THUMB_SIMD_MASK0) == THUMB_SIMD_CODE0 ) \ 210 || (((op) & THUMB_VFP_MASK0) == THUMB_VFP_CODE0 ) \ 211 || (((op) & THUMB_SIMD_VFP_MASK0) == THUMB_SIMD_VFP_CODE0 ) \ 212 || (((op) & THUMB_SIMD_VFP_MASK1) == THUMB_SIMD_VFP_CODE1 ) \ 213 || (((op) & THUMB_SIMD_VFP_MASK2) == THUMB_SIMD_VFP_CODE2 ) \ 214 || (((op) & THUMB_SIMD_VFP_MASK3) == THUMB_SIMD_VFP_CODE3)) 215 216 extern boolean_t arm_force_fast_fault(ppnum_t, vm_prot_t, int, void *); 217 extern kern_return_t arm_fast_fault(pmap_t, vm_map_address_t, vm_prot_t, bool, bool); 218 219 /* 220 * Determines if the aborted instruction is read or write operation 221 */ 222 #define arm_fault_type(op, spsr, vaddr) \ 223 (((((op)&ARM_CDX_MASK) == ARM_STC) || \ 224 (((op)&ARM_STRH_MASK) == ARM_STRH) || \ 225 (((op)&ARM_BDX_MASK) == ARM_STM) || \ 226 (((op)&ARM_SDX_MASK) == ARM_STR)) ? \ 227 (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ)) 228 229 #define thumb_fault_type(op, spsr, vaddr) \ 230 (((((op)&THUMB_STR_1_MASK) == THUMB_STMIA) || \ 231 (((op)&THUMB_STR_1_MASK) == THUMB_STR_1) || \ 232 (((op)&THUMB_STR_2_MASK) == THUMB_STR_2) || \ 233 (((op)&THUMB_STR_3_MASK) == THUMB_STR_3) || \ 234 (((op)&THUMB_STR_1_MASK) == THUMB_STRB_1) || \ 235 (((op)&THUMB_STR_2_MASK) == THUMB_STRB_2) || \ 236 (((op)&THUMB_STR_1_MASK) == THUMB_STRH_1) || \ 237 (((op)&THUMB_STR_2_MASK) == THUMB_STRH_2) || \ 238 (((op)&THUMB_PUSH_MASK) == THUMB_PUSH)) ? \ 239 (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ)) 240 241 typedef kern_return_t (*perfCallback)( 242 int trapno, 243 struct arm_saved_state *ss, 244 int, 245 int); 246 247 #endif /* _ARM_TRAP_INTERNAL_H_ */ 248