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Searched refs:msr (Results 1 – 16 of 16) sorted by relevance

/xnu-10063.141.1/osfmk/arm64/
H A Dstart.s51 msr VBAR_EL1, x0
62 msr TCR_EL1, x1
72 msr TTBR1_EL1, x0
84 msr SPSel, #0 // Back to SP0
87 msr SCTLR_EL1, x0
130 msr OSLAR_EL1, xzr
131 msr DAIFSet, #(DAIFSC_ALL) // Disable all interrupts
137 msr VBAR_EL1, x0
193 msr TPIDR_EL1, x13
321 msr TPIDR_EL0, x0
[all …]
H A Dpinst.s62 msr TTBR1_EL1, x0
66 msr VBAR_EL1, x0
70 msr TCR_EL1, x0
75 msr SCTLR_EL1, x0
114 msr SPSel, #1
H A Dmachine_routines_asm.s143 msr CPU_CFG, x13
204 msr FPSR, x1 // Write FPCR
205 msr FPCR, x2 // Write FPSR
234 msr MDSCR_EL1, x2
271 msr TTBR1_EL1, x0
289 msr TTBR0_EL1, x0
310 msr ACTLR_EL1, x0
323 msr VBAR_EL1, x0
349 msr TCR_EL1, x0
386 msr DAIFSet, #(DAIFSC_IRQF | DAIFSC_FIQF) // Disable IRQ
[all …]
H A Dcswitch.s131 msr SSBS, x$1
137 msr DIT, x$1
142 msr UAO, x$1
178 msr TPIDR_EL1, $0 // Write new thread pointer to TPIDR_EL1
183 msr TPIDR_EL0, $2
186 msr TPIDRRO_EL0, $1
190 msr CONTEXTIDR_EL1, $1 // CONTEXTIDR_EL1 (top 32-bits are RES0).
354 msr DAIFSet, #(DAIFSC_FIQF | DAIFSC_IRQF) // Disable interrupts
H A Dlocore.s139 msr TTBR0_EL1, x18
155 msr TCR_EL1, x18
356 msr SPSel, #0 // Switch to SP0
461 msr SP_EL0, x0 // Copy the user PCB pointer to SP0
463 msr SPSel, #0 // Switch to SP0
583 msr ELR_EL1, lr // Return to caller
983 msr DAIFClr, #DAIFSC_FIQF
1263 msr DAIFSet, #DAIFSC_ALL // Disable exceptions
1320 msr DAIFSet, #DAIFSC_ALL // Disable exceptions
1384 msr CPACR_EL1, x0
[all …]
H A Dmachine_routines_asm.h58 msr SPSel, #1
95 msr SPSel, #0
H A Dexception_asm.h219 msr SPSel, #1
221 msr SPSel, x19
H A Dproc_reg.h2396 msr $0, $2
2654 msr $0, $2
2666 msr $0, $2
2681 msr $0, $3
2697 msr \sreg, \scr1
H A Dcaches_asm.s95 msr CSSELR_EL1, $0 // Select appropriate cache
/xnu-10063.141.1/osfmk/arm64/sptm/
H A Dstart_sptm.s97 msr TPIDR_EL1, xzr
98 msr TPIDRRO_EL0, xzr
104 msr CPU_OVRD, x9
120 msr VBAR_EL1, x9
124 msr SPSel, #1
130 msr SPSel, #0
217 msr SPSel, #1
222 msr SPSel, #0
/xnu-10063.141.1/osfmk/i386/
H A Dproc_reg.h415 extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
416 extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
449 #define rdmsr(msr, lo, hi) \ argument
450 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
452 #define wrmsr(msr, lo, hi) \ argument
453 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
501 rdmsr64(uint32_t msr) in rdmsr64() argument
504 rdmsr(msr, lo, hi); in rdmsr64()
509 wrmsr64(uint32_t msr, uint64_t val) in wrmsr64() argument
511 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL)); in wrmsr64()
[all …]
H A Dcpuid.c988 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
989 if (0 == msr) { in cpuid_set_info()
991 msr = (1 << 16) | 1; in cpuid_set_info()
993 info_p->core_count = bitfield32((uint32_t)msr, 19, 16); in cpuid_set_info()
994 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
999 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); in cpuid_set_info() local
1000 if (0 == msr) { in cpuid_set_info()
1002 msr = (1 << 16) | 1; in cpuid_set_info()
1004 info_p->core_count = bitfield32((uint32_t)msr, 31, 16); in cpuid_set_info()
1005 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); in cpuid_set_info()
/xnu-10063.141.1/osfmk/i386/vmx/
H A Dvmx_cpu.h72 #define VMX_CAP(msr, shift, mask) (rdmsr64(msr) & ((mask) << (shift))) argument
H A Dvmx_cpu.c150 #define rdmsr_mask(msr, mask) (uint32_t)(rdmsr64(msr) & (mask)) in vmx_cpu_init() argument
409 #define CHK(msr, shift, mask) if (!VMX_CAP(msr, shift, mask)) return FALSE; in vmx_hv_support() argument
/xnu-10063.141.1/pexpert/pexpert/arm64/
H A Dapple_arm64_regs.h148 msr $2, $1
153 msr $3, $1
/xnu-10063.141.1/osfmk/kdp/ml/i386/
H A Dkdp_x86_common.c391 uint32_t msr = rq->address; in kdp_machine_msr64_read() local
397 *value = rdmsr64(msr); in kdp_machine_msr64_read()
405 uint32_t msr = rq->address; in kdp_machine_msr64_write() local
411 wrmsr64(msr, *value); in kdp_machine_msr64_write()