Home
last modified time | relevance | path

Searched refs:cpmu_reg_state (Results 1 – 2 of 2) sorted by relevance

/xnu-10002.81.5/osfmk/arm64/
H A Dperfmon_arm64.c222 struct perfmon_cpmu_regs cpmu_reg_state; variable
406 perfmon_cpmu_regs_init(&cpmu_reg_state); in perfmon_machine_configure()
421 cpmu_reg_state.pcr_pmcr0 |= 1ULL << (enable_offset + pmc); in perfmon_machine_configure()
424 cpmu_reg_state.pcr_pmcr0 |= 1ULL << (pmi_offset + pmc); in perfmon_machine_configure()
436 cpmu_reg_state.pcr_pmesr[pmesr_index] |= pmesr_bits; in perfmon_machine_configure()
438 perfmon_set_attrs(cpmu_reg_state.pcr_attr_regs, in perfmon_machine_configure()
439 ARRAYLEN(cpmu_reg_state.pcr_attr_regs), config); in perfmon_machine_configure()
444 &cpmu_reg_state); in perfmon_machine_configure()
481 perfmon_cpmu_regs_init(&cpmu_reg_state); in perfmon_machine_reset()
485 &cpmu_reg_state); in perfmon_machine_reset()
/xnu-10002.81.5/tests/
H A Dperfmon_unit_tests.c194 PRIx64, cpmu_reg_state.pcr_pmcr0, cpmu_reg_state.pcr_pmesr[0],
195 cpmu_reg_state.pcr_pmesr[1]);
198 T_EXPECT_BITS_SET(cpmu_reg_state.pcr_pmcr0,
200 T_EXPECT_BITS_SET(cpmu_reg_state.pcr_pmcr0,
205 T_EXPECT_EQ((cpmu_reg_state.pcr_pmesr[0] >> event_shift) & 0xff,