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/xnu-10002.41.9/bsd/dev/arm64/
H A Dcpu_memcmp_mask.s68 ld1.16b {v0}, [src1]
71 eor.16b v0, v0, v1
72 and.16b v0, v0, v2
73 umaxv b0, v0.16b
74 umov w0, v0.s[0]
95 ld1.16b {v0, v1}, [src1]
98 eor.16b v0, v0, v2
100 and.16b v0, v0, v4
102 orr.16b v0, v0, v1
103 umaxv b0, v0.16b
[all …]
H A Dcpu_copy_in_cksum.s111 st1.4s {v0, v1, v2, v3}, [x11], #4*16
119 eor.16b v0, v0, v0
122 mov v0.d[0], partial // move partial to 1st 64b lane in v0
156 uadalp.2d v0, v4
170 uadalp.2d v0, v16
188 uadalp.2d v0, v4
197 uadalp.2d v0, v16
207 add.2d v0, v0, v2
224 uadalp.2d v0, v2
231 uadalp.2d v0, v2
[all …]
H A Dcpu_in_cksum.s284 st1.4s {v0, v1, v2, v3}, [x11], #4*16
289 eor.16b v0, v0, v0
307 uadalp.2d v0, v4
322 uadalp.2d v0, v4
327 add.2d v0, v0, v1
329 addp.2d d0, v0
331 add.2d v0, v0, v2
335 ld1.4s {v0, v1, v2, v3}, [sp], #4*16
/xnu-10002.41.9/osfmk/arm64/
H A Dstrnlen.s97 orr.16b v0, v0, v1
108 1: uminv.16b b1, v0
130 cmhi.16b v0, v0, v1
131 orr.16b v0, v0, v2
132 uminv.16b b1, v0
165 orr.16b v0, v0, v1
177 1: uminv.16b b1, v0
195 cmhi.16b v0, v0, v1
196 orr.16b v0, v0, v2
197 uminv.16b b1, v0
H A Dstrncmp.s126 cmeq.16b v1, v0, v1
127 and.16b v0, v0, v1 // contains zero byte iff mismatch or EOS
128 uminv.16b b1, v0
167 cmeq.16b v1, v0, v1
168 and.16b v0, v0, v1 // contains zero byte iff mismatch or EOS
169 uminv.16b b1, v0
180 cmeq.16b v1, v0, v1
181 and.16b v0, v0, v1 // contains zero byte iff mismatch or EOS
182 uminv.16b b1, v0
194 cmhi.16b v0, v0, v1 // force non-zero lanes to 0xff
[all …]
H A DWKdmDecompress_4k.s136 st1.4s {v0,v1,v2},[rax],#48
191 ld1.4s {v0,v1},[rbx]
214 ushl.4s v2, v2, v0 // v1 = {0, -2, -4, -6}
215 ushl.4s v3, v3, v0 // v1 = {0, -2, -4, -6}
216 ushl.4s v4, v4, v0 // v1 = {0, -2, -4, -6}
217 ushl.4s v5, v5, v0 // v1 = {0, -2, -4, -6}
238 ld1.4s {v0,v1},[rbx]
245 ushl.4s v2, v2, v0 // v1 = {0, -4, 0, -4}
255 ushl.2s v2, v2, v0 // v1 = {0, -4}
277 ld1.4s {v0,v1,v2,v3},[rbx]
[all …]
H A DWKdmDecompress_16k.s136 st1.4s {v0,v1,v2},[rax],#48
191 ld1.4s {v0,v1},[rbx]
214 ushl.4s v2, v2, v0 // v1 = {0, -2, -4, -6}
215 ushl.4s v3, v3, v0 // v1 = {0, -2, -4, -6}
216 ushl.4s v4, v4, v0 // v1 = {0, -2, -4, -6}
217 ushl.4s v5, v5, v0 // v1 = {0, -2, -4, -6}
238 ld1.4s {v0,v1},[rbx]
245 ushl.4s v2, v2, v0 // v1 = {0, -4, 0, -4}
255 ushl.2s v2, v2, v0 // v1 = {0, -4}
277 ld1.4s {v0,v1,v2,v3},[rbx]
[all …]
H A DWKdmCompress_16k.s240 st1.4s {v0,v1,v2,v3},[sp]
353 ld1.2s {v0,v1,v2,v3},[rcx],#32
358 orr.8b v0, v0, v1
361 ushr.2d v1, v0, #30
364 orr.8b v0, v0, v1
367 zip1.2s v0, v0, v2
368 st1.2s {v0},[rdi],#8
465 ld1.4s {v0,v1,v2,v3},[sp],#64
H A DWKdmCompress_4k.s238 st1.4s {v0,v1,v2,v3},[sp]
351 ld1.2s {v0,v1,v2,v3},[rcx],#32
356 orr.8b v0, v0, v1
359 ushr.2d v1, v0, #30
362 orr.8b v0, v0, v1
365 zip1.2s v0, v0, v2
366 st1.2s {v0},[rdi],#8
463 ld1.4s {v0,v1,v2,v3},[sp],#64
H A Dmemcmp_zero.s98 orr.16b v4, v4, v0 // use orr to keep non-zero bytes
114 orr.16b v4, v4, v0 // use orr to keep non-zero bytes
123 umov w0, v0.b[0] // move byte to GPR for testing
H A Dlz4_decode_arm64.s226 tbl v0.16b,{v0.16b},v1.16b // low 16 bytes of pattern
253 tbl v0.16b,{v1.16b},v2.16b // low 16 bytes of pattern in q0
H A Dmachine_routines_asm.s1282 dup.4s v0, w2
/xnu-10002.41.9/bsd/dev/i386/
H A Dcpu_copy_in_cksum.s87 #define v0 %xmm0 macro
143 movdqa v0, 0*16(%rsp)
166 pxor v0, v0
169 movq partial, v0 // move partial to 1st 64b lane in v0
225 paddq v4, v0
246 paddq v12, v0
268 paddq v8, v0
288 paddq v12, v0
322 paddq v4, v0
339 paddq v12, v0
[all …]
/xnu-10002.41.9/bsd/dev/arm/
H A Dcpu_copy_in_cksum.s57 #define v0 q0 macro
124 vpush {v0-v3}
132 veor v0, v0, v0
156 vpadal.u16 v0, v8
166 vpadal.u16 v0, v12
180 vpadal.u16 v0, v8
188 vpadal.u16 v0, v12
198 vadd.i32 v0, v0, v2
208 vpadal.u16 v0, v8
212 vpadal.u16 v0, v10
[all …]
/xnu-10002.41.9/osfmk/arm64/corecrypto/
H A Dsha256_compress_arm64.s223 st1.4s {v0, v1, v2, v3}, [x4], #64
230 ld1.4s {v0,v1,v2,v3}, [data], #64 // w0,w1,w2,w3 need to bswap into big-endian
232 rev32.16b v0, v0 // byte swap of 1st 4 ints
243 add.4s v4, v0, v21 // 1st 4 input + K256
289 add.4s v4, v0, v21
309 rev32.16b v0, v0
313 add.4s v4, v0, v21
343 add.4s v4, v0, v21
357 add.4s v4, v0, v21
372 add.4s v4, v0, v21
[all …]