1 /*
2 * Copyright (c) 2012-2023 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 #include <arm/caches_internal.h>
30 #include <arm/cpu_data.h>
31 #include <arm/cpu_data_internal.h>
32 #include <arm/misc_protos.h>
33 #include <arm/thread.h>
34 #include <arm/rtclock.h>
35 #include <arm/trap.h> /* for IS_ARM_GDB_TRAP() et al */
36 #include <arm64/proc_reg.h>
37 #include <arm64/machine_machdep.h>
38 #include <arm64/monotonic.h>
39 #include <arm64/instructions.h>
40
41 #include <kern/debug.h>
42 #include <kern/restartable.h>
43 #include <kern/socd_client.h>
44 #include <kern/thread.h>
45 #include <kern/zalloc_internal.h>
46 #include <mach/exception.h>
47 #include <mach/arm/traps.h>
48 #include <mach/vm_types.h>
49 #include <mach/machine/thread_status.h>
50
51 #include <machine/atomic.h>
52 #include <machine/limits.h>
53
54 #include <pexpert/arm/protos.h>
55 #include <pexpert/arm64/apple_arm64_regs.h>
56 #include <pexpert/arm64/board_config.h>
57
58 #include <vm/vm_page.h>
59 #include <vm/pmap.h>
60 #include <vm/vm_fault.h>
61 #include <vm/vm_kern.h>
62
63 #include <sys/errno.h>
64 #include <sys/kdebug.h>
65 #include <kperf/kperf.h>
66
67 #include <kern/policy_internal.h>
68 #if CONFIG_TELEMETRY
69 #include <kern/telemetry.h>
70 #endif
71
72 #include <prng/entropy.h>
73
74
75
76
77 #include <arm64/platform_error_handler.h>
78
79 #if KASAN_TBI
80 #include <san/kasan.h>
81 #endif /* KASAN_TBI */
82
83 #if CONFIG_UBSAN_MINIMAL
84 #include <san/ubsan_minimal.h>
85 #endif
86
87
88 #ifndef __arm64__
89 #error Should only be compiling for arm64.
90 #endif
91
92 #if DEBUG || DEVELOPMENT
93 #define HAS_TELEMETRY_KERNEL_BRK 1
94 #endif
95
96
97 #define TEST_CONTEXT32_SANITY(context) \
98 (context->ss.ash.flavor == ARM_SAVED_STATE32 && context->ss.ash.count == ARM_SAVED_STATE32_COUNT && \
99 context->ns.nsh.flavor == ARM_NEON_SAVED_STATE32 && context->ns.nsh.count == ARM_NEON_SAVED_STATE32_COUNT)
100
101 #define TEST_CONTEXT64_SANITY(context) \
102 (context->ss.ash.flavor == ARM_SAVED_STATE64 && context->ss.ash.count == ARM_SAVED_STATE64_COUNT && \
103 context->ns.nsh.flavor == ARM_NEON_SAVED_STATE64 && context->ns.nsh.count == ARM_NEON_SAVED_STATE64_COUNT)
104
105 #define ASSERT_CONTEXT_SANITY(context) \
106 assert(TEST_CONTEXT32_SANITY(context) || TEST_CONTEXT64_SANITY(context))
107
108
109 #define COPYIN(src, dst, size) \
110 (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) ? \
111 copyin_kern(src, dst, size) : \
112 copyin(src, dst, size)
113
114 #define COPYOUT(src, dst, size) \
115 (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) ? \
116 copyout_kern(src, dst, size) : \
117 copyout(src, dst, size)
118
119 // Below is for concatenating a string param to a string literal
120 #define STR1(x) #x
121 #define STR(x) STR1(x)
122
123 #define ARM64_KDBG_CODE_KERNEL (0 << 8)
124 #define ARM64_KDBG_CODE_USER (1 << 8)
125 #define ARM64_KDBG_CODE_GUEST (2 << 8)
126
127 _Static_assert(ARM64_KDBG_CODE_GUEST <= KDBG_CODE_MAX, "arm64 KDBG trace codes out of range");
128 _Static_assert(ARM64_KDBG_CODE_GUEST <= UINT16_MAX, "arm64 KDBG trace codes out of range");
129
130 void panic_with_thread_kernel_state(const char *msg, arm_saved_state_t *ss) __abortlike;
131
132 void sleh_synchronous_sp1(arm_context_t *, uint32_t, vm_offset_t) __abortlike;
133 void sleh_synchronous(arm_context_t *, uint32_t, vm_offset_t);
134
135
136
137 void sleh_irq(arm_saved_state_t *);
138 void sleh_fiq(arm_saved_state_t *);
139 void sleh_serror(arm_context_t *context, uint32_t esr, vm_offset_t far);
140 void sleh_invalid_stack(arm_context_t *context, uint32_t esr, vm_offset_t far) __dead2;
141
142 static void sleh_interrupt_handler_prologue(arm_saved_state_t *, unsigned int type);
143 static void sleh_interrupt_handler_epilogue(void);
144
145 static void handle_svc(arm_saved_state_t *);
146 static void handle_mach_absolute_time_trap(arm_saved_state_t *);
147 static void handle_mach_continuous_time_trap(arm_saved_state_t *);
148
149 static void handle_msr_trap(arm_saved_state_t *state, uint32_t esr);
150 #if __has_feature(ptrauth_calls)
151 static void handle_pac_fail(arm_saved_state_t *state, uint32_t esr) __dead2;
152 #endif
153
154 extern kern_return_t arm_fast_fault(pmap_t, vm_map_address_t, vm_prot_t, bool, bool);
155
156 static void handle_uncategorized(arm_saved_state_t *);
157
158 static void handle_kernel_breakpoint(arm_saved_state_t *, uint32_t);
159
160 static void handle_breakpoint(arm_saved_state_t *, uint32_t) __dead2;
161
162 typedef void (*abort_inspector_t)(uint32_t, fault_status_t *, vm_prot_t *);
163 static void inspect_instruction_abort(uint32_t, fault_status_t *, vm_prot_t *);
164 static void inspect_data_abort(uint32_t, fault_status_t *, vm_prot_t *);
165
166 static int is_vm_fault(fault_status_t);
167 static int is_translation_fault(fault_status_t);
168 static int is_alignment_fault(fault_status_t);
169
170 typedef void (*abort_handler_t)(arm_saved_state_t *, uint32_t, vm_offset_t, fault_status_t, vm_prot_t, expected_fault_handler_t);
171 static void handle_user_abort(arm_saved_state_t *, uint32_t, vm_offset_t, fault_status_t, vm_prot_t, expected_fault_handler_t);
172 static void handle_kernel_abort(arm_saved_state_t *, uint32_t, vm_offset_t, fault_status_t, vm_prot_t, expected_fault_handler_t);
173
174 static void handle_pc_align(arm_saved_state_t *ss) __dead2;
175 static void handle_sp_align(arm_saved_state_t *ss) __dead2;
176 static void handle_sw_step_debug(arm_saved_state_t *ss) __dead2;
177 static void handle_wf_trap(arm_saved_state_t *ss) __dead2;
178 static void handle_fp_trap(arm_saved_state_t *ss, uint32_t esr) __dead2;
179
180 static void handle_watchpoint(vm_offset_t fault_addr) __dead2;
181
182 static void handle_abort(arm_saved_state_t *, uint32_t, vm_offset_t, abort_inspector_t, abort_handler_t, expected_fault_handler_t);
183
184 static void handle_user_trapped_instruction32(arm_saved_state_t *, uint32_t esr) __dead2;
185
186 static void handle_simd_trap(arm_saved_state_t *, uint32_t esr) __dead2;
187
188 extern void mach_kauth_cred_thread_update(void);
189 void mach_syscall_trace_exit(unsigned int retval, unsigned int call_number);
190
191 struct proc;
192
193 typedef uint32_t arm64_instr_t;
194
195 extern void
196 unix_syscall(struct arm_saved_state * regs, thread_t thread_act, struct proc * proc);
197
198 extern void
199 mach_syscall(struct arm_saved_state*);
200
201 #if CONFIG_DTRACE
202 extern kern_return_t dtrace_user_probe(arm_saved_state_t* regs);
203 extern boolean_t dtrace_tally_fault(user_addr_t);
204
205 /*
206 * Traps for userland processing. Can't include bsd/sys/fasttrap_isa.h, so copy
207 * and paste the trap instructions
208 * over from that file. Need to keep these in sync!
209 */
210 #define FASTTRAP_ARM32_INSTR 0xe7ffdefc
211 #define FASTTRAP_THUMB32_INSTR 0xdefc
212 #define FASTTRAP_ARM64_INSTR 0xe7eeee7e
213
214 #define FASTTRAP_ARM32_RET_INSTR 0xe7ffdefb
215 #define FASTTRAP_THUMB32_RET_INSTR 0xdefb
216 #define FASTTRAP_ARM64_RET_INSTR 0xe7eeee7d
217
218 /* See <rdar://problem/4613924> */
219 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
220 #endif
221
222
223
224 extern void arm64_thread_exception_return(void) __dead2;
225
226 #if defined(APPLETYPHOON)
227 #define CPU_NAME "Typhoon"
228 #elif defined(APPLETWISTER)
229 #define CPU_NAME "Twister"
230 #elif defined(APPLEHURRICANE)
231 #define CPU_NAME "Hurricane"
232 #elif defined(APPLELIGHTNING)
233 #define CPU_NAME "Lightning"
234 #else
235 #define CPU_NAME "Unknown"
236 #endif
237
238 #if (CONFIG_KERNEL_INTEGRITY && defined(KERNEL_INTEGRITY_WT))
239 #define ESR_WT_SERROR(esr) (((esr) & 0xffffff00) == 0xbf575400)
240 #define ESR_WT_REASON(esr) ((esr) & 0xff)
241
242 #define WT_REASON_NONE 0
243 #define WT_REASON_INTEGRITY_FAIL 1
244 #define WT_REASON_BAD_SYSCALL 2
245 #define WT_REASON_NOT_LOCKED 3
246 #define WT_REASON_ALREADY_LOCKED 4
247 #define WT_REASON_SW_REQ 5
248 #define WT_REASON_PT_INVALID 6
249 #define WT_REASON_PT_VIOLATION 7
250 #define WT_REASON_REG_VIOLATION 8
251 #endif
252
253 #if defined(HAS_IPI)
254 void cpu_signal_handler(void);
255 extern unsigned int gFastIPI;
256 #endif /* defined(HAS_IPI) */
257
258 static arm_saved_state64_t *original_faulting_state = NULL;
259
260
261 TUNABLE(bool, fp_exceptions_enabled, "-fp_exceptions", false);
262
263 extern vm_offset_t static_memory_end;
264
265 /*
266 * Fault copyio_recovery_entry in copyin/copyout routines.
267 *
268 * Offets are expressed in bytes from ©_recovery_table
269 */
270 struct copyio_recovery_entry {
271 ptrdiff_t cre_start;
272 ptrdiff_t cre_end;
273 ptrdiff_t cre_recovery;
274 };
275
276 extern struct copyio_recovery_entry copyio_recover_table[];
277 extern struct copyio_recovery_entry copyio_recover_table_end[];
278
279 static inline ptrdiff_t
copyio_recovery_offset(uintptr_t addr)280 copyio_recovery_offset(uintptr_t addr)
281 {
282 return (ptrdiff_t)(addr - (uintptr_t)copyio_recover_table);
283 }
284
285 #if !HAS_APPLE_PAC
286 static inline uintptr_t
copyio_recovery_addr(ptrdiff_t offset)287 copyio_recovery_addr(ptrdiff_t offset)
288 {
289 return (uintptr_t)copyio_recover_table + (uintptr_t)offset;
290 }
291 #endif
292
293 static inline struct copyio_recovery_entry *
find_copyio_recovery_entry(arm_saved_state_t * state)294 find_copyio_recovery_entry(arm_saved_state_t *state)
295 {
296 ptrdiff_t offset = copyio_recovery_offset(get_saved_state_pc(state));
297 struct copyio_recovery_entry *e;
298
299 for (e = copyio_recover_table; e < copyio_recover_table_end; e++) {
300 if (offset >= e->cre_start && offset < e->cre_end) {
301 return e;
302 }
303 }
304
305 return NULL;
306 }
307
308 static inline int
is_vm_fault(fault_status_t status)309 is_vm_fault(fault_status_t status)
310 {
311 switch (status) {
312 case FSC_TRANSLATION_FAULT_L0:
313 case FSC_TRANSLATION_FAULT_L1:
314 case FSC_TRANSLATION_FAULT_L2:
315 case FSC_TRANSLATION_FAULT_L3:
316 case FSC_ACCESS_FLAG_FAULT_L1:
317 case FSC_ACCESS_FLAG_FAULT_L2:
318 case FSC_ACCESS_FLAG_FAULT_L3:
319 case FSC_PERMISSION_FAULT_L1:
320 case FSC_PERMISSION_FAULT_L2:
321 case FSC_PERMISSION_FAULT_L3:
322 return TRUE;
323 default:
324 return FALSE;
325 }
326 }
327
328 static inline int
is_translation_fault(fault_status_t status)329 is_translation_fault(fault_status_t status)
330 {
331 switch (status) {
332 case FSC_TRANSLATION_FAULT_L0:
333 case FSC_TRANSLATION_FAULT_L1:
334 case FSC_TRANSLATION_FAULT_L2:
335 case FSC_TRANSLATION_FAULT_L3:
336 return TRUE;
337 default:
338 return FALSE;
339 }
340 }
341
342 static inline int
is_permission_fault(fault_status_t status)343 is_permission_fault(fault_status_t status)
344 {
345 switch (status) {
346 case FSC_PERMISSION_FAULT_L1:
347 case FSC_PERMISSION_FAULT_L2:
348 case FSC_PERMISSION_FAULT_L3:
349 return TRUE;
350 default:
351 return FALSE;
352 }
353 }
354
355 static inline int
is_alignment_fault(fault_status_t status)356 is_alignment_fault(fault_status_t status)
357 {
358 return status == FSC_ALIGNMENT_FAULT;
359 }
360
361 static inline int
is_parity_error(fault_status_t status)362 is_parity_error(fault_status_t status)
363 {
364 switch (status) {
365 /*
366 * TODO: According to ARM ARM, Async Parity (0b011001) is a DFSC that is
367 * only applicable to AArch32 HSR register. Can this be removed?
368 */
369 case FSC_ASYNC_PARITY:
370 case FSC_SYNC_PARITY:
371 case FSC_SYNC_PARITY_TT_L1:
372 case FSC_SYNC_PARITY_TT_L2:
373 case FSC_SYNC_PARITY_TT_L3:
374 return TRUE;
375 default:
376 return FALSE;
377 }
378 }
379
380
381
382 __dead2 __unused
383 static void
arm64_implementation_specific_error(arm_saved_state_t * state,uint32_t esr,vm_offset_t far)384 arm64_implementation_specific_error(arm_saved_state_t *state, uint32_t esr, vm_offset_t far)
385 {
386 #pragma unused (state, esr, far)
387 panic_plain("Unhandled implementation specific error\n");
388 }
389
390 #if CONFIG_KERNEL_INTEGRITY
391 #pragma clang diagnostic push
392 #pragma clang diagnostic ignored "-Wunused-parameter"
393 static void
kernel_integrity_error_handler(uint32_t esr,vm_offset_t far)394 kernel_integrity_error_handler(uint32_t esr, vm_offset_t far)
395 {
396 #if defined(KERNEL_INTEGRITY_WT)
397 #if (DEVELOPMENT || DEBUG)
398 if (ESR_WT_SERROR(esr)) {
399 switch (ESR_WT_REASON(esr)) {
400 case WT_REASON_INTEGRITY_FAIL:
401 panic_plain("Kernel integrity, violation in frame 0x%016lx.", far);
402 case WT_REASON_BAD_SYSCALL:
403 panic_plain("Kernel integrity, bad syscall.");
404 case WT_REASON_NOT_LOCKED:
405 panic_plain("Kernel integrity, not locked.");
406 case WT_REASON_ALREADY_LOCKED:
407 panic_plain("Kernel integrity, already locked.");
408 case WT_REASON_SW_REQ:
409 panic_plain("Kernel integrity, software request.");
410 case WT_REASON_PT_INVALID:
411 panic_plain("Kernel integrity, encountered invalid TTE/PTE while "
412 "walking 0x%016lx.", far);
413 case WT_REASON_PT_VIOLATION:
414 panic_plain("Kernel integrity, violation in mapping 0x%016lx.",
415 far);
416 case WT_REASON_REG_VIOLATION:
417 panic_plain("Kernel integrity, violation in system register %d.",
418 (unsigned) far);
419 default:
420 panic_plain("Kernel integrity, unknown (esr=0x%08x).", esr);
421 }
422 }
423 #else
424 if (ESR_WT_SERROR(esr)) {
425 panic_plain("SError esr: 0x%08x far: 0x%016lx.", esr, far);
426 }
427 #endif
428 #endif
429 }
430 #pragma clang diagnostic pop
431 #endif
432
433 static void
arm64_platform_error(arm_saved_state_t * state,uint32_t esr,vm_offset_t far,platform_error_source_t source)434 arm64_platform_error(arm_saved_state_t *state, uint32_t esr, vm_offset_t far, platform_error_source_t source)
435 {
436 #if CONFIG_KERNEL_INTEGRITY
437 kernel_integrity_error_handler(esr, far);
438 #endif
439
440 (void)source;
441 cpu_data_t *cdp = getCpuDatap();
442
443 if (PE_handle_platform_error(far)) {
444 return;
445 } else if (cdp->platform_error_handler != NULL) {
446 cdp->platform_error_handler(cdp->cpu_id, far);
447 } else {
448 arm64_implementation_specific_error(state, esr, far);
449 }
450 }
451
452 void
panic_with_thread_kernel_state(const char * msg,arm_saved_state_t * ss)453 panic_with_thread_kernel_state(const char *msg, arm_saved_state_t *ss)
454 {
455 boolean_t ss_valid;
456
457 ss_valid = is_saved_state64(ss);
458 arm_saved_state64_t *state = saved_state64(ss);
459
460 os_atomic_cmpxchg(&original_faulting_state, NULL, state, seq_cst);
461
462 // rdar://80659177
463 // Read SoCD tracepoints up to twice — once the first time we call panic and
464 // another time if we encounter a nested panic after that.
465 static int twice = 2;
466 if (twice > 0) {
467 twice--;
468 SOCD_TRACE_XNU(KERNEL_STATE_PANIC, ADDR(state->pc),
469 PACK_LSB(VALUE(state->lr), VALUE(ss_valid)),
470 PACK_2X32(VALUE(state->esr), VALUE(state->cpsr)),
471 VALUE(state->far));
472 }
473
474
475 panic_plain("%s at pc 0x%016llx, lr 0x%016llx (saved state: %p%s)\n"
476 "\t x0: 0x%016llx x1: 0x%016llx x2: 0x%016llx x3: 0x%016llx\n"
477 "\t x4: 0x%016llx x5: 0x%016llx x6: 0x%016llx x7: 0x%016llx\n"
478 "\t x8: 0x%016llx x9: 0x%016llx x10: 0x%016llx x11: 0x%016llx\n"
479 "\t x12: 0x%016llx x13: 0x%016llx x14: 0x%016llx x15: 0x%016llx\n"
480 "\t x16: 0x%016llx x17: 0x%016llx x18: 0x%016llx x19: 0x%016llx\n"
481 "\t x20: 0x%016llx x21: 0x%016llx x22: 0x%016llx x23: 0x%016llx\n"
482 "\t x24: 0x%016llx x25: 0x%016llx x26: 0x%016llx x27: 0x%016llx\n"
483 "\t x28: 0x%016llx fp: 0x%016llx lr: 0x%016llx sp: 0x%016llx\n"
484 "\t pc: 0x%016llx cpsr: 0x%08x esr: 0x%08x far: 0x%016llx\n",
485 msg, state->pc, state->lr, ss, (ss_valid ? "" : " INVALID"),
486 state->x[0], state->x[1], state->x[2], state->x[3],
487 state->x[4], state->x[5], state->x[6], state->x[7],
488 state->x[8], state->x[9], state->x[10], state->x[11],
489 state->x[12], state->x[13], state->x[14], state->x[15],
490 state->x[16], state->x[17], state->x[18], state->x[19],
491 state->x[20], state->x[21], state->x[22], state->x[23],
492 state->x[24], state->x[25], state->x[26], state->x[27],
493 state->x[28], state->fp, state->lr, state->sp,
494 state->pc, state->cpsr, state->esr, state->far);
495 }
496
497 void
sleh_synchronous_sp1(arm_context_t * context,uint32_t esr,vm_offset_t far __unused)498 sleh_synchronous_sp1(arm_context_t *context, uint32_t esr, vm_offset_t far __unused)
499 {
500 esr_exception_class_t class = ESR_EC(esr);
501 arm_saved_state_t * state = &context->ss;
502
503 switch (class) {
504 case ESR_EC_UNCATEGORIZED:
505 {
506 uint32_t instr = *((uint32_t*)get_saved_state_pc(state));
507 if (IS_ARM_GDB_TRAP(instr)) {
508 DebuggerCall(EXC_BREAKPOINT, state);
509 }
510 }
511 OS_FALLTHROUGH; // panic if we return from the debugger
512 default:
513 panic_with_thread_kernel_state("Synchronous exception taken while SP1 selected", state);
514 }
515 }
516
517
518 __attribute__((noreturn))
519 void
thread_exception_return()520 thread_exception_return()
521 {
522 thread_t thread = current_thread();
523 if (thread->machine.exception_trace_code != 0) {
524 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
525 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, thread->machine.exception_trace_code) | DBG_FUNC_END, 0, 0, 0, 0, 0);
526 thread->machine.exception_trace_code = 0;
527 }
528
529 #if KASAN_TBI
530 kasan_unpoison_curstack(true);
531 #endif /* KASAN_TBI */
532 arm64_thread_exception_return();
533 __builtin_unreachable();
534 }
535
536 /*
537 * check whether task vtimers are running and set thread and CPU BSD AST
538 *
539 * must be called with interrupts masked so updates of fields are atomic
540 * must be emitted inline to avoid generating an FBT probe on the exception path
541 *
542 */
543 __attribute__((__always_inline__))
544 static inline void
task_vtimer_check(thread_t thread)545 task_vtimer_check(thread_t thread)
546 {
547 task_t task = get_threadtask_early(thread);
548
549 if (__improbable(task != NULL && task->vtimers)) {
550 thread_ast_set(thread, AST_BSD);
551 thread->machine.CpuDatap->cpu_pending_ast |= AST_BSD;
552 }
553 }
554
555 #if MACH_ASSERT
556 /**
557 * A version of get_preemption_level() that works in early boot.
558 *
559 * If an exception is raised in early boot before the initial thread has been
560 * set up, then calling get_preemption_level() in the SLEH will trigger an
561 * infinitely-recursing exception. This function handles this edge case.
562 */
563 static inline int
sleh_get_preemption_level(void)564 sleh_get_preemption_level(void)
565 {
566 if (__improbable(current_thread() == NULL)) {
567 return 0;
568 }
569 return get_preemption_level();
570 }
571 #endif // MACH_ASSERT
572
573 static inline bool
is_platform_error(uint32_t esr)574 is_platform_error(uint32_t esr)
575 {
576 esr_exception_class_t class = ESR_EC(esr);
577 uint32_t iss = ESR_ISS(esr);
578 fault_status_t fault_code;
579
580 if (class == ESR_EC_DABORT_EL0 || class == ESR_EC_DABORT_EL1) {
581 fault_code = ISS_DA_FSC(iss);
582 } else if (class == ESR_EC_IABORT_EL0 || class == ESR_EC_IABORT_EL1) {
583 fault_code = ISS_IA_FSC(iss);
584 } else {
585 return false;
586 }
587
588 return fault_code == FSC_SYNC_PARITY;
589 }
590
591 void
sleh_synchronous(arm_context_t * context,uint32_t esr,vm_offset_t far)592 sleh_synchronous(arm_context_t *context, uint32_t esr, vm_offset_t far)
593 {
594 esr_exception_class_t class = ESR_EC(esr);
595 arm_saved_state_t * state = &context->ss;
596 thread_t thread = current_thread();
597 #if MACH_ASSERT
598 int preemption_level = sleh_get_preemption_level();
599 #endif
600 expected_fault_handler_t expected_fault_handler = NULL;
601 #ifdef CONFIG_XNUPOST
602 expected_fault_handler_t saved_expected_fault_handler = NULL;
603 uintptr_t saved_expected_fault_addr = 0;
604 #endif /* CONFIG_XNUPOST */
605
606 ASSERT_CONTEXT_SANITY(context);
607
608 task_vtimer_check(thread);
609
610 #if CONFIG_DTRACE
611 /*
612 * Handle kernel DTrace probes as early as possible to minimize the likelihood
613 * that this path will itself trigger a DTrace probe, which would lead to infinite
614 * probe recursion.
615 */
616 if (__improbable((class == ESR_EC_UNCATEGORIZED) && tempDTraceTrapHook &&
617 (tempDTraceTrapHook(EXC_BAD_INSTRUCTION, state, 0, 0) == KERN_SUCCESS))) {
618 return;
619 }
620 #endif
621 bool is_user = PSR64_IS_USER(get_saved_state_cpsr(state));
622
623 /*
624 * Use KERNEL_DEBUG_CONSTANT_IST here to avoid producing tracepoints
625 * that would disclose the behavior of PT_DENY_ATTACH processes.
626 */
627 if (is_user) {
628 /* Sanitize FAR (but only if the exception was taken from userspace) */
629 switch (class) {
630 case ESR_EC_IABORT_EL1:
631 case ESR_EC_IABORT_EL0:
632 /* If this is a SEA, since we can't trust FnV, just clear FAR from the save area. */
633 if (ISS_IA_FSC(ESR_ISS(esr)) == FSC_SYNC_EXT_ABORT) {
634 saved_state64(state)->far = 0;
635 }
636 break;
637 case ESR_EC_DABORT_EL1:
638 case ESR_EC_DABORT_EL0:
639 /* If this is a SEA, since we can't trust FnV, just clear FAR from the save area. */
640 if (ISS_DA_FSC(ESR_ISS(esr)) == FSC_SYNC_EXT_ABORT) {
641 saved_state64(state)->far = 0;
642 }
643 break;
644 case ESR_EC_WATCHPT_MATCH_EL1:
645 case ESR_EC_WATCHPT_MATCH_EL0:
646 case ESR_EC_PC_ALIGN:
647 break; /* FAR_ELx is valid */
648 default:
649 saved_state64(state)->far = 0;
650 break;
651 }
652
653 thread->machine.exception_trace_code = (uint16_t)(ARM64_KDBG_CODE_USER | class);
654 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
655 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, thread->machine.exception_trace_code) | DBG_FUNC_START,
656 esr, far, get_saved_state_pc(state), 0, 0);
657 } else {
658 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
659 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, ARM64_KDBG_CODE_KERNEL | class) | DBG_FUNC_START,
660 esr, VM_KERNEL_ADDRHIDE(far), VM_KERNEL_UNSLIDE(get_saved_state_pc(state)), 0, 0);
661 }
662
663 if (__improbable(ESR_INSTR_IS_2BYTES(esr))) {
664 /*
665 * We no longer support 32-bit, which means no 2-byte
666 * instructions.
667 */
668 if (is_user) {
669 panic("Exception on 2-byte instruction, "
670 "context=%p, esr=%#x, far=%p",
671 context, esr, (void *)far);
672 } else {
673 panic_with_thread_kernel_state("Exception on 2-byte instruction", state);
674 }
675 }
676
677 #ifdef CONFIG_XNUPOST
678 if (thread->machine.expected_fault_handler != NULL) {
679 saved_expected_fault_handler = thread->machine.expected_fault_handler;
680 saved_expected_fault_addr = thread->machine.expected_fault_addr;
681
682 thread->machine.expected_fault_handler = NULL;
683 thread->machine.expected_fault_addr = 0;
684
685 if (saved_expected_fault_addr == far) {
686 expected_fault_handler = saved_expected_fault_handler;
687 }
688 }
689 #endif /* CONFIG_XNUPOST */
690
691 if (__improbable(is_platform_error(esr))) {
692 /*
693 * Must gather error info in platform error handler before
694 * thread is preempted to another core/cluster to guarantee
695 * accurate error details
696 */
697
698 arm64_platform_error(state, esr, far, PLAT_ERR_SRC_SYNC);
699 return;
700 }
701
702 if (is_user && class == ESR_EC_DABORT_EL0) {
703 thread_reset_pcs_will_fault(thread);
704 }
705
706 /* Inherit the interrupt masks from previous context */
707 if (SPSR_INTERRUPTS_ENABLED(get_saved_state_cpsr(state))) {
708 ml_set_interrupts_enabled(TRUE);
709 }
710
711 switch (class) {
712 case ESR_EC_SVC_64:
713 if (!is_saved_state64(state) || !is_user) {
714 panic("Invalid SVC_64 context");
715 }
716
717 handle_svc(state);
718 break;
719
720 case ESR_EC_DABORT_EL0:
721 handle_abort(state, esr, far, inspect_data_abort, handle_user_abort, expected_fault_handler);
722 break;
723
724 case ESR_EC_MSR_TRAP:
725 handle_msr_trap(state, esr);
726 break;
727 /**
728 * Some APPLEVIRTUALPLATFORM targets do not specify armv8.6, but it's still possible for
729 * them to be hosted by a host that implements ARM_FPAC. There's no way for such a host
730 * to disable it or trap it without substantial performance penalty. Therefore, the FPAC
731 * handler here needs to be built into the guest kernels to prevent the exception to fall
732 * through.
733 */
734 #if __has_feature(ptrauth_calls)
735 case ESR_EC_PAC_FAIL:
736 handle_pac_fail(state, esr);
737 __builtin_unreachable();
738
739 #endif /* __has_feature(ptrauth_calls) */
740
741
742 case ESR_EC_IABORT_EL0:
743 handle_abort(state, esr, far, inspect_instruction_abort, handle_user_abort, expected_fault_handler);
744 break;
745
746 case ESR_EC_IABORT_EL1:
747 #ifdef CONFIG_XNUPOST
748 if ((expected_fault_handler != NULL) && expected_fault_handler(state)) {
749 break;
750 }
751 #endif /* CONFIG_XNUPOST */
752
753 panic_with_thread_kernel_state("Kernel instruction fetch abort", state);
754
755 case ESR_EC_PC_ALIGN:
756 handle_pc_align(state);
757 __builtin_unreachable();
758
759 case ESR_EC_DABORT_EL1:
760 handle_abort(state, esr, far, inspect_data_abort, handle_kernel_abort, expected_fault_handler);
761 break;
762
763 case ESR_EC_UNCATEGORIZED:
764 assert(!ESR_ISS(esr));
765
766 handle_uncategorized(&context->ss);
767 break;
768
769 case ESR_EC_SP_ALIGN:
770 handle_sp_align(state);
771 __builtin_unreachable();
772
773 case ESR_EC_BKPT_AARCH32:
774 handle_breakpoint(state, esr);
775 __builtin_unreachable();
776
777 case ESR_EC_BRK_AARCH64:
778 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
779 handle_kernel_breakpoint(state, esr);
780 break;
781 } else {
782 handle_breakpoint(state, esr);
783 __builtin_unreachable();
784 }
785
786 case ESR_EC_BKPT_REG_MATCH_EL0:
787 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
788 handle_breakpoint(state, esr);
789 }
790 panic("Unsupported Class %u event code. state=%p class=%u esr=%u far=%p",
791 class, state, class, esr, (void *)far);
792 __builtin_unreachable();
793
794 case ESR_EC_BKPT_REG_MATCH_EL1:
795 panic_with_thread_kernel_state("Hardware Breakpoint Debug exception from kernel. Panic (by design)", state);
796 __builtin_unreachable();
797
798 case ESR_EC_SW_STEP_DEBUG_EL0:
799 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
800 handle_sw_step_debug(state);
801 }
802 panic("Unsupported Class %u event code. state=%p class=%u esr=%u far=%p",
803 class, state, class, esr, (void *)far);
804 __builtin_unreachable();
805
806 case ESR_EC_SW_STEP_DEBUG_EL1:
807 panic_with_thread_kernel_state("Software Step Debug exception from kernel. Panic (by design)", state);
808 __builtin_unreachable();
809
810 case ESR_EC_WATCHPT_MATCH_EL0:
811 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
812 handle_watchpoint(far);
813 }
814 panic("Unsupported Class %u event code. state=%p class=%u esr=%u far=%p",
815 class, state, class, esr, (void *)far);
816 __builtin_unreachable();
817
818 case ESR_EC_WATCHPT_MATCH_EL1:
819 /*
820 * If we hit a watchpoint in kernel mode, probably in a copyin/copyout which we don't want to
821 * abort. Turn off watchpoints and keep going; we'll turn them back on in return_from_exception..
822 */
823 if (FSC_DEBUG_FAULT == ISS_SSDE_FSC(esr)) {
824 arm_debug_set(NULL);
825 break; /* return to first level handler */
826 }
827 panic("Unsupported Class %u event code. state=%p class=%u esr=%u far=%p",
828 class, state, class, esr, (void *)far);
829 __builtin_unreachable();
830
831 case ESR_EC_TRAP_SIMD_FP:
832 handle_simd_trap(state, esr);
833 __builtin_unreachable();
834
835 case ESR_EC_ILLEGAL_INSTR_SET:
836 panic("Illegal instruction set exception. state=%p class=%u esr=%u far=%p spsr=0x%x",
837 state, class, esr, (void *)far, get_saved_state_cpsr(state));
838 __builtin_unreachable();
839
840 case ESR_EC_MCR_MRC_CP15_TRAP:
841 case ESR_EC_MCRR_MRRC_CP15_TRAP:
842 case ESR_EC_MCR_MRC_CP14_TRAP:
843 case ESR_EC_LDC_STC_CP14_TRAP:
844 case ESR_EC_MCRR_MRRC_CP14_TRAP:
845 handle_user_trapped_instruction32(state, esr);
846 __builtin_unreachable();
847
848 case ESR_EC_WFI_WFE:
849 // Use of WFI or WFE instruction when they have been disabled for EL0
850 handle_wf_trap(state);
851 __builtin_unreachable();
852
853 case ESR_EC_FLOATING_POINT_64:
854 handle_fp_trap(state, esr);
855 __builtin_unreachable();
856
857 default:
858 handle_uncategorized(state);
859 }
860
861 #ifdef CONFIG_XNUPOST
862 if (saved_expected_fault_handler != NULL) {
863 thread->machine.expected_fault_handler = saved_expected_fault_handler;
864 thread->machine.expected_fault_addr = saved_expected_fault_addr;
865 }
866 #endif /* CONFIG_XNUPOST */
867
868 if (is_user) {
869 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
870 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, thread->machine.exception_trace_code) | DBG_FUNC_END,
871 esr, far, get_saved_state_pc(state), 0, 0);
872 thread->machine.exception_trace_code = 0;
873 } else {
874 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
875 MACHDBG_CODE(DBG_MACH_EXCP_SYNC_ARM, ARM64_KDBG_CODE_KERNEL | class) | DBG_FUNC_END,
876 esr, VM_KERNEL_ADDRHIDE(far), VM_KERNEL_UNSLIDE(get_saved_state_pc(state)), 0, 0);
877 }
878 #if MACH_ASSERT
879 if (preemption_level != sleh_get_preemption_level()) {
880 panic("synchronous exception changed preemption level from %d to %d", preemption_level, sleh_get_preemption_level());
881 }
882 #endif
883 }
884
885 /*
886 * Uncategorized exceptions are a catch-all for general execution errors.
887 * ARM64_TODO: For now, we assume this is for undefined instruction exceptions.
888 */
889 static void
handle_uncategorized(arm_saved_state_t * state)890 handle_uncategorized(arm_saved_state_t *state)
891 {
892 exception_type_t exception = EXC_BAD_INSTRUCTION;
893 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
894 mach_msg_type_number_t numcodes = 2;
895 uint32_t instr = 0;
896
897 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
898
899 #if CONFIG_DTRACE
900
901 if (PSR64_IS_USER64(get_saved_state_cpsr(state))) {
902 /*
903 * For a 64bit user process, we care about all 4 bytes of the
904 * instr.
905 */
906 if (instr == FASTTRAP_ARM64_INSTR || instr == FASTTRAP_ARM64_RET_INSTR) {
907 if (dtrace_user_probe(state) == KERN_SUCCESS) {
908 return;
909 }
910 }
911 } else if (PSR64_IS_USER32(get_saved_state_cpsr(state))) {
912 /*
913 * For a 32bit user process, we check for thumb mode, in
914 * which case we only care about a 2 byte instruction length.
915 * For non-thumb mode, we care about all 4 bytes of the instructin.
916 */
917 if (get_saved_state_cpsr(state) & PSR64_MODE_USER32_THUMB) {
918 if (((uint16_t)instr == FASTTRAP_THUMB32_INSTR) ||
919 ((uint16_t)instr == FASTTRAP_THUMB32_RET_INSTR)) {
920 if (dtrace_user_probe(state) == KERN_SUCCESS) {
921 return;
922 }
923 }
924 } else {
925 if ((instr == FASTTRAP_ARM32_INSTR) ||
926 (instr == FASTTRAP_ARM32_RET_INSTR)) {
927 if (dtrace_user_probe(state) == KERN_SUCCESS) {
928 return;
929 }
930 }
931 }
932 }
933
934 #endif /* CONFIG_DTRACE */
935
936 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
937 if (IS_ARM_GDB_TRAP(instr)) {
938 boolean_t interrupt_state;
939 exception = EXC_BREAKPOINT;
940
941 interrupt_state = ml_set_interrupts_enabled(FALSE);
942
943 /* Save off the context here (so that the debug logic
944 * can see the original state of this thread).
945 */
946 current_thread()->machine.kpcb = state;
947
948 /* Hop into the debugger (typically either due to a
949 * fatal exception, an explicit panic, or a stackshot
950 * request.
951 */
952 DebuggerCall(exception, state);
953
954 current_thread()->machine.kpcb = NULL;
955 (void) ml_set_interrupts_enabled(interrupt_state);
956 return;
957 } else {
958 panic("Undefined kernel instruction: pc=%p instr=%x", (void*)get_saved_state_pc(state), instr);
959 }
960 }
961
962 /*
963 * Check for GDB breakpoint via illegal opcode.
964 */
965 if (IS_ARM_GDB_TRAP(instr)) {
966 exception = EXC_BREAKPOINT;
967 codes[0] = EXC_ARM_BREAKPOINT;
968 codes[1] = instr;
969 } else {
970 codes[1] = instr;
971 }
972
973 exception_triage(exception, codes, numcodes);
974 __builtin_unreachable();
975 }
976
977 #if __has_feature(ptrauth_calls)
978 static const uint16_t PTRAUTH_TRAPS_START = 0xC470;
979 static inline bool
brk_comment_is_ptrauth(uint16_t comment)980 brk_comment_is_ptrauth(uint16_t comment)
981 {
982 return comment >= PTRAUTH_TRAPS_START &&
983 comment <= PTRAUTH_TRAPS_START + ptrauth_key_asdb;
984 }
985
986 static inline const char *
ptrauth_key_to_string(ptrauth_key key)987 ptrauth_key_to_string(ptrauth_key key)
988 {
989 switch (key) {
990 case ptrauth_key_asia:
991 return "IA";
992 case ptrauth_key_asib:
993 return "IB";
994 case ptrauth_key_asda:
995 return "DA";
996 case ptrauth_key_asdb:
997 return "DB";
998 default:
999 __builtin_unreachable();
1000 }
1001 }
1002
1003 static void __attribute__((noreturn))
ptrauth_handle_brk_trap(void * tstate,uint16_t comment)1004 ptrauth_handle_brk_trap(void *tstate, uint16_t comment)
1005 {
1006 arm_saved_state_t *state = (arm_saved_state_t *)tstate;
1007 #define MSG_FMT "Break 0x%04X instruction exception from kernel. Ptrauth failure with %s key resulted in 0x%016llx"
1008 char msg[strlen(MSG_FMT)
1009 - strlen("0x%04X") + strlen("0xFFFF")
1010 - strlen("%s") + strlen("IA")
1011 - strlen("0x%016llx") + strlen("0xFFFFFFFFFFFFFFFF")
1012 + 1];
1013 ptrauth_key key = (ptrauth_key)(comment - PTRAUTH_TRAPS_START);
1014 const char *key_str = ptrauth_key_to_string(key);
1015 snprintf(msg, sizeof(msg), MSG_FMT, comment, key_str, saved_state64(state)->x[16]);
1016 #undef MSG_FMT
1017
1018 panic_with_thread_kernel_state(msg, state);
1019 __builtin_unreachable();
1020 }
1021 #endif /* __has_feature(ptrauth_calls) */
1022
1023 #if HAS_TELEMETRY_KERNEL_BRK
1024 static uint32_t bound_chk_violations_event;
1025
1026 static void
telemetry_handle_brk_trap(void * tstate,uint16_t comment)1027 telemetry_handle_brk_trap(
1028 void *tstate,
1029 uint16_t comment)
1030 {
1031 #if CONFIG_UBSAN_MINIMAL
1032 if (comment == UBSAN_SIGNED_OVERFLOW_TRAP) {
1033 ubsan_handle_brk_trap(tstate, comment);
1034 }
1035 #else
1036 (void)tstate;
1037 #endif
1038
1039 if (comment == CLANG_BOUND_CHK_SOFT_TRAP) {
1040 os_atomic_inc(&bound_chk_violations_event, relaxed);
1041 }
1042 }
1043 #endif /* HAS_TELEMETRY_KERNEL_BRK */
1044
1045 #if __has_feature(ptrauth_calls)
1046 KERNEL_BRK_DESCRIPTOR_DEFINE(ptrauth_desc,
1047 .type = KERNEL_BRK_TYPE_PTRAUTH,
1048 .base = PTRAUTH_TRAPS_START,
1049 .max = PTRAUTH_TRAPS_START + ptrauth_key_asdb,
1050 .options = KERNEL_BRK_UNRECOVERABLE,
1051 .handle_breakpoint = ptrauth_handle_brk_trap);
1052 #endif
1053
1054 KERNEL_BRK_DESCRIPTOR_DEFINE(clang_desc,
1055 .type = KERNEL_BRK_TYPE_CLANG,
1056 .base = CLANG_TRAPS_ARM_START,
1057 .max = CLANG_TRAPS_ARM_END,
1058 .options = KERNEL_BRK_UNRECOVERABLE,
1059 .handle_breakpoint = NULL);
1060
1061 KERNEL_BRK_DESCRIPTOR_DEFINE(libcxx_desc,
1062 .type = KERNEL_BRK_TYPE_LIBCXX,
1063 .base = LIBCXX_TRAPS_START,
1064 .max = LIBCXX_TRAPS_END,
1065 .options = KERNEL_BRK_UNRECOVERABLE,
1066 .handle_breakpoint = NULL);
1067
1068 #if HAS_TELEMETRY_KERNEL_BRK
1069 KERNEL_BRK_DESCRIPTOR_DEFINE(telemetry_desc,
1070 .type = KERNEL_BRK_TYPE_TELEMETRY,
1071 .base = TELEMETRY_TRAPS_START,
1072 .max = TELEMETRY_TRAPS_END,
1073 .options = KERNEL_BRK_RECOVERABLE | KERNEL_BRK_CORE_ANALYTICS,
1074 .handle_breakpoint = telemetry_handle_brk_trap);
1075 #endif /* HAS_TELEMETRY_KERNEL_BRK */
1076
1077 static void
1078 #if !HAS_TELEMETRY_KERNEL_BRK
1079 __attribute__((noreturn))
1080 #endif
handle_kernel_breakpoint(arm_saved_state_t * state,uint32_t esr)1081 handle_kernel_breakpoint(arm_saved_state_t *state, uint32_t esr)
1082 {
1083 uint16_t comment = ISS_BRK_COMMENT(esr);
1084 const struct kernel_brk_descriptor *desc;
1085
1086 #define MSG_FMT "Break 0x%04X instruction exception from kernel. Panic (by design)"
1087 char msg[strlen(MSG_FMT) - strlen("0x%04X") + strlen("0xFFFF") + 1];
1088
1089 desc = find_brk_descriptor_by_comment(comment);
1090
1091 if (!desc) {
1092 goto brk_out;
1093 }
1094
1095 #if HAS_TELEMETRY_KERNEL_BRK
1096 if (desc->options & KERNEL_BRK_TELEMETRY_OPTIONS) {
1097 telemetry_kernel_brk(desc->type, desc->options, (void *)state, comment);
1098 }
1099 #endif
1100
1101 if (desc->handle_breakpoint) {
1102 desc->handle_breakpoint(state, comment); /* May trigger panic */
1103 }
1104
1105 #if HAS_TELEMETRY_KERNEL_BRK
1106 /* Still alive? Check if we should recover. */
1107 if (desc->options & KERNEL_BRK_RECOVERABLE) {
1108 add_saved_state_pc(state, 4);
1109 return;
1110 }
1111 #endif
1112
1113 brk_out:
1114 snprintf(msg, sizeof(msg), MSG_FMT, comment);
1115
1116 panic_with_thread_kernel_state(msg, state);
1117 __builtin_unreachable();
1118 #undef MSG_FMT
1119 }
1120
1121 static void
handle_breakpoint(arm_saved_state_t * state,uint32_t esr __unused)1122 handle_breakpoint(arm_saved_state_t *state, uint32_t esr __unused)
1123 {
1124 exception_type_t exception = EXC_BREAKPOINT;
1125 mach_exception_data_type_t codes[2] = {EXC_ARM_BREAKPOINT};
1126 mach_msg_type_number_t numcodes = 2;
1127
1128 #if __has_feature(ptrauth_calls)
1129 if (ESR_EC(esr) == ESR_EC_BRK_AARCH64 &&
1130 brk_comment_is_ptrauth(ISS_BRK_COMMENT(esr))) {
1131 exception |= EXC_PTRAUTH_BIT;
1132 }
1133 #endif /* __has_feature(ptrauth_calls) */
1134
1135 codes[1] = get_saved_state_pc(state);
1136 exception_triage(exception, codes, numcodes);
1137 __builtin_unreachable();
1138 }
1139
1140 static void
handle_watchpoint(vm_offset_t fault_addr)1141 handle_watchpoint(vm_offset_t fault_addr)
1142 {
1143 exception_type_t exception = EXC_BREAKPOINT;
1144 mach_exception_data_type_t codes[2] = {EXC_ARM_DA_DEBUG};
1145 mach_msg_type_number_t numcodes = 2;
1146
1147 codes[1] = fault_addr;
1148 exception_triage(exception, codes, numcodes);
1149 __builtin_unreachable();
1150 }
1151
1152 static void
handle_abort(arm_saved_state_t * state,uint32_t esr,vm_offset_t fault_addr,abort_inspector_t inspect_abort,abort_handler_t handler,expected_fault_handler_t expected_fault_handler)1153 handle_abort(arm_saved_state_t *state, uint32_t esr, vm_offset_t fault_addr,
1154 abort_inspector_t inspect_abort, abort_handler_t handler, expected_fault_handler_t expected_fault_handler)
1155 {
1156 fault_status_t fault_code;
1157 vm_prot_t fault_type;
1158
1159 inspect_abort(ESR_ISS(esr), &fault_code, &fault_type);
1160 handler(state, esr, fault_addr, fault_code, fault_type, expected_fault_handler);
1161 }
1162
1163 static void
inspect_instruction_abort(uint32_t iss,fault_status_t * fault_code,vm_prot_t * fault_type)1164 inspect_instruction_abort(uint32_t iss, fault_status_t *fault_code, vm_prot_t *fault_type)
1165 {
1166 getCpuDatap()->cpu_stat.instr_ex_cnt++;
1167 *fault_code = ISS_IA_FSC(iss);
1168 *fault_type = (VM_PROT_READ | VM_PROT_EXECUTE);
1169 }
1170
1171 static void
inspect_data_abort(uint32_t iss,fault_status_t * fault_code,vm_prot_t * fault_type)1172 inspect_data_abort(uint32_t iss, fault_status_t *fault_code, vm_prot_t *fault_type)
1173 {
1174 getCpuDatap()->cpu_stat.data_ex_cnt++;
1175 *fault_code = ISS_DA_FSC(iss);
1176
1177 /*
1178 * Cache maintenance operations always report faults as write access.
1179 * Change these to read access, unless they report a permission fault.
1180 * Only certain cache maintenance operations (e.g. 'dc ivac') require write
1181 * access to the mapping, but if a cache maintenance operation that only requires
1182 * read access generates a permission fault, then we will not be able to handle
1183 * the fault regardless of whether we treat it as a read or write fault.
1184 */
1185 if ((iss & ISS_DA_WNR) && (!(iss & ISS_DA_CM) || is_permission_fault(*fault_code))) {
1186 *fault_type = (VM_PROT_READ | VM_PROT_WRITE);
1187 } else {
1188 *fault_type = (VM_PROT_READ);
1189 }
1190 }
1191
1192 #if __has_feature(ptrauth_calls)
1193 static inline uint64_t
fault_addr_bitmask(unsigned int bit_from,unsigned int bit_to)1194 fault_addr_bitmask(unsigned int bit_from, unsigned int bit_to)
1195 {
1196 return ((1ULL << (bit_to - bit_from + 1)) - 1) << bit_from;
1197 }
1198
1199 static inline bool
fault_addr_bit(vm_offset_t fault_addr,unsigned int bit)1200 fault_addr_bit(vm_offset_t fault_addr, unsigned int bit)
1201 {
1202 return (bool)((fault_addr >> bit) & 1);
1203 }
1204
1205 extern int gARM_FEAT_PAuth2;
1206
1207 /**
1208 * Determines whether a fault address taken at EL0 contains a PAC error code
1209 * corresponding to the specified kind of ptrauth key.
1210 */
1211 static bool
user_fault_addr_matches_pac_error_code(vm_offset_t fault_addr,bool data_key)1212 user_fault_addr_matches_pac_error_code(vm_offset_t fault_addr, bool data_key)
1213 {
1214 bool instruction_tbi = !(get_tcr() & TCR_TBID0_TBI_DATA_ONLY);
1215 bool tbi = data_key || __improbable(instruction_tbi);
1216
1217 if (gARM_FEAT_PAuth2) {
1218 /*
1219 * EnhancedPAC2 CPUs don't encode error codes at fixed positions, so
1220 * treat all non-canonical address bits like potential poison bits.
1221 */
1222 uint64_t mask = fault_addr_bitmask(T0SZ_BOOT, 54);
1223 if (!tbi) {
1224 mask |= fault_addr_bitmask(56, 63);
1225 }
1226 return (fault_addr & mask) != 0;
1227 } else {
1228 unsigned int poison_shift;
1229 if (tbi) {
1230 poison_shift = 53;
1231 } else {
1232 poison_shift = 61;
1233 }
1234
1235 /* PAC error codes are always in the form key_number:NOT(key_number) */
1236 bool poison_bit_1 = fault_addr_bit(fault_addr, poison_shift);
1237 bool poison_bit_2 = fault_addr_bit(fault_addr, poison_shift + 1);
1238 return poison_bit_1 != poison_bit_2;
1239 }
1240 }
1241 #endif /* __has_feature(ptrauth_calls) */
1242
1243 static void
handle_pc_align(arm_saved_state_t * ss)1244 handle_pc_align(arm_saved_state_t *ss)
1245 {
1246 exception_type_t exc;
1247 mach_exception_data_type_t codes[2];
1248 mach_msg_type_number_t numcodes = 2;
1249
1250 if (!PSR64_IS_USER(get_saved_state_cpsr(ss))) {
1251 panic_with_thread_kernel_state("PC alignment exception from kernel.", ss);
1252 }
1253
1254 exc = EXC_BAD_ACCESS;
1255 #if __has_feature(ptrauth_calls)
1256 if (user_fault_addr_matches_pac_error_code(get_saved_state_pc(ss), false)) {
1257 exc |= EXC_PTRAUTH_BIT;
1258 }
1259 #endif /* __has_feature(ptrauth_calls) */
1260
1261 codes[0] = EXC_ARM_DA_ALIGN;
1262 codes[1] = get_saved_state_pc(ss);
1263
1264 exception_triage(exc, codes, numcodes);
1265 __builtin_unreachable();
1266 }
1267
1268 static void
handle_sp_align(arm_saved_state_t * ss)1269 handle_sp_align(arm_saved_state_t *ss)
1270 {
1271 exception_type_t exc;
1272 mach_exception_data_type_t codes[2];
1273 mach_msg_type_number_t numcodes = 2;
1274
1275 if (!PSR64_IS_USER(get_saved_state_cpsr(ss))) {
1276 panic_with_thread_kernel_state("SP alignment exception from kernel.", ss);
1277 }
1278
1279 exc = EXC_BAD_ACCESS;
1280 #if __has_feature(ptrauth_calls)
1281 if (user_fault_addr_matches_pac_error_code(get_saved_state_sp(ss), true)) {
1282 exc |= EXC_PTRAUTH_BIT;
1283 }
1284 #endif /* __has_feature(ptrauth_calls) */
1285
1286 codes[0] = EXC_ARM_SP_ALIGN;
1287 codes[1] = get_saved_state_sp(ss);
1288
1289 exception_triage(exc, codes, numcodes);
1290 __builtin_unreachable();
1291 }
1292
1293 static void
handle_wf_trap(arm_saved_state_t * state)1294 handle_wf_trap(arm_saved_state_t *state)
1295 {
1296 exception_type_t exc;
1297 mach_exception_data_type_t codes[2];
1298 mach_msg_type_number_t numcodes = 2;
1299 uint32_t instr = 0;
1300
1301 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1302
1303 exc = EXC_BAD_INSTRUCTION;
1304 codes[0] = EXC_ARM_UNDEFINED;
1305 codes[1] = instr;
1306
1307 exception_triage(exc, codes, numcodes);
1308 __builtin_unreachable();
1309 }
1310
1311 static void
handle_fp_trap(arm_saved_state_t * state,uint32_t esr)1312 handle_fp_trap(arm_saved_state_t *state, uint32_t esr)
1313 {
1314 exception_type_t exc = EXC_ARITHMETIC;
1315 mach_exception_data_type_t codes[2];
1316 mach_msg_type_number_t numcodes = 2;
1317 uint32_t instr = 0;
1318
1319 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
1320 panic_with_thread_kernel_state("Floating point exception from kernel", state);
1321 }
1322
1323 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1324 codes[1] = instr;
1325
1326 /* The floating point trap flags are only valid if TFV is set. */
1327 if (!fp_exceptions_enabled) {
1328 exc = EXC_BAD_INSTRUCTION;
1329 codes[0] = EXC_ARM_UNDEFINED;
1330 } else if (!(esr & ISS_FP_TFV)) {
1331 codes[0] = EXC_ARM_FP_UNDEFINED;
1332 } else if (esr & ISS_FP_UFF) {
1333 codes[0] = EXC_ARM_FP_UF;
1334 } else if (esr & ISS_FP_OFF) {
1335 codes[0] = EXC_ARM_FP_OF;
1336 } else if (esr & ISS_FP_IOF) {
1337 codes[0] = EXC_ARM_FP_IO;
1338 } else if (esr & ISS_FP_DZF) {
1339 codes[0] = EXC_ARM_FP_DZ;
1340 } else if (esr & ISS_FP_IDF) {
1341 codes[0] = EXC_ARM_FP_ID;
1342 } else if (esr & ISS_FP_IXF) {
1343 codes[0] = EXC_ARM_FP_IX;
1344 } else {
1345 panic("Unrecognized floating point exception, state=%p, esr=%#x", state, esr);
1346 }
1347
1348 exception_triage(exc, codes, numcodes);
1349 __builtin_unreachable();
1350 }
1351
1352
1353
1354 /*
1355 * handle_alignment_fault_from_user:
1356 * state: Saved state
1357 *
1358 * Attempts to deal with an alignment fault from userspace (possibly by
1359 * emulating the faulting instruction). If emulation failed due to an
1360 * unservicable fault, the ESR for that fault will be stored in the
1361 * recovery_esr field of the thread by the exception code.
1362 *
1363 * Returns:
1364 * -1: Emulation failed (emulation of state/instr not supported)
1365 * 0: Successfully emulated the instruction
1366 * EFAULT: Emulation failed (probably due to permissions)
1367 * EINVAL: Emulation failed (probably due to a bad address)
1368 */
1369
1370
1371 static int
handle_alignment_fault_from_user(arm_saved_state_t * state,kern_return_t * vmfr)1372 handle_alignment_fault_from_user(arm_saved_state_t *state, kern_return_t *vmfr)
1373 {
1374 int ret = -1;
1375
1376 #pragma unused (state)
1377 #pragma unused (vmfr)
1378
1379 return ret;
1380 }
1381
1382
1383
1384
1385 static void
handle_sw_step_debug(arm_saved_state_t * state)1386 handle_sw_step_debug(arm_saved_state_t *state)
1387 {
1388 thread_t thread = current_thread();
1389 exception_type_t exc;
1390 mach_exception_data_type_t codes[2];
1391 mach_msg_type_number_t numcodes = 2;
1392
1393 if (!PSR64_IS_USER(get_saved_state_cpsr(state))) {
1394 panic_with_thread_kernel_state("SW_STEP_DEBUG exception from kernel.", state);
1395 }
1396
1397 // Disable single step and unmask interrupts (in the saved state, anticipating next exception return)
1398 if (thread->machine.DebugData != NULL) {
1399 thread->machine.DebugData->uds.ds64.mdscr_el1 &= ~0x1;
1400 } else {
1401 panic_with_thread_kernel_state("SW_STEP_DEBUG exception thread DebugData is NULL.", state);
1402 }
1403
1404 mask_user_saved_state_cpsr(thread->machine.upcb, 0, PSR64_SS | DAIF_ALL);
1405
1406 // Special encoding for gdb single step event on ARM
1407 exc = EXC_BREAKPOINT;
1408 codes[0] = 1;
1409 codes[1] = 0;
1410
1411 exception_triage(exc, codes, numcodes);
1412 __builtin_unreachable();
1413 }
1414
1415 static void
handle_user_abort(arm_saved_state_t * state,uint32_t esr,vm_offset_t fault_addr,fault_status_t fault_code,vm_prot_t fault_type,expected_fault_handler_t expected_fault_handler)1416 handle_user_abort(arm_saved_state_t *state, uint32_t esr, vm_offset_t fault_addr,
1417 fault_status_t fault_code, vm_prot_t fault_type, expected_fault_handler_t expected_fault_handler)
1418 {
1419 exception_type_t exc = EXC_BAD_ACCESS;
1420 mach_exception_data_type_t codes[2];
1421 mach_msg_type_number_t numcodes = 2;
1422 thread_t thread = current_thread();
1423
1424 (void)esr;
1425 (void)expected_fault_handler;
1426
1427 if (ml_at_interrupt_context()) {
1428 panic_with_thread_kernel_state("Apparently on interrupt stack when taking user abort!\n", state);
1429 }
1430
1431 thread->iotier_override = THROTTLE_LEVEL_NONE; /* Reset IO tier override before handling abort from userspace */
1432
1433 if (!is_vm_fault(fault_code) &&
1434 thread->t_rr_state.trr_fault_state != TRR_FAULT_NONE) {
1435 thread_reset_pcs_done_faulting(thread);
1436 }
1437
1438 if (is_vm_fault(fault_code)) {
1439 vm_map_t map = thread->map;
1440 vm_offset_t vm_fault_addr = fault_addr;
1441 kern_return_t result = KERN_FAILURE;
1442
1443 assert(map != kernel_map);
1444
1445 if (!(fault_type & VM_PROT_EXECUTE)) {
1446 vm_fault_addr = VM_USER_STRIP_TBI(fault_addr);
1447 }
1448
1449 /* check to see if it is just a pmap ref/modify fault */
1450 if (!is_translation_fault(fault_code)) {
1451 result = arm_fast_fault(map->pmap,
1452 vm_fault_addr,
1453 fault_type, (fault_code == FSC_ACCESS_FLAG_FAULT_L3), TRUE);
1454 }
1455 if (result != KERN_SUCCESS) {
1456
1457 {
1458 /* We have to fault the page in */
1459 result = vm_fault(map, vm_fault_addr, fault_type,
1460 /* change_wiring */ FALSE, VM_KERN_MEMORY_NONE, THREAD_ABORTSAFE,
1461 /* caller_pmap */ NULL, /* caller_pmap_addr */ 0);
1462 }
1463 }
1464 if (thread->t_rr_state.trr_fault_state != TRR_FAULT_NONE) {
1465 thread_reset_pcs_done_faulting(thread);
1466 }
1467 if (result == KERN_SUCCESS || result == KERN_ABORTED) {
1468 return;
1469 }
1470
1471 /*
1472 * vm_fault() should never return KERN_FAILURE for page faults from user space.
1473 * If it does, we're leaking preemption disables somewhere in the kernel.
1474 */
1475 if (__improbable(result == KERN_FAILURE)) {
1476 panic("vm_fault() KERN_FAILURE from user fault on thread %p", thread);
1477 }
1478
1479 codes[0] = result;
1480 } else if (is_alignment_fault(fault_code)) {
1481 kern_return_t vmfkr = KERN_SUCCESS;
1482 thread->machine.recover_esr = 0;
1483 thread->machine.recover_far = 0;
1484 int result = handle_alignment_fault_from_user(state, &vmfkr);
1485 if (result == 0) {
1486 /* Successfully emulated, or instruction
1487 * copyin() for decode/emulation failed.
1488 * Continue, or redrive instruction.
1489 */
1490 thread_exception_return();
1491 } else if (((result == EFAULT) || (result == EINVAL)) &&
1492 (thread->machine.recover_esr == 0)) {
1493 /*
1494 * If we didn't actually take a fault, but got one of
1495 * these errors, then we failed basic sanity checks of
1496 * the fault address. Treat this as an invalid
1497 * address.
1498 */
1499 codes[0] = KERN_INVALID_ADDRESS;
1500 } else if ((result == EFAULT) &&
1501 (thread->machine.recover_esr)) {
1502 /*
1503 * Since alignment aborts are prioritized
1504 * ahead of translation aborts, the misaligned
1505 * atomic emulation flow may have triggered a
1506 * VM pagefault, which the VM could not resolve.
1507 * Report the VM fault error in codes[]
1508 */
1509
1510 codes[0] = vmfkr;
1511 assertf(vmfkr != KERN_SUCCESS, "Unexpected vmfkr 0x%x", vmfkr);
1512 /* Cause ESR_EC to reflect an EL0 abort */
1513 thread->machine.recover_esr &= ~ESR_EC_MASK;
1514 thread->machine.recover_esr |= (ESR_EC_DABORT_EL0 << ESR_EC_SHIFT);
1515 set_saved_state_esr(thread->machine.upcb, thread->machine.recover_esr);
1516 set_saved_state_far(thread->machine.upcb, thread->machine.recover_far);
1517 fault_addr = thread->machine.recover_far;
1518 } else {
1519 /* This was just an unsupported alignment
1520 * exception. Misaligned atomic emulation
1521 * timeouts fall in this category.
1522 */
1523 codes[0] = EXC_ARM_DA_ALIGN;
1524 }
1525 } else if (is_parity_error(fault_code)) {
1526 #if defined(APPLE_ARM64_ARCH_FAMILY)
1527 /*
1528 * Platform errors are handled in sleh_sync before interrupts are enabled.
1529 */
1530 #else
1531 panic("User parity error.");
1532 #endif
1533 } else {
1534 codes[0] = KERN_FAILURE;
1535 }
1536
1537 codes[1] = fault_addr;
1538 #if __has_feature(ptrauth_calls)
1539 bool is_data_abort = (ESR_EC(esr) == ESR_EC_DABORT_EL0);
1540 if (user_fault_addr_matches_pac_error_code(fault_addr, is_data_abort)) {
1541 exc |= EXC_PTRAUTH_BIT;
1542 }
1543 #endif /* __has_feature(ptrauth_calls) */
1544 exception_triage(exc, codes, numcodes);
1545 __builtin_unreachable();
1546 }
1547
1548 /**
1549 * Panic because the kernel abort handler tried to apply a recovery handler that
1550 * isn't inside copyio_recover_table[].
1551 *
1552 * @param state original saved-state
1553 * @param recover invalid recovery handler
1554 */
1555 __attribute__((noreturn, used))
1556 static void
panic_on_invalid_recovery_handler(arm_saved_state_t * state,struct copyio_recovery_entry * recover)1557 panic_on_invalid_recovery_handler(arm_saved_state_t *state, struct copyio_recovery_entry *recover)
1558 {
1559 panic("attempt to set invalid recovery handler %p on kernel saved-state %p", recover, state);
1560 }
1561
1562 static void
handle_kernel_abort_recover(arm_saved_state_t * state,uint32_t esr,vm_offset_t fault_addr,thread_t thread,struct copyio_recovery_entry * _Nonnull recover)1563 handle_kernel_abort_recover(
1564 arm_saved_state_t *state,
1565 uint32_t esr,
1566 vm_offset_t fault_addr,
1567 thread_t thread,
1568 struct copyio_recovery_entry *_Nonnull recover)
1569 {
1570 thread->machine.recover_esr = esr;
1571 thread->machine.recover_far = fault_addr;
1572 #if defined(HAS_APPLE_PAC)
1573 MANIPULATE_SIGNED_THREAD_STATE(state,
1574 "adrp x6, _copyio_recover_table_end@page \n"
1575 "add x6, x6, _copyio_recover_table_end@pageoff \n"
1576 "cmp %[recover], x6 \n"
1577 "b.lt 1f \n"
1578 "b _panic_on_invalid_recovery_handler \n"
1579 "1: \n"
1580 "adrp x6, _copyio_recover_table@page \n"
1581 "add x6, x6, _copyio_recover_table@pageoff \n"
1582 "cmp %[recover], x6 \n"
1583 "b.ge 1f \n"
1584 "b _panic_on_invalid_recovery_handler \n"
1585 "1: \n"
1586 "ldr x1, [%[recover], %[CRE_RECOVERY]] \n"
1587 "add x1, x1, x6 \n"
1588 "str x1, [x0, %[SS64_PC]] \n",
1589 [recover] "r"(recover),
1590 [CRE_RECOVERY] "i"(offsetof(struct copyio_recovery_entry, cre_recovery))
1591 );
1592 #else
1593 if ((uintptr_t)recover < (uintptr_t)copyio_recover_table ||
1594 (uintptr_t)recover >= (uintptr_t)copyio_recover_table_end) {
1595 panic_on_invalid_recovery_handler(state, recover);
1596 }
1597 saved_state64(state)->pc = copyio_recovery_addr(recover->cre_recovery);
1598 #endif
1599 }
1600
1601 static void
handle_kernel_abort(arm_saved_state_t * state,uint32_t esr,vm_offset_t fault_addr,fault_status_t fault_code,vm_prot_t fault_type,expected_fault_handler_t expected_fault_handler)1602 handle_kernel_abort(arm_saved_state_t *state, uint32_t esr, vm_offset_t fault_addr,
1603 fault_status_t fault_code, vm_prot_t fault_type, expected_fault_handler_t expected_fault_handler)
1604 {
1605 thread_t thread = current_thread();
1606 struct copyio_recovery_entry *recover = find_copyio_recovery_entry(state);
1607
1608 #ifdef CONFIG_KERNEL_TAGGING
1609 /*
1610 * If a read/write access to a tagged address faults over pageable kernel memory
1611 * vm_fault() will need to find the right vm entry and offset. Canonicalize the
1612 * address here so that the correct comparisons can happen later in the VM code.
1613 */
1614 if (!(fault_type & VM_PROT_EXECUTE) && VM_KERNEL_ADDRESS(fault_addr)) {
1615 fault_addr = vm_memtag_canonicalize_address(fault_addr);
1616 }
1617 #endif /* CONFIG_KERNEL_TAGGING */
1618
1619 #ifndef CONFIG_XNUPOST
1620 (void)expected_fault_handler;
1621 #endif /* CONFIG_XNUPOST */
1622
1623 #if CONFIG_DTRACE
1624 if (is_vm_fault(fault_code) && thread->t_dtrace_inprobe) { /* Executing under dtrace_probe? */
1625 if (dtrace_tally_fault(fault_addr)) { /* Should a fault under dtrace be ignored? */
1626 /*
1627 * Point to next instruction, or recovery handler if set.
1628 */
1629 if (recover) {
1630 handle_kernel_abort_recover(state, esr, fault_addr, thread, recover);
1631 } else {
1632 add_saved_state_pc(state, 4);
1633 }
1634 return;
1635 } else {
1636 panic_with_thread_kernel_state("Unexpected page fault under dtrace_probe", state);
1637 }
1638 }
1639 #endif
1640
1641 if (ml_at_interrupt_context()) {
1642 panic_with_thread_kernel_state("Unexpected abort while on interrupt stack.", state);
1643 }
1644
1645 if (is_vm_fault(fault_code)) {
1646 kern_return_t result = KERN_FAILURE;
1647 vm_map_t map;
1648 int interruptible;
1649
1650 /*
1651 * Ensure no faults in the physical aperture. This could happen if
1652 * a page table is incorrectly allocated from the read only region
1653 * when running with KTRR.
1654 */
1655
1656 #ifdef CONFIG_XNUPOST
1657 if (expected_fault_handler && expected_fault_handler(state)) {
1658 return;
1659 }
1660 #endif /* CONFIG_XNUPOST */
1661
1662 if (fault_addr >= gVirtBase && fault_addr < static_memory_end) {
1663 panic_with_thread_kernel_state("Unexpected fault in kernel static region\n", state);
1664 }
1665
1666 if (VM_KERNEL_ADDRESS(fault_addr) || thread == THREAD_NULL || recover == 0) {
1667 /*
1668 * If no recovery handler is supplied, always drive the fault against
1669 * the kernel map. If the fault was taken against a userspace VA, indicating
1670 * an unprotected access to user address space, vm_fault() should fail and
1671 * ultimately lead to a panic here.
1672 */
1673 map = kernel_map;
1674 interruptible = THREAD_UNINT;
1675 } else {
1676 map = thread->map;
1677
1678 /**
1679 * In the case that the recovery handler is set (e.g., during copyio
1680 * and dtrace probes), we don't want the vm_fault() operation to be
1681 * aborted early. Those code paths can't handle restarting the
1682 * vm_fault() operation so don't allow it to return early without
1683 * creating the wanted mapping.
1684 */
1685 interruptible = (recover) ? THREAD_UNINT : THREAD_ABORTSAFE;
1686 }
1687
1688 /* check to see if it is just a pmap ref/modify fault */
1689 if (!is_translation_fault(fault_code)) {
1690 result = arm_fast_fault(map->pmap,
1691 fault_addr,
1692 fault_type, (fault_code == FSC_ACCESS_FLAG_FAULT_L3), FALSE);
1693 if (result == KERN_SUCCESS) {
1694 return;
1695 }
1696 }
1697
1698 if (result != KERN_PROTECTION_FAILURE) {
1699 /*
1700 * We have to "fault" the page in.
1701 */
1702 result = vm_fault(map, fault_addr, fault_type,
1703 /* change_wiring */ FALSE, VM_KERN_MEMORY_NONE, interruptible,
1704 /* caller_pmap */ NULL, /* caller_pmap_addr */ 0);
1705 }
1706
1707 if (result == KERN_SUCCESS) {
1708 return;
1709 }
1710
1711 /*
1712 * If we have a recover handler, invoke it now.
1713 */
1714 if (recover) {
1715 handle_kernel_abort_recover(state, esr, fault_addr, thread, recover);
1716 return;
1717 }
1718
1719 panic_fault_address = fault_addr;
1720 } else if (is_alignment_fault(fault_code)) {
1721 if (recover) {
1722 handle_kernel_abort_recover(state, esr, fault_addr, thread, recover);
1723 return;
1724 }
1725 panic_with_thread_kernel_state("Unaligned kernel data abort.", state);
1726 } else if (is_parity_error(fault_code)) {
1727 #if defined(APPLE_ARM64_ARCH_FAMILY)
1728 /*
1729 * Platform errors are handled in sleh_sync before interrupts are enabled.
1730 */
1731 #else
1732 panic_with_thread_kernel_state("Kernel parity error.", state);
1733 #endif
1734 } else {
1735 kprintf("Unclassified kernel abort (fault_code=0x%x)\n", fault_code);
1736 }
1737
1738 panic_with_thread_kernel_state("Kernel data abort.", state);
1739 }
1740
1741 extern void syscall_trace(struct arm_saved_state * regs);
1742
1743 static void
handle_svc(arm_saved_state_t * state)1744 handle_svc(arm_saved_state_t *state)
1745 {
1746 int trap_no = get_saved_state_svc_number(state);
1747 thread_t thread = current_thread();
1748 struct proc *p;
1749
1750 #define handle_svc_kprintf(x...) /* kprintf("handle_svc: " x) */
1751
1752 #define TRACE_SYSCALL 1
1753 #if TRACE_SYSCALL
1754 syscall_trace(state);
1755 #endif
1756
1757 thread->iotier_override = THROTTLE_LEVEL_NONE; /* Reset IO tier override before handling SVC from userspace */
1758
1759 if (trap_no == (int)PLATFORM_SYSCALL_TRAP_NO) {
1760 platform_syscall(state);
1761 panic("Returned from platform_syscall()?");
1762 }
1763
1764 mach_kauth_cred_thread_update();
1765
1766 if (trap_no < 0) {
1767 switch (trap_no) {
1768 case MACH_ARM_TRAP_ABSTIME:
1769 handle_mach_absolute_time_trap(state);
1770 return;
1771 case MACH_ARM_TRAP_CONTTIME:
1772 handle_mach_continuous_time_trap(state);
1773 return;
1774 }
1775
1776 /* Counting perhaps better in the handler, but this is how it's been done */
1777 thread->syscalls_mach++;
1778 mach_syscall(state);
1779 } else {
1780 /* Counting perhaps better in the handler, but this is how it's been done */
1781 thread->syscalls_unix++;
1782 p = get_bsdthreadtask_info(thread);
1783
1784 assert(p);
1785
1786 unix_syscall(state, thread, p);
1787 }
1788 }
1789
1790 static void
handle_mach_absolute_time_trap(arm_saved_state_t * state)1791 handle_mach_absolute_time_trap(arm_saved_state_t *state)
1792 {
1793 uint64_t now = mach_absolute_time();
1794 saved_state64(state)->x[0] = now;
1795 }
1796
1797 static void
handle_mach_continuous_time_trap(arm_saved_state_t * state)1798 handle_mach_continuous_time_trap(arm_saved_state_t *state)
1799 {
1800 uint64_t now = mach_continuous_time();
1801 saved_state64(state)->x[0] = now;
1802 }
1803
1804
1805 __attribute__((noreturn))
1806 static void
handle_msr_trap(arm_saved_state_t * state,uint32_t esr)1807 handle_msr_trap(arm_saved_state_t *state, uint32_t esr)
1808 {
1809 exception_type_t exception = EXC_BAD_INSTRUCTION;
1810 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
1811 mach_msg_type_number_t numcodes = 2;
1812 uint32_t instr = 0;
1813
1814 if (!is_saved_state64(state)) {
1815 panic("MSR/MRS trap (ESR 0x%x) from 32-bit state", esr);
1816 }
1817
1818 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
1819 panic("MSR/MRS trap (ESR 0x%x) from kernel", esr);
1820 }
1821
1822 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1823 codes[1] = instr;
1824
1825 exception_triage(exception, codes, numcodes);
1826 __builtin_unreachable();
1827 }
1828
1829 #if __has_feature(ptrauth_calls)
1830 static void
stringify_gpr(unsigned int r,char reg[4])1831 stringify_gpr(unsigned int r, char reg[4])
1832 {
1833 switch (r) {
1834 case 29:
1835 strncpy(reg, "fp", 4);
1836 return;
1837
1838 case 30:
1839 strncpy(reg, "lr", 4);
1840 return;
1841
1842 case 31:
1843 strncpy(reg, "xzr", 4);
1844 return;
1845
1846 default:
1847 snprintf(reg, 4, "x%u", r);
1848 return;
1849 }
1850 }
1851
1852 static void
autxx_instruction_extract_reg(uint32_t instr,char reg[4])1853 autxx_instruction_extract_reg(uint32_t instr, char reg[4])
1854 {
1855 unsigned int rd = ARM64_INSTR_AUTxx_RD_GET(instr);
1856 stringify_gpr(rd, reg);
1857 }
1858
1859 static const char *
autix_system_instruction_extract_reg(uint32_t instr)1860 autix_system_instruction_extract_reg(uint32_t instr)
1861 {
1862 unsigned int crm_op2 = ARM64_INSTR_AUTIx_SYSTEM_CRM_OP2_GET(instr);
1863 if (crm_op2 == ARM64_INSTR_AUTIx_SYSTEM_CRM_OP2_AUTIA1716 ||
1864 crm_op2 == ARM64_INSTR_AUTIx_SYSTEM_CRM_OP2_AUTIB1716) {
1865 return "x17";
1866 } else {
1867 return "lr";
1868 }
1869 }
1870
1871
1872 static void
handle_pac_fail(arm_saved_state_t * state,uint32_t esr)1873 handle_pac_fail(arm_saved_state_t *state, uint32_t esr)
1874 {
1875 exception_type_t exception = EXC_BAD_ACCESS | EXC_PTRAUTH_BIT;
1876 mach_exception_data_type_t codes[2] = {EXC_ARM_PAC_FAIL};
1877 mach_msg_type_number_t numcodes = 2;
1878 uint32_t instr = 0;
1879
1880 if (!is_saved_state64(state)) {
1881 panic("PAC failure (ESR 0x%x) from 32-bit state", esr);
1882 }
1883
1884 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1885
1886 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
1887 #define GENERIC_PAC_FAILURE_MSG_FMT "PAC failure from kernel with %s key"
1888 #define AUTXX_MSG_FMT GENERIC_PAC_FAILURE_MSG_FMT " while authing %s"
1889 #define GENERIC_MSG_FMT GENERIC_PAC_FAILURE_MSG_FMT
1890 #define MAX_PAC_MSG_FMT AUTXX_MSG_FMT
1891
1892 char msg[strlen(MAX_PAC_MSG_FMT)
1893 - strlen("%s") + strlen("IA")
1894 - strlen("%s") + strlen("xzr")
1895 + 1];
1896 ptrauth_key key = (ptrauth_key)(esr & 0x3);
1897 const char *key_str = ptrauth_key_to_string(key);
1898
1899 if (ARM64_INSTR_IS_AUTxx(instr)) {
1900 char reg[4];
1901 autxx_instruction_extract_reg(instr, reg);
1902 snprintf(msg, sizeof(msg), AUTXX_MSG_FMT, key_str, reg);
1903 } else if (ARM64_INSTR_IS_AUTIx_SYSTEM(instr)) {
1904 const char *reg = autix_system_instruction_extract_reg(instr);
1905 snprintf(msg, sizeof(msg), AUTXX_MSG_FMT, key_str, reg);
1906 } else {
1907 snprintf(msg, sizeof(msg), GENERIC_MSG_FMT, key_str);
1908 }
1909 panic_with_thread_kernel_state(msg, state);
1910 }
1911
1912 codes[1] = instr;
1913
1914 exception_triage(exception, codes, numcodes);
1915 __builtin_unreachable();
1916 }
1917 #endif /* __has_feature(ptrauth_calls) */
1918
1919 static void
handle_user_trapped_instruction32(arm_saved_state_t * state,uint32_t esr)1920 handle_user_trapped_instruction32(arm_saved_state_t *state, uint32_t esr)
1921 {
1922 exception_type_t exception = EXC_BAD_INSTRUCTION;
1923 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
1924 mach_msg_type_number_t numcodes = 2;
1925 uint32_t instr;
1926
1927 if (is_saved_state64(state)) {
1928 panic("ESR (0x%x) for instruction trapped from U32, but saved state is 64-bit.", esr);
1929 }
1930
1931 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
1932 panic("ESR (0x%x) for instruction trapped from U32, actually came from kernel?", esr);
1933 }
1934
1935 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1936 codes[1] = instr;
1937
1938 exception_triage(exception, codes, numcodes);
1939 __builtin_unreachable();
1940 }
1941
1942 static void
handle_simd_trap(arm_saved_state_t * state,uint32_t esr)1943 handle_simd_trap(arm_saved_state_t *state, uint32_t esr)
1944 {
1945 exception_type_t exception = EXC_BAD_INSTRUCTION;
1946 mach_exception_data_type_t codes[2] = {EXC_ARM_UNDEFINED};
1947 mach_msg_type_number_t numcodes = 2;
1948 uint32_t instr = 0;
1949
1950 if (PSR64_IS_KERNEL(get_saved_state_cpsr(state))) {
1951 panic("ESR (0x%x) for SIMD trap from userland, actually came from kernel?", esr);
1952 }
1953
1954 COPYIN(get_saved_state_pc(state), (char *)&instr, sizeof(instr));
1955 codes[1] = instr;
1956
1957 exception_triage(exception, codes, numcodes);
1958 __builtin_unreachable();
1959 }
1960
1961 void
sleh_irq(arm_saved_state_t * state)1962 sleh_irq(arm_saved_state_t *state)
1963 {
1964 cpu_data_t * cdp __unused = getCpuDatap();
1965 #if MACH_ASSERT
1966 int preemption_level = sleh_get_preemption_level();
1967 #endif
1968
1969
1970 sleh_interrupt_handler_prologue(state, DBG_INTR_TYPE_OTHER);
1971
1972 #if USE_APPLEARMSMP
1973 PE_handle_ext_interrupt();
1974 #else
1975 /* Run the registered interrupt handler. */
1976 cdp->interrupt_handler(cdp->interrupt_target,
1977 cdp->interrupt_refCon,
1978 cdp->interrupt_nub,
1979 cdp->interrupt_source);
1980 #endif
1981
1982 entropy_collect();
1983
1984
1985 sleh_interrupt_handler_epilogue();
1986 #if MACH_ASSERT
1987 if (preemption_level != sleh_get_preemption_level()) {
1988 panic("irq handler %p changed preemption level from %d to %d", cdp->interrupt_handler, preemption_level, sleh_get_preemption_level());
1989 }
1990 #endif
1991 }
1992
1993 void
sleh_fiq(arm_saved_state_t * state)1994 sleh_fiq(arm_saved_state_t *state)
1995 {
1996 unsigned int type = DBG_INTR_TYPE_UNKNOWN;
1997 #if MACH_ASSERT
1998 int preemption_level = sleh_get_preemption_level();
1999 #endif
2000
2001 #if MONOTONIC_FIQ
2002 uint64_t pmcr0 = 0, upmsr = 0;
2003 #endif /* MONOTONIC_FIQ */
2004
2005 #if defined(HAS_IPI)
2006 boolean_t is_ipi = FALSE;
2007 uint64_t ipi_sr = 0;
2008
2009 if (gFastIPI) {
2010 MRS(ipi_sr, "S3_5_C15_C1_1");
2011
2012 if (ipi_sr & ARM64_IPISR_IPI_PENDING) {
2013 is_ipi = TRUE;
2014 }
2015 }
2016
2017 if (is_ipi) {
2018 type = DBG_INTR_TYPE_IPI;
2019 } else
2020 #endif /* defined(HAS_IPI) */
2021 if (ml_get_timer_pending()) {
2022 type = DBG_INTR_TYPE_TIMER;
2023 }
2024 #if MONOTONIC_FIQ
2025 /* Consult the PMI sysregs last, after IPI/timer
2026 * classification.
2027 */
2028 else if (mt_pmi_pending(&pmcr0, &upmsr)) {
2029 type = DBG_INTR_TYPE_PMI;
2030 }
2031 #endif /* MONOTONIC_FIQ */
2032
2033 sleh_interrupt_handler_prologue(state, type);
2034
2035 #if APPLEVIRTUALPLATFORM
2036 uint64_t iar = __builtin_arm_rsr64("ICC_IAR0_EL1");
2037 #endif
2038
2039 #if defined(HAS_IPI)
2040 if (type == DBG_INTR_TYPE_IPI) {
2041 /*
2042 * Order is important here: we must ack the IPI by writing IPI_SR
2043 * before we call cpu_signal_handler(). Otherwise, there will be
2044 * a window between the completion of pending-signal processing in
2045 * cpu_signal_handler() and the ack during which a newly-issued
2046 * IPI to this CPU may be lost. ISB is required to ensure the msr
2047 * is retired before execution of cpu_signal_handler().
2048 */
2049 MSR("S3_5_C15_C1_1", ARM64_IPISR_IPI_PENDING);
2050 __builtin_arm_isb(ISB_SY);
2051 cpu_signal_handler();
2052 } else
2053 #endif /* defined(HAS_IPI) */
2054 #if MONOTONIC_FIQ
2055 if (type == DBG_INTR_TYPE_PMI) {
2056 INTERRUPT_MASKED_DEBUG_START(mt_fiq, DBG_INTR_TYPE_PMI);
2057 mt_fiq(getCpuDatap(), pmcr0, upmsr);
2058 INTERRUPT_MASKED_DEBUG_END();
2059 } else
2060 #endif /* MONOTONIC_FIQ */
2061 {
2062 /*
2063 * We don't know that this is a timer, but we don't have insight into
2064 * the other interrupts that go down this path.
2065 */
2066
2067 cpu_data_t *cdp = getCpuDatap();
2068
2069 cdp->cpu_decrementer = -1; /* Large */
2070
2071 /*
2072 * ARM64_TODO: whether we're coming from userland is ignored right now.
2073 * We can easily thread it through, but not bothering for the
2074 * moment (AArch32 doesn't either).
2075 */
2076 INTERRUPT_MASKED_DEBUG_START(rtclock_intr, DBG_INTR_TYPE_TIMER);
2077 rtclock_intr(TRUE);
2078 INTERRUPT_MASKED_DEBUG_END();
2079 }
2080
2081 #if APPLEVIRTUALPLATFORM
2082 if (iar != GIC_SPURIOUS_IRQ) {
2083 __builtin_arm_wsr64("ICC_EOIR0_EL1", iar);
2084 __builtin_arm_isb(ISB_SY);
2085 }
2086 #endif
2087
2088 sleh_interrupt_handler_epilogue();
2089 #if MACH_ASSERT
2090 if (preemption_level != sleh_get_preemption_level()) {
2091 panic("fiq type %u changed preemption level from %d to %d", type, preemption_level, sleh_get_preemption_level());
2092 }
2093 #endif
2094 }
2095
2096 void
sleh_serror(arm_context_t * context,uint32_t esr,vm_offset_t far)2097 sleh_serror(arm_context_t *context, uint32_t esr, vm_offset_t far)
2098 {
2099 task_vtimer_check(current_thread());
2100
2101 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_SERR_ARM, 0) | DBG_FUNC_START,
2102 esr, VM_KERNEL_ADDRHIDE(far));
2103 arm_saved_state_t *state = &context->ss;
2104 #if MACH_ASSERT
2105 int preemption_level = sleh_get_preemption_level();
2106 #endif
2107
2108 if (PSR64_IS_USER(get_saved_state_cpsr(state))) {
2109 /* Sanitize FAR (only if we came from userspace) */
2110 saved_state64(state)->far = 0;
2111 }
2112
2113 ASSERT_CONTEXT_SANITY(context);
2114 arm64_platform_error(state, esr, far, PLAT_ERR_SRC_ASYNC);
2115 #if MACH_ASSERT
2116 if (preemption_level != sleh_get_preemption_level()) {
2117 panic("serror changed preemption level from %d to %d", preemption_level, sleh_get_preemption_level());
2118 }
2119 #endif
2120 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_SERR_ARM, 0) | DBG_FUNC_END,
2121 esr, VM_KERNEL_ADDRHIDE(far));
2122 }
2123
2124 void
mach_syscall_trace_exit(unsigned int retval,unsigned int call_number)2125 mach_syscall_trace_exit(unsigned int retval,
2126 unsigned int call_number)
2127 {
2128 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
2129 MACHDBG_CODE(DBG_MACH_EXCP_SC, (call_number)) |
2130 DBG_FUNC_END, retval, 0, 0, 0, 0);
2131 }
2132
2133 __attribute__((noreturn))
2134 void
thread_syscall_return(kern_return_t error)2135 thread_syscall_return(kern_return_t error)
2136 {
2137 thread_t thread;
2138 struct arm_saved_state *state;
2139
2140 thread = current_thread();
2141 state = get_user_regs(thread);
2142
2143 assert(is_saved_state64(state));
2144 saved_state64(state)->x[0] = error;
2145
2146 #if MACH_ASSERT
2147 kern_allocation_name_t
2148 prior __assert_only = thread_get_kernel_state(thread)->allocation_name;
2149 assertf(prior == NULL, "thread_set_allocation_name(\"%s\") not cleared", kern_allocation_get_name(prior));
2150 #endif /* MACH_ASSERT */
2151
2152 if (kdebug_enable) {
2153 /* Invert syscall number (negative for a mach syscall) */
2154 mach_syscall_trace_exit(error, (-1) * get_saved_state_svc_number(state));
2155 }
2156
2157 thread_exception_return();
2158 }
2159
2160 void
syscall_trace(struct arm_saved_state * regs __unused)2161 syscall_trace(
2162 struct arm_saved_state * regs __unused)
2163 {
2164 /* kprintf("syscall: %d\n", saved_state64(regs)->x[16]); */
2165 }
2166
2167 static void
sleh_interrupt_handler_prologue(arm_saved_state_t * state,unsigned int type)2168 sleh_interrupt_handler_prologue(arm_saved_state_t *state, unsigned int type)
2169 {
2170 const bool is_user = PSR64_IS_USER(get_saved_state_cpsr(state));
2171
2172 if (is_user == true) {
2173 /* Sanitize FAR (only if the interrupt occurred while the CPU was in usermode) */
2174 saved_state64(state)->far = 0;
2175 }
2176
2177 recount_enter_interrupt();
2178
2179 task_vtimer_check(current_thread());
2180
2181 uint64_t pc = is_user ? get_saved_state_pc(state) :
2182 VM_KERNEL_UNSLIDE(get_saved_state_pc(state));
2183
2184 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
2185 0, pc, is_user, type);
2186
2187 #if CONFIG_TELEMETRY
2188 if (telemetry_needs_record) {
2189 telemetry_mark_curthread(is_user, FALSE);
2190 }
2191 #endif /* CONFIG_TELEMETRY */
2192 }
2193
2194 static void
sleh_interrupt_handler_epilogue(void)2195 sleh_interrupt_handler_epilogue(void)
2196 {
2197 #if KPERF
2198 kperf_interrupt();
2199 #endif /* KPERF */
2200 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END);
2201 recount_leave_interrupt();
2202 }
2203
2204 void
sleh_invalid_stack(arm_context_t * context,uint32_t esr __unused,vm_offset_t far __unused)2205 sleh_invalid_stack(arm_context_t *context, uint32_t esr __unused, vm_offset_t far __unused)
2206 {
2207 thread_t thread = current_thread();
2208 vm_offset_t kernel_stack_bottom, sp;
2209
2210 sp = get_saved_state_sp(&context->ss);
2211 vm_offset_t kstackptr = (vm_offset_t)thread->machine.kstackptr;
2212 kernel_stack_bottom = round_page(kstackptr) - KERNEL_STACK_SIZE;
2213
2214 if ((sp < kernel_stack_bottom) && (sp >= (kernel_stack_bottom - PAGE_SIZE))) {
2215 panic_with_thread_kernel_state("Invalid kernel stack pointer (probable overflow).", &context->ss);
2216 }
2217
2218 panic_with_thread_kernel_state("Invalid kernel stack pointer (probable corruption).", &context->ss);
2219 }
2220
2221
2222 #if DEVELOPMENT || DEBUG
2223 static int trap_handled;
2224 static void
handle_recoverable_kernel_trap(__unused void * tstate,uint16_t comment)2225 handle_recoverable_kernel_trap(
2226 __unused void *tstate,
2227 uint16_t comment)
2228 {
2229 assert(comment == TEST_RECOVERABLE_SOFT_TRAP);
2230
2231 printf("Recoverable trap handled.\n");
2232 trap_handled = 1;
2233 }
2234
2235 KERNEL_BRK_DESCRIPTOR_DEFINE(test_desc,
2236 .type = KERNEL_BRK_TYPE_TEST,
2237 .base = TEST_RECOVERABLE_SOFT_TRAP,
2238 .max = TEST_RECOVERABLE_SOFT_TRAP,
2239 .options = KERNEL_BRK_RECOVERABLE,
2240 .handle_breakpoint = handle_recoverable_kernel_trap);
2241
2242 static int
recoverable_kernel_trap_test(__unused int64_t in,int64_t * out)2243 recoverable_kernel_trap_test(__unused int64_t in, int64_t *out)
2244 {
2245 ml_recoverable_trap(TEST_RECOVERABLE_SOFT_TRAP);
2246
2247 *out = trap_handled;
2248 return 0;
2249 }
2250
2251 SYSCTL_TEST_REGISTER(recoverable_kernel_trap, recoverable_kernel_trap_test);
2252
2253 #endif
2254