1 /* 2 * Copyright (c) 2019 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 29 30 #ifndef _ARM64_DWARF_UNWIND_H_ 31 #define _ARM64_DWARF_UNWIND_H_ 32 33 /* 34 * This file contains the architecture specific DWARF definitions needed for unwind 35 * information added to trap handlers (and hand-written assembly functions that 36 * don't follow the standard calling convention ABI). 37 */ 38 39 /* DWARF Register numbers for ARM64 registers contained in the saved state */ 40 #define DWARF_ARM64_X0 0 41 #define DWARF_ARM64_X1 1 42 #define DWARF_ARM64_X2 2 43 #define DWARF_ARM64_X3 3 44 #define DWARF_ARM64_X4 4 45 #define DWARF_ARM64_X5 5 46 #define DWARF_ARM64_X6 6 47 #define DWARF_ARM64_X7 7 48 #define DWARF_ARM64_X8 8 49 #define DWARF_ARM64_X9 9 50 #define DWARF_ARM64_X10 10 51 #define DWARF_ARM64_X11 11 52 #define DWARF_ARM64_X12 12 53 #define DWARF_ARM64_X13 13 54 #define DWARF_ARM64_X14 14 55 #define DWARF_ARM64_X15 15 56 #define DWARF_ARM64_X16 16 57 #define DWARF_ARM64_X17 17 58 #define DWARF_ARM64_X18 18 59 #define DWARF_ARM64_X19 19 60 #define DWARF_ARM64_X20 20 61 #define DWARF_ARM64_X21 21 62 #define DWARF_ARM64_X22 22 63 #define DWARF_ARM64_X23 23 64 #define DWARF_ARM64_X24 24 65 #define DWARF_ARM64_X25 25 66 #define DWARF_ARM64_X26 26 67 #define DWARF_ARM64_X27 27 68 #define DWARF_ARM64_X28 28 69 70 #define DWARF_ARM64_FP 29 71 #define DWARF_ARM64_LR 30 72 #define DWARF_ARM64_SP 31 73 #define DWARF_ARM64_PC 32 74 #define DWARF_ARM64_CPSR 33 75 76 #define DWARF_ARM64_X0_OFFSET 8 77 #define DWARF_ARM64_X1_OFFSET 16 78 #define DWARF_ARM64_X2_OFFSET 24 79 #define DWARF_ARM64_X3_OFFSET 32 80 #define DWARF_ARM64_X4_OFFSET 40 81 #define DWARF_ARM64_X5_OFFSET 48 82 #define DWARF_ARM64_X6_OFFSET 56 83 #define DWARF_ARM64_X7_OFFSET 0xc0, 0x00 84 #define DWARF_ARM64_X8_OFFSET 0xc8, 0x00 85 #define DWARF_ARM64_X9_OFFSET 0xd0, 0x00 86 #define DWARF_ARM64_X10_OFFSET 0xd8, 0x00 87 #define DWARF_ARM64_X11_OFFSET 0xe0, 0x00 88 #define DWARF_ARM64_X12_OFFSET 0xe8, 0x00 89 #define DWARF_ARM64_X13_OFFSET 0xf0, 0x00 90 #define DWARF_ARM64_X14_OFFSET 0xf8, 0x00 91 #define DWARF_ARM64_X15_OFFSET 0x80, 0x01 92 #define DWARF_ARM64_X16_OFFSET 0x88, 0x01 93 #define DWARF_ARM64_X17_OFFSET 0x90, 0x01 94 #define DWARF_ARM64_X18_OFFSET 0x98, 0x01 95 #define DWARF_ARM64_X19_OFFSET 0xa0, 0x01 96 #define DWARF_ARM64_X20_OFFSET 0xa8, 0x01 97 #define DWARF_ARM64_X21_OFFSET 0xb0, 0x01 98 #define DWARF_ARM64_X22_OFFSET 0xb8, 0x01 99 #define DWARF_ARM64_X23_OFFSET 0xc0, 0x01 100 #define DWARF_ARM64_X24_OFFSET 0xc8, 0x01 101 #define DWARF_ARM64_X25_OFFSET 0xd0, 0x01 102 #define DWARF_ARM64_X26_OFFSET 0xd8, 0x01 103 #define DWARF_ARM64_X27_OFFSET 0xe0, 0x01 104 #define DWARF_ARM64_X28_OFFSET 0xe8, 0x01 105 106 #define DWARF_ARM64_FP_OFFSET 0xf0, 0x01 107 #define DWARF_ARM64_LR_OFFSET 0xf8, 0x01 108 #define DWARF_ARM64_SP_OFFSET 0x80, 0x02 109 #define DWARF_ARM64_PC_OFFSET 0x88, 0x02 110 #define DWARF_ARM64_CPSR_OFFSET 0x90, 0x02 111 112 /* DWARF constants */ 113 #define DW_CFA_register 0x09 114 #define DW_CFA_expression 0x10 115 #define DW_CFA_offset_extended_sf 0x11 116 117 #define DW_OP_breg21 0x85 118 119 #define DW_FORM_LEN_ONE_BYTE_SLEB 2 120 #define DW_FORM_LEN_TWO_BYTE_SLEB 3 121 122 123 /* The actual unwind directives added to trap handlers to let the debugger know where the register state is stored */ 124 125 /* Unwind Prologue added to each function to indicate the start of the unwind information. */ 126 #define UNWIND_PROLOGUE \ 127 .cfi_sections .eh_frame %%\ 128 .cfi_startproc %%\ 129 130 #define TRAP_UNWIND_PROLOGUE \ 131 UNWIND_PROLOGUE \ 132 .cfi_signal_frame %%\ 133 134 /* Unwind Epilogue added to each function to indicate the end of the unwind information */ 135 136 #define UNWIND_EPILOGUE .cfi_endproc 137 138 /* Unwind directives for trap handlers let the debugger know where the register state is stored. 139 * 140 * The saved state is stored in the `struct arm_kernel_saved_state` pointed to by x21. 141 * 142 * A note on setting the CFA relative to $fp: 143 * We have hand-written assembly that alters $sp all over the place, which interferes with InstructionEmulation-based unwinding. 144 * So lldb falls back to the architecture-default unwind plan - which sets the CFA relative to $sp. 145 * Although the $sp tampering means it can't be provided - we don't need at all for the unwind plan here. 146 * By setting the CFA relative to $fp, which can be provided, lldb won't stop unwinding */ 147 #define TRAP_UNWIND_DIRECTIVES \ 148 .cfi_def_cfa w29, 0 %%\ 149 .cfi_escape DW_CFA_expression, DWARF_ARM64_X0, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X0_OFFSET %%\ 150 .cfi_escape DW_CFA_expression, DWARF_ARM64_X1, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X1_OFFSET %%\ 151 .cfi_escape DW_CFA_expression, DWARF_ARM64_X2, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X2_OFFSET %%\ 152 .cfi_escape DW_CFA_expression, DWARF_ARM64_X3, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X3_OFFSET %%\ 153 .cfi_escape DW_CFA_expression, DWARF_ARM64_X4, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X4_OFFSET %%\ 154 .cfi_escape DW_CFA_expression, DWARF_ARM64_X5, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X5_OFFSET %%\ 155 .cfi_escape DW_CFA_expression, DWARF_ARM64_X6, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X6_OFFSET %%\ 156 .cfi_escape DW_CFA_expression, DWARF_ARM64_X7, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X7_OFFSET %%\ 157 .cfi_escape DW_CFA_expression, DWARF_ARM64_X8, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X8_OFFSET %%\ 158 .cfi_escape DW_CFA_expression, DWARF_ARM64_X9, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X9_OFFSET %%\ 159 .cfi_escape DW_CFA_expression, DWARF_ARM64_X10, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X10_OFFSET %%\ 160 .cfi_escape DW_CFA_expression, DWARF_ARM64_X11, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X11_OFFSET %%\ 161 .cfi_escape DW_CFA_expression, DWARF_ARM64_X12, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X12_OFFSET %%\ 162 .cfi_escape DW_CFA_expression, DWARF_ARM64_X13, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X13_OFFSET %%\ 163 .cfi_escape DW_CFA_expression, DWARF_ARM64_X14, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X14_OFFSET %%\ 164 .cfi_escape DW_CFA_expression, DWARF_ARM64_X15, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X15_OFFSET %%\ 165 .cfi_escape DW_CFA_expression, DWARF_ARM64_X16, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X16_OFFSET %%\ 166 .cfi_escape DW_CFA_expression, DWARF_ARM64_X17, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X17_OFFSET %%\ 167 .cfi_escape DW_CFA_expression, DWARF_ARM64_X18, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X18_OFFSET %%\ 168 .cfi_escape DW_CFA_expression, DWARF_ARM64_X19, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X19_OFFSET %%\ 169 .cfi_escape DW_CFA_expression, DWARF_ARM64_X20, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X20_OFFSET %%\ 170 .cfi_escape DW_CFA_expression, DWARF_ARM64_X21, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X21_OFFSET %%\ 171 .cfi_escape DW_CFA_expression, DWARF_ARM64_X22, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X22_OFFSET %%\ 172 .cfi_escape DW_CFA_expression, DWARF_ARM64_X23, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X23_OFFSET %%\ 173 .cfi_escape DW_CFA_expression, DWARF_ARM64_X24, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X24_OFFSET %%\ 174 .cfi_escape DW_CFA_expression, DWARF_ARM64_X25, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X25_OFFSET %%\ 175 .cfi_escape DW_CFA_expression, DWARF_ARM64_X26, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X26_OFFSET %%\ 176 .cfi_escape DW_CFA_expression, DWARF_ARM64_X27, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X27_OFFSET %%\ 177 .cfi_escape DW_CFA_expression, DWARF_ARM64_X28, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_X28_OFFSET %%\ 178 .cfi_escape DW_CFA_expression, DWARF_ARM64_FP, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_FP_OFFSET %%\ 179 .cfi_escape DW_CFA_expression, DWARF_ARM64_LR, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_LR_OFFSET %%\ 180 .cfi_escape DW_CFA_expression, DWARF_ARM64_SP, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_SP_OFFSET %%\ 181 .cfi_escape DW_CFA_expression, DWARF_ARM64_PC, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_PC_OFFSET %%\ 182 .cfi_escape DW_CFA_expression, DWARF_ARM64_CPSR, DW_FORM_LEN_TWO_BYTE_SLEB, DW_OP_breg21, DWARF_ARM64_CPSR_OFFSET %%\ 183 184 #if CONFIG_SPTM 185 /** 186 * These offsets are SLEB128 encodings of the offsets of the FP, LR, SP, and PC 187 * members of the SPTM dispatch_panic_state_t structure defined in sptm/dispatch/dispatch.h 188 * 189 * If the offsets of these members are changed in SPTM data structures, they should be 190 * changed here to match accordingly. 191 */ 192 #define SPTM_UNWIND_DIRECTIVES \ 193 .cfi_escape DW_CFA_expression, DWARF_ARM64_FP, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, 0 %%\ 194 .cfi_escape DW_CFA_expression, DWARF_ARM64_LR, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, 8 %%\ 195 .cfi_escape DW_CFA_expression, DWARF_ARM64_SP, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, 16 %%\ 196 .cfi_escape DW_CFA_expression, DWARF_ARM64_PC, DW_FORM_LEN_ONE_BYTE_SLEB, DW_OP_breg21, 24 %%\ 197 198 #endif /* CONFIG_SPTM */ 199 200 /* Special unwinding instructions for `return_to_kernel`. 201 * 202 * We set the CFA, $fp and $lr the same as would be for the architecture default 203 * plan. 204 * We have to tell the unwinder that x21 is at x21, because it isn't aware 205 * we use it for the saved state. 206 * (i.e. it isn't used as a general purpose register / isn't volatile) 207 */ 208 #define RETURN_TO_KERNEL_UNWIND \ 209 .cfi_def_cfa w29, 16 %%\ 210 .cfi_escape DW_CFA_offset_extended_sf, DWARF_ARM64_FP, 2 %%\ 211 .cfi_escape DW_CFA_offset_extended_sf, DWARF_ARM64_LR, 1 %%\ 212 .cfi_escape DW_CFA_register, DWARF_ARM64_X21, DWARF_ARM64_X21 %%\ 213 214 #endif /* _ARM64_DWARF_UNWIND_H_ */ 215