1 /* 2 * Copyright (c) 2007-2021 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 32 #ifndef _ARM_MACHINE_ROUTINES_H_ 33 #define _ARM_MACHINE_ROUTINES_H_ 34 35 #include <mach/mach_types.h> 36 #include <mach/vm_types.h> 37 #include <mach/boolean.h> 38 #include <kern/kern_types.h> 39 #include <pexpert/pexpert.h> 40 41 #include <sys/cdefs.h> 42 #include <sys/appleapiopts.h> 43 44 #include <stdarg.h> 45 46 #ifdef XNU_KERNEL_PRIVATE 47 #include <kern/sched_hygiene.h> 48 #include <kern/startup.h> 49 #endif /* XNU_KERNEL_PRIVATE */ 50 51 __BEGIN_DECLS 52 #ifdef XNU_KERNEL_PRIVATE 53 #ifdef __arm64__ 54 typedef bool (*expected_fault_handler_t)(arm_saved_state_t *); 55 #endif /* __arm64__ */ 56 #endif /* XNU_KERNEL_PRIVATE */ 57 58 /* Interrupt handling */ 59 60 void ml_cpu_signal(unsigned int cpu_id); 61 void ml_cpu_signal_deferred_adjust_timer(uint64_t nanosecs); 62 uint64_t ml_cpu_signal_deferred_get_timer(void); 63 void ml_cpu_signal_deferred(unsigned int cpu_id); 64 void ml_cpu_signal_retract(unsigned int cpu_id); 65 bool ml_cpu_signal_is_enabled(void); 66 67 /* Initialize Interrupts */ 68 void ml_init_interrupt(void); 69 70 /* Get Interrupts Enabled */ 71 boolean_t ml_get_interrupts_enabled(void); 72 73 /* Set Interrupts Enabled */ 74 #if __has_feature(ptrauth_calls) 75 uint64_t ml_pac_safe_interrupts_disable(void); 76 void ml_pac_safe_interrupts_restore(uint64_t); 77 #endif /* __has_feature(ptrauth_calls) */ 78 boolean_t ml_set_interrupts_enabled_with_debug(boolean_t enable, boolean_t debug); 79 boolean_t ml_set_interrupts_enabled(boolean_t enable); 80 boolean_t ml_early_set_interrupts_enabled(boolean_t enable); 81 82 /* 83 * Functions for disabling measurements for AppleCLPC only. 84 */ 85 boolean_t sched_perfcontrol_ml_set_interrupts_without_measurement(boolean_t enable); 86 void sched_perfcontrol_abandon_preemption_disable_measurement(void); 87 88 /* Check if running at interrupt context */ 89 boolean_t ml_at_interrupt_context(void); 90 91 /* Generate a fake interrupt */ 92 void ml_cause_interrupt(void); 93 94 95 #ifdef XNU_KERNEL_PRIVATE 96 /* Clear interrupt spin debug state for thread */ 97 98 #if SCHED_HYGIENE_DEBUG 99 void ml_adjust_preemption_disable_time(thread_t thread, int64_t duration); 100 101 void mt_cur_cpu_cycles_instrs_speculative(uint64_t *cycles, uint64_t *instrs); 102 103 #if MONOTONIC 104 #define INTERRUPT_MASKED_DEBUG_CAPTURE_PMC(thread) \ 105 if (sched_hygiene_debug_pmc) { \ 106 mt_cur_cpu_cycles_instrs_speculative(&thread->machine.intmask_cycles, \ 107 &thread->machine.intmask_instr); \ 108 } 109 #else 110 #define INTERRUPT_MASKED_DEBUG_CAPTURE_PMC(thread) 111 #endif 112 113 #define INTERRUPT_MASKED_DEBUG_START(handler_addr, type) \ 114 do { \ 115 if ((interrupt_masked_debug_mode || sched_preemption_disable_debug_mode) && os_atomic_load(&interrupt_masked_timeout, relaxed) > 0) { \ 116 thread_t thread = current_thread(); \ 117 thread->machine.int_type = type; \ 118 thread->machine.int_handler_addr = (uintptr_t)VM_KERNEL_STRIP_UPTR(handler_addr); \ 119 thread->machine.inthandler_timestamp = ml_get_sched_hygiene_timebase(); \ 120 INTERRUPT_MASKED_DEBUG_CAPTURE_PMC(thread); \ 121 thread->machine.int_vector = (uintptr_t)NULL; \ 122 } \ 123 } while (0) 124 125 #define INTERRUPT_MASKED_DEBUG_END() \ 126 do { \ 127 if ((interrupt_masked_debug_mode || sched_preemption_disable_debug_mode) && os_atomic_load(&interrupt_masked_timeout, relaxed) > 0) { \ 128 thread_t thread = current_thread(); \ 129 ml_handle_interrupt_handler_duration(thread); \ 130 thread->machine.inthandler_timestamp = 0; \ 131 thread->machine.inthandler_abandon = false; \ 132 } \ 133 } while (0) 134 135 void ml_irq_debug_start(uintptr_t handler, uintptr_t vector); 136 void ml_irq_debug_end(void); 137 void ml_irq_debug_abandon(void); 138 139 void ml_spin_debug_reset(thread_t thread); 140 void ml_spin_debug_clear(thread_t thread); 141 void ml_spin_debug_clear_self(void); 142 void ml_handle_interrupts_disabled_duration(thread_t thread); 143 void ml_handle_stackshot_interrupt_disabled_duration(thread_t thread); 144 void ml_handle_interrupt_handler_duration(thread_t thread); 145 146 #else /* SCHED_HYGIENE_DEBUG */ 147 148 #define INTERRUPT_MASKED_DEBUG_START(handler_addr, type) 149 #define INTERRUPT_MASKED_DEBUG_END() 150 151 #endif /* SCHED_HYGIENE_DEBUG */ 152 153 extern bool ml_snoop_thread_is_on_core(thread_t thread); 154 extern boolean_t ml_is_quiescing(void); 155 extern void ml_set_is_quiescing(boolean_t); 156 extern uint64_t ml_get_booter_memory_size(void); 157 #endif 158 159 /* Type for the Time Base Enable function */ 160 typedef void (*time_base_enable_t)(cpu_id_t cpu_id, boolean_t enable); 161 #if defined(PEXPERT_KERNEL_PRIVATE) || defined(MACH_KERNEL_PRIVATE) 162 /* Type for the Processor Cache Dispatch function */ 163 typedef void (*cache_dispatch_t)(cpu_id_t cpu_id, unsigned int select, unsigned int param0, unsigned int param1); 164 165 typedef uint32_t (*get_decrementer_t)(void); 166 typedef void (*set_decrementer_t)(uint32_t); 167 typedef void (*fiq_handler_t)(void); 168 169 #endif 170 171 #define CacheConfig 0x00000000UL 172 #define CacheControl 0x00000001UL 173 #define CacheClean 0x00000002UL 174 #define CacheCleanRegion 0x00000003UL 175 #define CacheCleanFlush 0x00000004UL 176 #define CacheCleanFlushRegion 0x00000005UL 177 #define CacheShutdown 0x00000006UL 178 179 #define CacheControlEnable 0x00000000UL 180 181 #define CacheConfigCCSIDR 0x00000001UL 182 #define CacheConfigSize 0x00000100UL 183 184 /* Type for the Processor Idle function */ 185 typedef void (*processor_idle_t)(cpu_id_t cpu_id, boolean_t enter, uint64_t *new_timeout_ticks); 186 187 /* Type for the Idle Tickle function */ 188 typedef void (*idle_tickle_t)(void); 189 190 /* Type for the Idle Timer function */ 191 typedef void (*idle_timer_t)(void *refcon, uint64_t *new_timeout_ticks); 192 193 /* Type for the IPI Hander */ 194 typedef void (*ipi_handler_t)(void); 195 196 /* Type for the Lockdown Hander */ 197 typedef void (*lockdown_handler_t)(void *); 198 199 /* Type for the Platform specific Error Handler */ 200 typedef void (*platform_error_handler_t)(void *refcon, vm_offset_t fault_addr); 201 202 /* 203 * The exception callback (ex_cb) module allows kernel drivers to 204 * register and receive callbacks for exceptions, and indicate 205 * actions to be taken by the platform kernel 206 * Currently this is supported for ARM64 but extending support for ARM32 207 * should be straightforward 208 */ 209 210 /* Supported exception classes for callbacks */ 211 typedef enum{ 212 EXCB_CLASS_ILLEGAL_INSTR_SET, 213 #ifdef CONFIG_XNUPOST 214 EXCB_CLASS_TEST1, 215 EXCB_CLASS_TEST2, 216 EXCB_CLASS_TEST3, 217 #endif 218 EXCB_CLASS_MAX // this must be last 219 } 220 ex_cb_class_t; 221 222 /* Actions indicated by callbacks to be taken by platform kernel */ 223 typedef enum{ 224 EXCB_ACTION_RERUN, // re-run the faulting instruction 225 EXCB_ACTION_NONE, // continue normal exception handling 226 #ifdef CONFIG_XNUPOST 227 EXCB_ACTION_TEST_FAIL, 228 #endif 229 } 230 ex_cb_action_t; 231 232 /* 233 * Exception state 234 * We cannot use a private kernel data structure such as arm_saved_state_t 235 * The CPSR and ESR are not clobbered when the callback function is invoked so 236 * those registers can be examined by the callback function; 237 * the same is done in the platform error handlers 238 */ 239 typedef struct{ 240 vm_offset_t far; 241 } 242 ex_cb_state_t; 243 244 /* callback type definition */ 245 typedef ex_cb_action_t (*ex_cb_t) ( 246 ex_cb_class_t cb_class, 247 void *refcon,// provided at registration 248 const ex_cb_state_t *state // exception state 249 ); 250 251 /* 252 * Callback registration 253 * Currently we support only one registered callback per class but 254 * it should be possible to support more callbacks 255 */ 256 kern_return_t ex_cb_register( 257 ex_cb_class_t cb_class, 258 ex_cb_t cb, 259 void *refcon ); 260 261 /* 262 * Called internally by platform kernel to invoke the registered callback for class 263 */ 264 ex_cb_action_t ex_cb_invoke( 265 ex_cb_class_t cb_class, 266 vm_offset_t far); 267 268 typedef enum { 269 CLUSTER_TYPE_SMP, 270 CLUSTER_TYPE_E, 271 CLUSTER_TYPE_P, 272 MAX_CPU_TYPES, 273 } cluster_type_t; 274 275 void ml_parse_cpu_topology(void); 276 277 unsigned int ml_get_cpu_count(void); 278 279 unsigned int ml_get_cpu_number_type(cluster_type_t cluster_type, bool logical, bool available); 280 281 unsigned int ml_get_cluster_number_type(cluster_type_t cluster_type); 282 283 unsigned int ml_cpu_cache_sharing(unsigned int level, cluster_type_t cluster_type, bool include_all_cpu_types); 284 285 unsigned int ml_get_cpu_types(void); 286 287 unsigned int ml_get_cluster_count(void); 288 289 int ml_get_boot_cpu_number(void); 290 291 int ml_get_cpu_number(uint32_t phys_id); 292 293 unsigned int ml_get_cpu_number_local(void); 294 295 int ml_get_cluster_number(uint32_t phys_id); 296 297 int ml_get_max_cpu_number(void); 298 299 int ml_get_max_cluster_number(void); 300 301 /* 302 * Return the id of a cluster's first cpu. 303 */ 304 unsigned int ml_get_first_cpu_id(unsigned int cluster_id); 305 306 /* 307 * Return the die id of a cluster. 308 */ 309 unsigned int ml_get_die_id(unsigned int cluster_id); 310 311 /* 312 * Return the index of a cluster in its die. 313 */ 314 unsigned int ml_get_die_cluster_id(unsigned int cluster_id); 315 316 /* 317 * Return the highest die id of the system. 318 */ 319 unsigned int ml_get_max_die_id(void); 320 321 #ifdef __arm64__ 322 int ml_get_cluster_number_local(void); 323 #endif /* __arm64__ */ 324 325 /* Struct for ml_cpu_get_info */ 326 struct ml_cpu_info { 327 unsigned long vector_unit; 328 unsigned long cache_line_size; 329 unsigned long l1_icache_size; 330 unsigned long l1_dcache_size; 331 unsigned long l2_settings; 332 unsigned long l2_cache_size; 333 unsigned long l3_settings; 334 unsigned long l3_cache_size; 335 }; 336 typedef struct ml_cpu_info ml_cpu_info_t; 337 338 cluster_type_t ml_get_boot_cluster_type(void); 339 340 /*! 341 * @typedef ml_topology_cpu_t 342 * @brief Describes one CPU core in the topology. 343 * 344 * @field cpu_id Logical CPU ID (EDT: cpu-id): 0, 1, 2, 3, 4, ... 345 * @field phys_id Physical CPU ID (EDT: reg). Same as MPIDR[15:0], i.e. 346 * (cluster_id << 8) | core_number_within_cluster 347 * @field cluster_id Cluster ID (EDT: cluster-id) 348 * @field die_id Die ID (EDT: die-id) 349 * @field cluster_type The type of CPUs found in this cluster. 350 * @field l2_access_penalty Indicates that the scheduler should try to de-prioritize a core because 351 * L2 accesses are slower than on the boot processor. 352 * @field l2_cache_size Size of the L2 cache, in bytes. 0 if unknown or not present. 353 * @field l2_cache_id l2-cache-id property read from EDT. 354 * @field l3_cache_size Size of the L3 cache, in bytes. 0 if unknown or not present. 355 * @field l3_cache_id l3-cache-id property read from EDT. 356 * @field cpu_IMPL_regs IO-mapped virtual address of cpuX_IMPL (implementation-defined) register block. 357 * @field cpu_IMPL_pa Physical address of cpuX_IMPL register block. 358 * @field cpu_IMPL_len Length of cpuX_IMPL register block. 359 * @field cpu_UTTDBG_regs IO-mapped virtual address of cpuX_UTTDBG register block. 360 * @field cpu_UTTDBG_pa Physical address of cpuX_UTTDBG register block, if set in DT, else zero 361 * @field cpu_UTTDBG_len Length of cpuX_UTTDBG register block, if set in DT, else zero 362 * @field coresight_regs IO-mapped virtual address of CoreSight debug register block. 363 * @field coresight_pa Physical address of CoreSight register block. 364 * @field coresight_len Length of CoreSight register block. 365 * @field die_cluster_id Cluster ID within the local die (EDT: die-cluster-id) 366 * @field cluster_core_id Core ID within the local cluster (EDT: cluster-core-id) 367 */ 368 typedef struct ml_topology_cpu { 369 unsigned int cpu_id; 370 uint32_t phys_id; 371 unsigned int cluster_id; 372 unsigned int die_id; 373 cluster_type_t cluster_type; 374 uint32_t l2_access_penalty; 375 uint32_t l2_cache_size; 376 uint32_t l2_cache_id; 377 uint32_t l3_cache_size; 378 uint32_t l3_cache_id; 379 vm_offset_t cpu_IMPL_regs; 380 uint64_t cpu_IMPL_pa; 381 uint64_t cpu_IMPL_len; 382 vm_offset_t cpu_UTTDBG_regs; 383 uint64_t cpu_UTTDBG_pa; 384 uint64_t cpu_UTTDBG_len; 385 vm_offset_t coresight_regs; 386 uint64_t coresight_pa; 387 uint64_t coresight_len; 388 unsigned int die_cluster_id; 389 unsigned int cluster_core_id; 390 } ml_topology_cpu_t; 391 392 /*! 393 * @typedef ml_topology_cluster_t 394 * @brief Describes one cluster in the topology. 395 * 396 * @field cluster_id Cluster ID (EDT: cluster-id) 397 * @field cluster_type The type of CPUs found in this cluster. 398 * @field num_cpus Total number of usable CPU cores in this cluster. 399 * @field first_cpu_id The cpu_id of the first CPU in the cluster. 400 * @field cpu_mask A bitmask representing the cpu_id's that belong to the cluster. Example: 401 * If the cluster contains CPU4 and CPU5, cpu_mask will be 0x30. 402 * @field acc_IMPL_regs IO-mapped virtual address of acc_IMPL (implementation-defined) register block. 403 * @field acc_IMPL_pa Physical address of acc_IMPL register block. 404 * @field acc_IMPL_len Length of acc_IMPL register block. 405 * @field cpm_IMPL_regs IO-mapped virtual address of cpm_IMPL (implementation-defined) register block. 406 * @field cpm_IMPL_pa Physical address of cpm_IMPL register block. 407 * @field cpm_IMPL_len Length of cpm_IMPL register block. 408 */ 409 typedef struct ml_topology_cluster { 410 unsigned int cluster_id; 411 cluster_type_t cluster_type; 412 unsigned int num_cpus; 413 unsigned int first_cpu_id; 414 uint64_t cpu_mask; 415 vm_offset_t acc_IMPL_regs; 416 uint64_t acc_IMPL_pa; 417 uint64_t acc_IMPL_len; 418 vm_offset_t cpm_IMPL_regs; 419 uint64_t cpm_IMPL_pa; 420 uint64_t cpm_IMPL_len; 421 } ml_topology_cluster_t; 422 423 // Bump this version number any time any ml_topology_* struct changes, so 424 // that KPI users can check whether their headers are compatible with 425 // the running kernel. 426 #define CPU_TOPOLOGY_VERSION 1 427 428 /*! 429 * @typedef ml_topology_info_t 430 * @brief Describes the CPU topology for all APs in the system. Populated from EDT and read-only at runtime. 431 * @discussion This struct only lists CPU cores that are considered usable by both iBoot and XNU. Some 432 * physically present CPU cores may be considered unusable due to configuration options like 433 * the "cpus=" boot-arg. Cores that are disabled in hardware will not show up in EDT at all, so 434 * they also will not be present in this struct. 435 * 436 * @field version Version of the struct (set to CPU_TOPOLOGY_VERSION). 437 * @field num_cpus Total number of usable CPU cores. 438 * @field max_cpu_id The highest usable logical CPU ID. 439 * @field num_clusters Total number of AP CPU clusters on the system (usable or not). 440 * @field max_cluster_id The highest cluster ID found in EDT. 441 * @field cpus List of |num_cpus| entries. 442 * @field clusters List of |num_clusters| entries. 443 * @field boot_cpu Points to the |cpus| entry for the boot CPU. 444 * @field boot_cluster Points to the |clusters| entry which contains the boot CPU. 445 * @field chip_revision Silicon revision reported by iBoot, which comes from the 446 * SoC-specific fuse bits. See CPU_VERSION_xx macros for definitions. 447 */ 448 typedef struct ml_topology_info { 449 unsigned int version; 450 unsigned int num_cpus; 451 unsigned int max_cpu_id; 452 unsigned int num_clusters; 453 unsigned int max_cluster_id; 454 unsigned int max_die_id; 455 ml_topology_cpu_t *cpus; 456 ml_topology_cluster_t *clusters; 457 ml_topology_cpu_t *boot_cpu; 458 ml_topology_cluster_t *boot_cluster; 459 unsigned int chip_revision; 460 unsigned int cluster_types; 461 unsigned int cluster_type_num_cpus[MAX_CPU_TYPES]; 462 unsigned int cluster_type_num_clusters[MAX_CPU_TYPES]; 463 } ml_topology_info_t; 464 465 /*! 466 * @function ml_get_topology_info 467 * @result A pointer to the read-only topology struct. Does not need to be freed. Returns NULL 468 * if the struct hasn't been initialized or the feature is unsupported. 469 */ 470 const ml_topology_info_t *ml_get_topology_info(void); 471 472 /*! 473 * @function ml_map_cpu_pio 474 * @brief Maps per-CPU and per-cluster PIO registers found in EDT. This needs to be 475 * called after arm_vm_init() so it can't be part of ml_parse_cpu_topology(). 476 */ 477 void ml_map_cpu_pio(void); 478 479 /* Struct for ml_processor_register */ 480 struct ml_processor_info { 481 cpu_id_t cpu_id; 482 vm_offset_t start_paddr; 483 boolean_t supports_nap; 484 void *platform_cache_dispatch; 485 time_base_enable_t time_base_enable; 486 processor_idle_t processor_idle; 487 idle_tickle_t *idle_tickle; 488 idle_timer_t idle_timer; 489 void *idle_timer_refcon; 490 vm_offset_t powergate_stub_addr; 491 uint32_t powergate_stub_length; 492 uint32_t powergate_latency; 493 platform_error_handler_t platform_error_handler; 494 uint64_t regmap_paddr; 495 uint32_t phys_id; 496 uint32_t log_id; 497 uint32_t l2_access_penalty; 498 uint32_t cluster_id; 499 cluster_type_t cluster_type; 500 uint32_t l2_cache_id; 501 uint32_t l2_cache_size; 502 uint32_t l3_cache_id; 503 uint32_t l3_cache_size; 504 }; 505 typedef struct ml_processor_info ml_processor_info_t; 506 507 #if defined(PEXPERT_KERNEL_PRIVATE) || defined(MACH_KERNEL_PRIVATE) 508 /* Struct for ml_init_timebase */ 509 struct tbd_ops { 510 fiq_handler_t tbd_fiq_handler; 511 get_decrementer_t tbd_get_decrementer; 512 set_decrementer_t tbd_set_decrementer; 513 }; 514 typedef struct tbd_ops *tbd_ops_t; 515 typedef struct tbd_ops tbd_ops_data_t; 516 #endif 517 518 519 /*! 520 * @function ml_processor_register 521 * 522 * @abstract callback from platform kext to register processor 523 * 524 * @discussion This function is called by the platform kext when a processor is 525 * being registered. This is called while running on the CPU itself, as part of 526 * its initialization. 527 * 528 * @param ml_processor_info provides machine-specific information about the 529 * processor to xnu. 530 * 531 * @param processor is set as an out-parameter to an opaque handle that should 532 * be used by the platform kext when referring to this processor in the future. 533 * 534 * @param ipi_handler is set as an out-parameter to the function that should be 535 * registered as the IPI handler. 536 * 537 * @param pmi_handler is set as an out-parameter to the function that should be 538 * registered as the PMI handler. 539 * 540 * @returns KERN_SUCCESS on success and an error code, otherwise. 541 */ 542 kern_return_t ml_processor_register(ml_processor_info_t *ml_processor_info, 543 processor_t *processor, ipi_handler_t *ipi_handler, 544 perfmon_interrupt_handler_func *pmi_handler); 545 546 /* Register a lockdown handler */ 547 kern_return_t ml_lockdown_handler_register(lockdown_handler_t, void *); 548 549 /* Register a M$ flushing */ 550 typedef kern_return_t (*mcache_flush_function)(void *service); 551 kern_return_t ml_mcache_flush_callback_register(mcache_flush_function func, void *service); 552 kern_return_t ml_mcache_flush(void); 553 554 #if XNU_KERNEL_PRIVATE 555 void ml_lockdown_init(void); 556 557 /* Machine layer routine for intercepting panics */ 558 __printflike(1, 0) 559 void ml_panic_trap_to_debugger(const char *panic_format_str, 560 va_list *panic_args, 561 unsigned int reason, 562 void *ctx, 563 uint64_t panic_options_mask, 564 unsigned long panic_caller); 565 #endif /* XNU_KERNEL_PRIVATE */ 566 567 /* Initialize Interrupts */ 568 void ml_install_interrupt_handler( 569 void *nub, 570 int source, 571 void *target, 572 IOInterruptHandler handler, 573 void *refCon); 574 575 vm_offset_t 576 ml_static_vtop( 577 vm_offset_t); 578 579 kern_return_t 580 ml_static_verify_page_protections( 581 uint64_t base, uint64_t size, vm_prot_t prot); 582 583 vm_offset_t 584 ml_static_ptovirt( 585 vm_offset_t); 586 587 /* Offset required to obtain absolute time value from tick counter */ 588 uint64_t ml_get_abstime_offset(void); 589 590 /* Offset required to obtain continuous time value from tick counter */ 591 uint64_t ml_get_conttime_offset(void); 592 593 #ifdef __APPLE_API_UNSTABLE 594 /* PCI config cycle probing */ 595 boolean_t ml_probe_read( 596 vm_offset_t paddr, 597 unsigned int *val); 598 boolean_t ml_probe_read_64( 599 addr64_t paddr, 600 unsigned int *val); 601 602 /* Read physical address byte */ 603 unsigned int ml_phys_read_byte( 604 vm_offset_t paddr); 605 unsigned int ml_phys_read_byte_64( 606 addr64_t paddr); 607 608 /* Read physical address half word */ 609 unsigned int ml_phys_read_half( 610 vm_offset_t paddr); 611 unsigned int ml_phys_read_half_64( 612 addr64_t paddr); 613 614 /* Read physical address word*/ 615 unsigned int ml_phys_read( 616 vm_offset_t paddr); 617 unsigned int ml_phys_read_64( 618 addr64_t paddr); 619 unsigned int ml_phys_read_word( 620 vm_offset_t paddr); 621 unsigned int ml_phys_read_word_64( 622 addr64_t paddr); 623 624 /* Read physical address double word */ 625 unsigned long long ml_phys_read_double( 626 vm_offset_t paddr); 627 unsigned long long ml_phys_read_double_64( 628 addr64_t paddr); 629 630 /* Write physical address byte */ 631 void ml_phys_write_byte( 632 vm_offset_t paddr, unsigned int data); 633 void ml_phys_write_byte_64( 634 addr64_t paddr, unsigned int data); 635 636 /* Write physical address half word */ 637 void ml_phys_write_half( 638 vm_offset_t paddr, unsigned int data); 639 void ml_phys_write_half_64( 640 addr64_t paddr, unsigned int data); 641 642 /* Write physical address word */ 643 void ml_phys_write( 644 vm_offset_t paddr, unsigned int data); 645 void ml_phys_write_64( 646 addr64_t paddr, unsigned int data); 647 void ml_phys_write_word( 648 vm_offset_t paddr, unsigned int data); 649 void ml_phys_write_word_64( 650 addr64_t paddr, unsigned int data); 651 652 /* Write physical address double word */ 653 void ml_phys_write_double( 654 vm_offset_t paddr, unsigned long long data); 655 void ml_phys_write_double_64( 656 addr64_t paddr, unsigned long long data); 657 658 void ml_static_mfree( 659 vm_offset_t, 660 vm_size_t); 661 662 kern_return_t 663 ml_static_protect( 664 vm_offset_t start, 665 vm_size_t size, 666 vm_prot_t new_prot); 667 668 typedef int ml_page_protection_t; 669 670 /* Return the type of page protection supported */ 671 ml_page_protection_t ml_page_protection_type(void); 672 673 /* virtual to physical on wired pages */ 674 vm_offset_t ml_vtophys( 675 vm_offset_t vaddr); 676 677 /* Get processor cache info */ 678 void ml_cpu_get_info(ml_cpu_info_t *ml_cpu_info); 679 void ml_cpu_get_info_type(ml_cpu_info_t * ml_cpu_info, cluster_type_t cluster_type); 680 681 #endif /* __APPLE_API_UNSTABLE */ 682 683 #ifdef __APPLE_API_PRIVATE 684 #ifdef XNU_KERNEL_PRIVATE 685 vm_size_t ml_nofault_copy( 686 vm_offset_t virtsrc, 687 vm_offset_t virtdst, 688 vm_size_t size); 689 boolean_t ml_validate_nofault( 690 vm_offset_t virtsrc, vm_size_t size); 691 #endif /* XNU_KERNEL_PRIVATE */ 692 #if defined(PEXPERT_KERNEL_PRIVATE) || defined(MACH_KERNEL_PRIVATE) 693 /* IO memory map services */ 694 695 extern vm_offset_t io_map( 696 vm_map_offset_t phys_addr, 697 vm_size_t size, 698 unsigned int flags, 699 vm_prot_t prot, 700 bool unmappable); 701 702 /* Map memory map IO space */ 703 vm_offset_t ml_io_map( 704 vm_offset_t phys_addr, 705 vm_size_t size); 706 707 vm_offset_t ml_io_map_wcomb( 708 vm_offset_t phys_addr, 709 vm_size_t size); 710 711 vm_offset_t ml_io_map_unmappable( 712 vm_offset_t phys_addr, 713 vm_size_t size, 714 uint32_t flags); 715 716 vm_offset_t ml_io_map_with_prot( 717 vm_offset_t phys_addr, 718 vm_size_t size, 719 vm_prot_t prot); 720 721 void ml_io_unmap( 722 vm_offset_t addr, 723 vm_size_t sz); 724 725 void ml_get_bouncepool_info( 726 vm_offset_t *phys_addr, 727 vm_size_t *size); 728 729 vm_map_address_t ml_map_high_window( 730 vm_offset_t phys_addr, 731 vm_size_t len); 732 733 void ml_init_timebase( 734 void *args, 735 tbd_ops_t tbd_funcs, 736 vm_offset_t int_address, 737 vm_offset_t int_value); 738 739 uint64_t ml_get_timebase(void); 740 741 #if MACH_KERNEL_PRIVATE 742 void ml_memory_to_timebase_fence(void); 743 void ml_timebase_to_memory_fence(void); 744 #endif /* MACH_KERNEL_PRIVATE */ 745 746 uint64_t ml_get_speculative_timebase(void); 747 748 uint64_t ml_get_timebase_entropy(void); 749 750 boolean_t ml_delay_should_spin(uint64_t interval); 751 752 void ml_delay_on_yield(void); 753 754 uint32_t ml_get_decrementer(void); 755 756 #include <machine/config.h> 757 758 uint64_t ml_get_hwclock(void); 759 760 #ifdef __arm64__ 761 boolean_t ml_get_timer_pending(void); 762 #endif 763 764 void platform_syscall( 765 struct arm_saved_state *); 766 767 void ml_set_decrementer( 768 uint32_t dec_value); 769 770 boolean_t is_user_contex( 771 void); 772 773 void ml_init_arm_debug_interface(void *args, vm_offset_t virt_address); 774 775 /* These calls are only valid if __ARM_USER_PROTECT__ is defined */ 776 uintptr_t arm_user_protect_begin( 777 thread_t thread); 778 779 void arm_user_protect_end( 780 thread_t thread, 781 uintptr_t up, 782 boolean_t disable_interrupts); 783 784 #endif /* PEXPERT_KERNEL_PRIVATE || MACH_KERNEL_PRIVATE */ 785 786 /* Zero bytes starting at a physical address */ 787 void bzero_phys( 788 addr64_t phys_address, 789 vm_size_t length); 790 791 void bzero_phys_nc(addr64_t src64, vm_size_t bytes); 792 793 #if MACH_KERNEL_PRIVATE 794 #ifdef __arm64__ 795 /* Pattern-fill buffer with zeros or a 32-bit pattern; 796 * target must be 128-byte aligned and sized a multiple of 128 797 * Both variants emit stores with non-temporal properties. 798 */ 799 void fill32_dczva(addr64_t, vm_size_t); 800 void fill32_nt(addr64_t, vm_size_t, uint32_t); 801 bool cpu_interrupt_is_pending(void); 802 #endif 803 #endif 804 805 void ml_thread_policy( 806 thread_t thread, 807 unsigned policy_id, 808 unsigned policy_info); 809 810 #define MACHINE_GROUP 0x00000001 811 #define MACHINE_NETWORK_GROUP 0x10000000 812 #define MACHINE_NETWORK_WORKLOOP 0x00000001 813 #define MACHINE_NETWORK_NETISR 0x00000002 814 815 /* Set the maximum number of CPUs */ 816 void ml_set_max_cpus( 817 unsigned int max_cpus); 818 819 /* Return the maximum number of CPUs set by ml_set_max_cpus(), waiting if necessary */ 820 unsigned int ml_wait_max_cpus( 821 void); 822 823 /* Return the maximum memory size */ 824 unsigned int ml_get_machine_mem(void); 825 826 #ifdef XNU_KERNEL_PRIVATE 827 /* Return max offset */ 828 vm_map_offset_t ml_get_max_offset( 829 boolean_t is64, 830 unsigned int option); 831 #define MACHINE_MAX_OFFSET_DEFAULT 0x01 832 #define MACHINE_MAX_OFFSET_MIN 0x02 833 #define MACHINE_MAX_OFFSET_MAX 0x04 834 #define MACHINE_MAX_OFFSET_DEVICE 0x08 835 #endif 836 837 extern void ml_cpu_init_completed(void); 838 extern void ml_cpu_up(void); 839 extern void ml_cpu_down(void); 840 /* 841 * The update to CPU counts needs to be separate from other actions 842 * in ml_cpu_up() and ml_cpu_down() 843 * because we don't update the counts when CLPC causes temporary 844 * cluster powerdown events, as these must be transparent to the user. 845 */ 846 extern void ml_cpu_up_update_counts(int cpu_id); 847 extern void ml_cpu_down_update_counts(int cpu_id); 848 extern void ml_arm_sleep(void); 849 850 extern uint64_t ml_get_wake_timebase(void); 851 extern uint64_t ml_get_conttime_wake_time(void); 852 853 /* Time since the system was reset (as part of boot/wake) */ 854 uint64_t ml_get_time_since_reset(void); 855 856 /* 857 * Called by ApplePMGR to set wake time. Units and epoch are identical 858 * to mach_continuous_time(). Has no effect on !HAS_CONTINUOUS_HWCLOCK 859 * chips. If wake_time == UINT64_MAX, that means the wake time is 860 * unknown and calls to ml_get_time_since_reset() will return UINT64_MAX. 861 */ 862 void ml_set_reset_time(uint64_t wake_time); 863 864 #ifdef XNU_KERNEL_PRIVATE 865 /* Just a stub on ARM */ 866 extern kern_return_t ml_interrupt_prewarm(uint64_t deadline); 867 #define TCOAL_DEBUG(x, a, b, c, d, e) do { } while(0) 868 #endif /* XNU_KERNEL_PRIVATE */ 869 870 /* Bytes available on current stack */ 871 vm_offset_t ml_stack_remaining(void); 872 873 #ifdef MACH_KERNEL_PRIVATE 874 uint32_t get_fpscr(void); 875 void set_fpscr(uint32_t); 876 void machine_conf(void); 877 void machine_lockdown(void); 878 879 #ifdef __arm64__ 880 unsigned long update_mdscr(unsigned long clear, unsigned long set); 881 #endif /* __arm64__ */ 882 883 extern void arm_debug_set_cp14(arm_debug_state_t *debug_state); 884 extern void fiq_context_init(boolean_t enable_fiq); 885 886 extern void reenable_async_aborts(void); 887 888 #ifdef __arm64__ 889 uint64_t ml_cluster_wfe_timeout(uint32_t wfe_cluster_id); 890 #endif 891 892 #ifdef MONITOR 893 #define MONITOR_SET_ENTRY 0x800 /* Set kernel entry point from monitor */ 894 #define MONITOR_LOCKDOWN 0x801 /* Enforce kernel text/rodata integrity */ 895 unsigned long monitor_call(uintptr_t callnum, uintptr_t arg1, 896 uintptr_t arg2, uintptr_t arg3); 897 #endif /* MONITOR */ 898 899 #if __ARM_KERNEL_PROTECT__ 900 extern void set_vbar_el1(uint64_t); 901 #endif /* __ARM_KERNEL_PROTECT__ */ 902 #endif /* MACH_KERNEL_PRIVATE */ 903 904 extern uint32_t arm_debug_read_dscr(void); 905 906 extern int set_be_bit(void); 907 extern int clr_be_bit(void); 908 extern int be_tracing(void); 909 910 /* Please note that cpu_broadcast_xcall is not as simple is you would like it to be. 911 * It will sometimes put the calling thread to sleep, and it is up to your callback 912 * to wake it up as needed, where "as needed" is defined as "all other CPUs have 913 * called the broadcast func". Look around the kernel for examples, or instead use 914 * cpu_broadcast_xcall_simple() which does indeed act like you would expect, given 915 * the prototype. cpu_broadcast_immediate_xcall has the same caveats and has a similar 916 * _simple() wrapper 917 */ 918 typedef void (*broadcastFunc) (void *); 919 unsigned int cpu_broadcast_xcall(uint32_t *, boolean_t, broadcastFunc, void *); 920 unsigned int cpu_broadcast_xcall_simple(boolean_t, broadcastFunc, void *); 921 __result_use_check kern_return_t cpu_xcall(int, broadcastFunc, void *); 922 unsigned int cpu_broadcast_immediate_xcall(uint32_t *, boolean_t, broadcastFunc, void *); 923 unsigned int cpu_broadcast_immediate_xcall_simple(boolean_t, broadcastFunc, void *); 924 __result_use_check kern_return_t cpu_immediate_xcall(int, broadcastFunc, void *); 925 926 #ifdef KERNEL_PRIVATE 927 928 /* Interface to be used by the perf. controller to register a callback, in a 929 * single-threaded fashion. The callback will receive notifications of 930 * processor performance quality-of-service changes from the scheduler. 931 */ 932 933 #ifdef __arm64__ 934 typedef void (*cpu_qos_update_t)(int throughput_qos, uint64_t qos_param1, uint64_t qos_param2); 935 void cpu_qos_update_register(cpu_qos_update_t); 936 #endif /* __arm64__ */ 937 938 struct going_on_core { 939 uint64_t thread_id; 940 uint16_t qos_class; 941 uint16_t urgency; /* XCPM compatibility */ 942 uint32_t is_32_bit : 1; /* uses 32-bit ISA/register state in userspace (which may differ from address space size) */ 943 uint32_t is_kernel_thread : 1; 944 uint64_t thread_group_id; 945 void *thread_group_data; 946 uint64_t scheduling_latency; /* absolute time between when thread was made runnable and this ctx switch */ 947 uint64_t start_time; 948 uint64_t scheduling_latency_at_same_basepri; 949 uint32_t energy_estimate_nj; /* return: In nanojoules */ 950 /* smaller of the time between last change to base priority and ctx switch and scheduling_latency */ 951 }; 952 typedef struct going_on_core *going_on_core_t; 953 954 struct going_off_core { 955 uint64_t thread_id; 956 uint32_t energy_estimate_nj; /* return: In nanojoules */ 957 uint32_t reserved; 958 uint64_t end_time; 959 uint64_t thread_group_id; 960 void *thread_group_data; 961 }; 962 typedef struct going_off_core *going_off_core_t; 963 964 struct thread_group_data { 965 uint64_t thread_group_id; 966 void *thread_group_data; 967 uint32_t thread_group_size; 968 uint32_t thread_group_flags; 969 }; 970 typedef struct thread_group_data *thread_group_data_t; 971 972 struct perfcontrol_max_runnable_latency { 973 uint64_t max_scheduling_latencies[4 /* THREAD_URGENCY_MAX */]; 974 }; 975 typedef struct perfcontrol_max_runnable_latency *perfcontrol_max_runnable_latency_t; 976 977 struct perfcontrol_work_interval { 978 uint64_t thread_id; 979 uint16_t qos_class; 980 uint16_t urgency; 981 uint32_t flags; // notify 982 uint64_t work_interval_id; 983 uint64_t start; 984 uint64_t finish; 985 uint64_t deadline; 986 uint64_t next_start; 987 uint64_t thread_group_id; 988 void *thread_group_data; 989 uint32_t create_flags; 990 }; 991 typedef struct perfcontrol_work_interval *perfcontrol_work_interval_t; 992 993 typedef enum { 994 WORK_INTERVAL_START, 995 WORK_INTERVAL_UPDATE, 996 WORK_INTERVAL_FINISH 997 } work_interval_ctl_t; 998 999 struct perfcontrol_work_interval_instance { 1000 work_interval_ctl_t ctl; 1001 uint32_t create_flags; 1002 uint64_t complexity; 1003 uint64_t thread_id; 1004 uint64_t work_interval_id; 1005 uint64_t instance_id; /* out: start, in: update/finish */ 1006 uint64_t start; 1007 uint64_t finish; 1008 uint64_t deadline; 1009 uint64_t thread_group_id; 1010 void *thread_group_data; 1011 }; 1012 typedef struct perfcontrol_work_interval_instance *perfcontrol_work_interval_instance_t; 1013 1014 /* 1015 * Structure to export per-CPU counters as part of the CLPC callout. 1016 * Contains only the fixed CPU counters (instructions and cycles); CLPC 1017 * would call back into XNU to get the configurable counters if needed. 1018 */ 1019 struct perfcontrol_cpu_counters { 1020 uint64_t instructions; 1021 uint64_t cycles; 1022 }; 1023 1024 __options_decl(perfcontrol_thread_flags_mask_t, uint64_t, { 1025 PERFCTL_THREAD_FLAGS_MASK_CLUSTER_SHARED_RSRC_RR = 1 << 0, 1026 PERFCTL_THREAD_FLAGS_MASK_CLUSTER_SHARED_RSRC_NATIVE_FIRST = 1 << 1, 1027 }); 1028 1029 1030 /* 1031 * Structure used to pass information about a thread to CLPC 1032 */ 1033 struct perfcontrol_thread_data { 1034 /* 1035 * Energy estimate (return value) 1036 * The field is populated by CLPC and used to update the 1037 * energy estimate of the thread 1038 */ 1039 uint32_t energy_estimate_nj; 1040 /* Perfcontrol class for thread */ 1041 perfcontrol_class_t perfctl_class; 1042 /* Thread ID for the thread */ 1043 uint64_t thread_id; 1044 /* Thread Group ID */ 1045 uint64_t thread_group_id; 1046 /* 1047 * Scheduling latency for threads at the same base priority. 1048 * Calculated by the scheduler and passed into CLPC. The field is 1049 * populated only in the thread_data structure for the thread 1050 * going on-core. 1051 */ 1052 uint64_t scheduling_latency_at_same_basepri; 1053 /* Thread Group data pointer */ 1054 void *thread_group_data; 1055 /* perfctl state pointer */ 1056 void *perfctl_state; 1057 /* Bitmask to indicate which thread flags have been updated as part of the callout */ 1058 perfcontrol_thread_flags_mask_t thread_flags_mask; 1059 /* Actual values for the flags that are getting updated in the callout */ 1060 perfcontrol_thread_flags_mask_t thread_flags; 1061 }; 1062 1063 /* 1064 * All callouts from the scheduler are executed with interrupts 1065 * disabled. Callouts should be implemented in C with minimal 1066 * abstractions, and only use KPI exported by the mach/libkern 1067 * symbolset, restricted to routines like spinlocks and atomic 1068 * operations and scheduler routines as noted below. Spinlocks that 1069 * are used to synchronize data in the perfcontrol_state_t should only 1070 * ever be acquired with interrupts disabled, to avoid deadlocks where 1071 * an quantum expiration timer interrupt attempts to perform a callout 1072 * that attempts to lock a spinlock that is already held. 1073 */ 1074 1075 /* 1076 * When a processor is switching between two threads (after the 1077 * scheduler has chosen a new thread), the low-level platform layer 1078 * will call this routine, which should perform required timestamps, 1079 * MMIO register reads, or other state switching. No scheduler locks 1080 * are held during this callout. 1081 * 1082 * This function is called with interrupts ENABLED. 1083 */ 1084 typedef void (*sched_perfcontrol_context_switch_t)(perfcontrol_state_t, perfcontrol_state_t); 1085 1086 /* 1087 * Once the processor has switched to the new thread, the offcore 1088 * callout will indicate the old thread that is no longer being 1089 * run. The thread's scheduler lock is held, so it will not begin 1090 * running on another processor (in the case of preemption where it 1091 * remains runnable) until it completes. If the "thread_terminating" 1092 * boolean is TRUE, this will be the last callout for this thread_id. 1093 */ 1094 typedef void (*sched_perfcontrol_offcore_t)(perfcontrol_state_t, going_off_core_t /* populated by callee */, boolean_t); 1095 1096 /* 1097 * After the offcore callout and after the old thread can potentially 1098 * start running on another processor, the oncore callout will be 1099 * called with the thread's scheduler lock held. The oncore callout is 1100 * also called any time one of the parameters in the going_on_core_t 1101 * structure changes, like priority/QoS changes, and quantum 1102 * expiration, so the callout must not assume callouts are paired with 1103 * offcore callouts. 1104 */ 1105 typedef void (*sched_perfcontrol_oncore_t)(perfcontrol_state_t, going_on_core_t); 1106 1107 /* 1108 * Periodically (on hundreds of ms scale), the scheduler will perform 1109 * maintenance and report the maximum latency for runnable (but not currently 1110 * running) threads for each urgency class. 1111 */ 1112 typedef void (*sched_perfcontrol_max_runnable_latency_t)(perfcontrol_max_runnable_latency_t); 1113 1114 /* 1115 * When the kernel receives information about work intervals from userland, 1116 * it is passed along using this callback. No locks are held, although the state 1117 * object will not go away during the callout. 1118 */ 1119 typedef void (*sched_perfcontrol_work_interval_notify_t)(perfcontrol_state_t, perfcontrol_work_interval_t); 1120 1121 /* 1122 * Start, update and finish work interval instance with optional complexity estimate. 1123 */ 1124 typedef void (*sched_perfcontrol_work_interval_ctl_t)(perfcontrol_state_t, perfcontrol_work_interval_instance_t); 1125 1126 /* 1127 * These callbacks are used when thread groups are added, removed or properties 1128 * updated. 1129 * No blocking allocations (or anything else blocking) are allowed inside these 1130 * callbacks. No locks allowed in these callbacks as well since the kernel might 1131 * be holding the thread/task locks. 1132 */ 1133 typedef void (*sched_perfcontrol_thread_group_init_t)(thread_group_data_t); 1134 typedef void (*sched_perfcontrol_thread_group_deinit_t)(thread_group_data_t); 1135 typedef void (*sched_perfcontrol_thread_group_flags_update_t)(thread_group_data_t); 1136 1137 /* 1138 * Sometime after the timeout set by sched_perfcontrol_update_callback_deadline has passed, 1139 * this function will be called, passing the timeout deadline that was previously armed as an argument. 1140 * 1141 * This is called inside context-switch/quantum-interrupt context and must follow the safety rules for that context. 1142 */ 1143 typedef void (*sched_perfcontrol_deadline_passed_t)(uint64_t deadline); 1144 1145 /* 1146 * Context Switch Callout 1147 * 1148 * Parameters: 1149 * event - The perfcontrol_event for this callout 1150 * cpu_id - The CPU doing the context switch 1151 * timestamp - The timestamp for the context switch 1152 * flags - Flags for other relevant information 1153 * offcore - perfcontrol_data structure for thread going off-core 1154 * oncore - perfcontrol_data structure for thread going on-core 1155 * cpu_counters - perfcontrol_cpu_counters for the CPU doing the switch 1156 */ 1157 typedef void (*sched_perfcontrol_csw_t)( 1158 perfcontrol_event event, uint32_t cpu_id, uint64_t timestamp, uint32_t flags, 1159 struct perfcontrol_thread_data *offcore, struct perfcontrol_thread_data *oncore, 1160 struct perfcontrol_cpu_counters *cpu_counters, __unused void *unused); 1161 1162 1163 /* 1164 * Thread State Update Callout 1165 * 1166 * Parameters: 1167 * event - The perfcontrol_event for this callout 1168 * cpu_id - The CPU doing the state update 1169 * timestamp - The timestamp for the state update 1170 * flags - Flags for other relevant information 1171 * thr_data - perfcontrol_data structure for the thread being updated 1172 */ 1173 typedef void (*sched_perfcontrol_state_update_t)( 1174 perfcontrol_event event, uint32_t cpu_id, uint64_t timestamp, uint32_t flags, 1175 struct perfcontrol_thread_data *thr_data, __unused void *unused); 1176 1177 /* 1178 * Thread Group Blocking Relationship Callout 1179 * 1180 * Parameters: 1181 * blocked_tg - Thread group blocking on progress of another thread group 1182 * blocking_tg - Thread group blocking progress of another thread group 1183 * flags - Flags for other relevant information 1184 * blocked_thr_state - Per-thread perfcontrol state for blocked thread 1185 */ 1186 typedef void (*sched_perfcontrol_thread_group_blocked_t)( 1187 thread_group_data_t blocked_tg, thread_group_data_t blocking_tg, uint32_t flags, perfcontrol_state_t blocked_thr_state); 1188 1189 /* 1190 * Thread Group Unblocking Callout 1191 * 1192 * Parameters: 1193 * unblocked_tg - Thread group being unblocked from making forward progress 1194 * unblocking_tg - Thread group unblocking progress of another thread group 1195 * flags - Flags for other relevant information 1196 * unblocked_thr_state - Per-thread perfcontrol state for unblocked thread 1197 */ 1198 typedef void (*sched_perfcontrol_thread_group_unblocked_t)( 1199 thread_group_data_t unblocked_tg, thread_group_data_t unblocking_tg, uint32_t flags, perfcontrol_state_t unblocked_thr_state); 1200 1201 /* 1202 * Callers should always use the CURRENT version so that the kernel can detect both older 1203 * and newer structure layouts. New callbacks should always be added at the end of the 1204 * structure, and xnu should expect existing source recompiled against newer headers 1205 * to pass NULL for unimplemented callbacks. Pass NULL as the as the callbacks parameter 1206 * to reset callbacks to their default in-kernel values. 1207 */ 1208 1209 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_0 (0) /* up-to oncore */ 1210 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_1 (1) /* up-to max_runnable_latency */ 1211 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_2 (2) /* up-to work_interval_notify */ 1212 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_3 (3) /* up-to thread_group_deinit */ 1213 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_4 (4) /* up-to deadline_passed */ 1214 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_5 (5) /* up-to state_update */ 1215 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_6 (6) /* up-to thread_group_flags_update */ 1216 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_7 (7) /* up-to work_interval_ctl */ 1217 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_8 (8) /* up-to thread_group_unblocked */ 1218 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_9 (9) /* allows CLPC to specify resource contention flags */ 1219 #define SCHED_PERFCONTROL_CALLBACKS_VERSION_CURRENT SCHED_PERFCONTROL_CALLBACKS_VERSION_6 1220 1221 struct sched_perfcontrol_callbacks { 1222 unsigned long version; /* Use SCHED_PERFCONTROL_CALLBACKS_VERSION_CURRENT */ 1223 sched_perfcontrol_offcore_t offcore; 1224 sched_perfcontrol_context_switch_t context_switch; 1225 sched_perfcontrol_oncore_t oncore; 1226 sched_perfcontrol_max_runnable_latency_t max_runnable_latency; 1227 sched_perfcontrol_work_interval_notify_t work_interval_notify; 1228 sched_perfcontrol_thread_group_init_t thread_group_init; 1229 sched_perfcontrol_thread_group_deinit_t thread_group_deinit; 1230 sched_perfcontrol_deadline_passed_t deadline_passed; 1231 sched_perfcontrol_csw_t csw; 1232 sched_perfcontrol_state_update_t state_update; 1233 sched_perfcontrol_thread_group_flags_update_t thread_group_flags_update; 1234 sched_perfcontrol_work_interval_ctl_t work_interval_ctl; 1235 sched_perfcontrol_thread_group_blocked_t thread_group_blocked; 1236 sched_perfcontrol_thread_group_unblocked_t thread_group_unblocked; 1237 }; 1238 typedef struct sched_perfcontrol_callbacks *sched_perfcontrol_callbacks_t; 1239 1240 extern void sched_perfcontrol_register_callbacks(sched_perfcontrol_callbacks_t callbacks, unsigned long size_of_state); 1241 extern void sched_perfcontrol_thread_group_recommend(void *data, cluster_type_t recommendation); 1242 extern void sched_perfcontrol_inherit_recommendation_from_tg(perfcontrol_class_t perfctl_class, boolean_t inherit); 1243 extern const char* sched_perfcontrol_thread_group_get_name(void *data); 1244 1245 /* 1246 * Edge Scheduler-CLPC Interface 1247 * 1248 * sched_perfcontrol_thread_group_preferred_clusters_set() 1249 * 1250 * The Edge scheduler expects thread group recommendations to be specific clusters rather 1251 * than just E/P. In order to allow more fine grained control, CLPC can specify an override 1252 * preferred cluster per QoS bucket. CLPC passes a common preferred cluster `tg_preferred_cluster` 1253 * and an array of size [PERFCONTROL_CLASS_MAX] with overrides for specific perfctl classes. 1254 * The scheduler translates these preferences into sched_bucket 1255 * preferences and applies the changes. 1256 * 1257 */ 1258 /* Token to indicate a particular perfctl class is not overriden */ 1259 #define SCHED_PERFCONTROL_PREFERRED_CLUSTER_OVERRIDE_NONE ((uint32_t)~0) 1260 1261 /* 1262 * CLPC can also indicate if there should be an immediate rebalancing of threads of this TG as 1263 * part of this preferred cluster change. It does that by specifying the following options. 1264 */ 1265 #define SCHED_PERFCONTROL_PREFERRED_CLUSTER_MIGRATE_RUNNING 0x1 1266 #define SCHED_PERFCONTROL_PREFERRED_CLUSTER_MIGRATE_RUNNABLE 0x2 1267 typedef uint64_t sched_perfcontrol_preferred_cluster_options_t; 1268 1269 extern void sched_perfcontrol_thread_group_preferred_clusters_set(void *machine_data, uint32_t tg_preferred_cluster, 1270 uint32_t overrides[PERFCONTROL_CLASS_MAX], sched_perfcontrol_preferred_cluster_options_t options); 1271 1272 /* 1273 * Edge Scheduler-CLPC Interface 1274 * 1275 * sched_perfcontrol_edge_matrix_get()/sched_perfcontrol_edge_matrix_set() 1276 * 1277 * The Edge scheduler uses edges between clusters to define the likelihood of migrating threads 1278 * across clusters. The edge config between any two clusters defines the edge weight and whether 1279 * migation and steal operations are allowed across that edge. The getter and setter allow CLPC 1280 * to query and configure edge properties between various clusters on the platform. 1281 */ 1282 1283 extern void sched_perfcontrol_edge_matrix_get(sched_clutch_edge *edge_matrix, bool *edge_request_bitmap, uint64_t flags, uint64_t matrix_order); 1284 extern void sched_perfcontrol_edge_matrix_set(sched_clutch_edge *edge_matrix, bool *edge_changes_bitmap, uint64_t flags, uint64_t matrix_order); 1285 1286 /* 1287 * Update the deadline after which sched_perfcontrol_deadline_passed will be called. 1288 * Returns TRUE if it successfully canceled a previously set callback, 1289 * and FALSE if it did not (i.e. one wasn't set, or callback already fired / is in flight). 1290 * The callback is automatically canceled when it fires, and does not repeat unless rearmed. 1291 * 1292 * This 'timer' executes as the scheduler switches between threads, on a non-idle core 1293 * 1294 * There can be only one outstanding timer globally. 1295 */ 1296 extern boolean_t sched_perfcontrol_update_callback_deadline(uint64_t deadline); 1297 1298 /* 1299 * SFI configuration. 1300 */ 1301 extern kern_return_t sched_perfcontrol_sfi_set_window(uint64_t window_usecs); 1302 extern kern_return_t sched_perfcontrol_sfi_set_bg_offtime(uint64_t offtime_usecs); 1303 extern kern_return_t sched_perfcontrol_sfi_set_utility_offtime(uint64_t offtime_usecs); 1304 1305 typedef enum perfcontrol_callout_type { 1306 PERFCONTROL_CALLOUT_ON_CORE, 1307 PERFCONTROL_CALLOUT_OFF_CORE, 1308 PERFCONTROL_CALLOUT_CONTEXT, 1309 PERFCONTROL_CALLOUT_STATE_UPDATE, 1310 /* Add other callout types here */ 1311 PERFCONTROL_CALLOUT_MAX 1312 } perfcontrol_callout_type_t; 1313 1314 typedef enum perfcontrol_callout_stat { 1315 PERFCONTROL_STAT_INSTRS, 1316 PERFCONTROL_STAT_CYCLES, 1317 /* Add other stat types here */ 1318 PERFCONTROL_STAT_MAX 1319 } perfcontrol_callout_stat_t; 1320 1321 uint64_t perfcontrol_callout_stat_avg(perfcontrol_callout_type_t type, 1322 perfcontrol_callout_stat_t stat); 1323 1324 #ifdef __arm64__ 1325 /* The performance controller may use this interface to recommend 1326 * that CPUs in the designated cluster employ WFE rather than WFI 1327 * within the idle loop, falling back to WFI after the specified 1328 * timeout. The updates are expected to be serialized by the caller, 1329 * the implementation is not required to perform internal synchronization. 1330 */ 1331 uint32_t ml_update_cluster_wfe_recommendation(uint32_t wfe_cluster_id, uint64_t wfe_timeout_abstime_interval, uint64_t wfe_hint_flags); 1332 #endif /* __arm64__ */ 1333 1334 #if defined(HAS_APPLE_PAC) 1335 #define ONES(x) (BIT((x))-1) 1336 #define PTR_MASK ONES(64-T1SZ_BOOT) 1337 #define PAC_MASK ~PTR_MASK 1338 #define SIGN(p) ((p) & BIT(55)) 1339 #define UNSIGN_PTR(p) \ 1340 SIGN(p) ? ((p) | PAC_MASK) : ((p) & ~PAC_MASK) 1341 1342 uint64_t ml_default_rop_pid(void); 1343 uint64_t ml_default_jop_pid(void); 1344 void ml_task_set_rop_pid(task_t task, task_t parent_task, boolean_t inherit); 1345 void ml_task_set_jop_pid(task_t task, task_t parent_task, boolean_t inherit); 1346 void ml_task_set_jop_pid_from_shared_region(task_t task); 1347 void ml_task_set_disable_user_jop(task_t task, uint8_t disable_user_jop); 1348 void ml_thread_set_disable_user_jop(thread_t thread, uint8_t disable_user_jop); 1349 void ml_thread_set_jop_pid(thread_t thread, task_t task); 1350 void *ml_auth_ptr_unchecked(void *ptr, unsigned key, uint64_t modifier); 1351 1352 uint64_t ml_enable_user_jop_key(uint64_t user_jop_key); 1353 1354 /** 1355 * Restores the previous JOP key state after a previous ml_enable_user_jop_key() 1356 * call. 1357 * 1358 * @param user_jop_key The userspace JOP key previously passed to 1359 * ml_enable_user_jop_key() 1360 * @param saved_jop_state The saved JOP state returned by 1361 * ml_enable_user_jop_key() 1362 */ 1363 void ml_disable_user_jop_key(uint64_t user_jop_key, uint64_t saved_jop_state); 1364 #endif /* defined(HAS_APPLE_PAC) */ 1365 1366 void ml_enable_monitor(void); 1367 1368 #endif /* KERNEL_PRIVATE */ 1369 1370 boolean_t machine_timeout_suspended(void); 1371 void ml_get_power_state(boolean_t *, boolean_t *); 1372 1373 uint32_t get_arm_cpu_version(void); 1374 boolean_t user_cont_hwclock_allowed(void); 1375 uint8_t user_timebase_type(void); 1376 boolean_t ml_thread_is64bit(thread_t thread); 1377 1378 #ifdef __arm64__ 1379 bool ml_feature_supported(uint32_t feature_bit); 1380 void ml_set_align_checking(void); 1381 extern void wfe_timeout_configure(void); 1382 extern void wfe_timeout_init(void); 1383 #endif /* __arm64__ */ 1384 1385 void ml_timer_evaluate(void); 1386 boolean_t ml_timer_forced_evaluation(void); 1387 void ml_gpu_stat_update(uint64_t); 1388 uint64_t ml_gpu_stat(thread_t); 1389 #endif /* __APPLE_API_PRIVATE */ 1390 1391 1392 1393 #if __arm64__ && defined(CONFIG_XNUPOST) && defined(XNU_KERNEL_PRIVATE) 1394 extern void ml_expect_fault_begin(expected_fault_handler_t, uintptr_t); 1395 extern void ml_expect_fault_end(void); 1396 #endif /* __arm64__ && defined(CONFIG_XNUPOST) && defined(XNU_KERNEL_PRIVATE) */ 1397 1398 1399 extern uint32_t phy_read_panic; 1400 extern uint32_t phy_write_panic; 1401 #if DEVELOPMENT || DEBUG 1402 extern uint64_t simulate_stretched_io; 1403 #endif 1404 1405 void ml_hibernate_active_pre(void); 1406 void ml_hibernate_active_post(void); 1407 1408 void ml_report_minor_badness(uint32_t badness_id); 1409 #define ML_MINOR_BADNESS_CONSOLE_BUFFER_FULL 0 1410 #define ML_MINOR_BADNESS_MEMFAULT_REPORTING_NOT_ENABLED 1 1411 #define ML_MINOR_BADNESS_PIO_WRITTEN_FROM_USERSPACE 2 1412 1413 #ifdef XNU_KERNEL_PRIVATE 1414 /** 1415 * Depending on the system, by the time a backtracer starts inspecting an 1416 * interrupted CPU's register state, the value of the PC might have been 1417 * modified. In those cases, the original PC value is placed into a different 1418 * register. This function abstracts out those differences for a backtracer 1419 * wanting the PC of an interrupted CPU. 1420 * 1421 * @param state The ARM register state to parse. 1422 * 1423 * @return The original PC of the interrupted CPU. 1424 */ 1425 uint64_t ml_get_backtrace_pc(struct arm_saved_state *state); 1426 #endif /* XNU_KERNEL_PRIVATE */ 1427 1428 __END_DECLS 1429 1430 #endif /* _ARM_MACHINE_ROUTINES_H_ */ 1431