1 /*
2 * Copyright (c) 2007-2011 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 #include <kern/zalloc.h>
30 #include <mach/mach_time.h>
31 #include <i386/cpu_data.h>
32 #include <i386/cpuid.h>
33 #include <i386/cpu_topology.h>
34 #include <i386/cpu_threads.h>
35 #include <i386/lapic.h>
36 #include <i386/machine_cpu.h>
37 #include <i386/machine_check.h>
38 #include <i386/proc_reg.h>
39
40 /*
41 * At the time of the machine-check exception, all hardware-threads panic.
42 * Each thread saves the state of its MCA registers to its per-cpu data area.
43 *
44 * State reporting is serialized so one thread dumps all valid state for all
45 * threads to the panic log. This may entail spinning waiting for other
46 * threads to complete saving state to memory. A timeout applies to this wait
47 * -- in particular, a 3-strikes timeout may prevent a thread from taking
48 * part is the affair.
49 */
50
51 #define IF(bool, str) ((bool) ? (str) : "")
52
53 static boolean_t mca_initialized = FALSE;
54 static boolean_t mca_MCE_present = FALSE;
55 static boolean_t mca_MCA_present = FALSE;
56 static uint32_t mca_family = 0;
57 static unsigned int mca_error_bank_count = 0;
58 static boolean_t mca_control_MSR_present = FALSE;
59 static boolean_t mca_cmci_present = FALSE;
60 static ia32_mcg_cap_t ia32_mcg_cap;
61 decl_simple_lock_data(static, mca_lock);
62
63 typedef struct {
64 ia32_mci_ctl_t mca_mci_ctl;
65 ia32_mci_status_t mca_mci_status;
66 ia32_mci_misc_t mca_mci_misc;
67 ia32_mci_addr_t mca_mci_addr;
68 } mca_mci_bank_t;
69
70 typedef struct mca_state {
71 boolean_t mca_is_saved;
72 boolean_t mca_is_valid; /* some state is valid */
73 ia32_mcg_ctl_t mca_mcg_ctl;
74 ia32_mcg_status_t mca_mcg_status;
75 mca_mci_bank_t mca_error_bank[0];
76 } mca_state_t;
77
78 typedef enum {
79 CLEAR,
80 DUMPING,
81 DUMPED
82 } mca_dump_state_t;
83 static volatile mca_dump_state_t mca_dump_state = CLEAR;
84
85 static void
mca_get_availability(void)86 mca_get_availability(void)
87 {
88 uint64_t features = cpuid_info()->cpuid_features;
89 uint32_t family = cpuid_info()->cpuid_family;
90 uint32_t model = cpuid_info()->cpuid_model;
91 uint32_t stepping = cpuid_info()->cpuid_stepping;
92
93 if (family == 6 &&
94 ((model == CPUID_MODEL_HASWELL && stepping < 3) ||
95 (model == CPUID_MODEL_HASWELL_ULT && stepping < 1) ||
96 (model == CPUID_MODEL_CRYSTALWELL && stepping < 1))) {
97 panic("Haswell pre-C0 steppings are not supported");
98 }
99
100 mca_MCE_present = (features & CPUID_FEATURE_MCE) != 0;
101 mca_MCA_present = (features & CPUID_FEATURE_MCA) != 0;
102 mca_family = family;
103
104 /*
105 * If MCA, the number of banks etc is reported by the IA32_MCG_CAP MSR.
106 */
107 if (mca_MCA_present) {
108 ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
109 mca_error_bank_count = ia32_mcg_cap.bits.count;
110 mca_control_MSR_present = ia32_mcg_cap.bits.mcg_ctl_p;
111 mca_cmci_present = ia32_mcg_cap.bits.mcg_ext_corr_err_p;
112 }
113 }
114
115 void
mca_cpu_init(void)116 mca_cpu_init(void)
117 {
118 unsigned int i;
119
120 /*
121 * The first (boot) processor is responsible for discovering the
122 * machine check architecture present on this machine.
123 */
124 if (!mca_initialized) {
125 mca_get_availability();
126 mca_initialized = TRUE;
127 simple_lock_init(&mca_lock, 0);
128 }
129
130 if (mca_MCA_present) {
131 /* Enable all MCA features */
132 if (mca_control_MSR_present) {
133 wrmsr64(IA32_MCG_CTL, IA32_MCG_CTL_ENABLE);
134 }
135
136 switch (mca_family) {
137 case 0x06:
138 /* Enable all but mc0 */
139 for (i = 1; i < mca_error_bank_count; i++) {
140 wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL);
141 }
142
143 /* Clear all errors */
144 for (i = 0; i < mca_error_bank_count; i++) {
145 wrmsr64(IA32_MCi_STATUS(i), 0ULL);
146 }
147 break;
148 default:
149 /* Enable all banks */
150 for (i = 0; i < mca_error_bank_count; i++) {
151 wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL);
152 }
153
154 /* Clear all errors */
155 for (i = 0; i < mca_error_bank_count; i++) {
156 wrmsr64(IA32_MCi_STATUS(i), 0ULL);
157 }
158 break;
159 }
160 }
161
162 /* Enable machine check exception handling if available */
163 if (mca_MCE_present) {
164 set_cr4(get_cr4() | CR4_MCE);
165 }
166 }
167
168 boolean_t
mca_is_cmci_present(void)169 mca_is_cmci_present(void)
170 {
171 if (!mca_initialized) {
172 mca_cpu_init();
173 }
174 return mca_cmci_present;
175 }
176
177 void
mca_cpu_alloc(cpu_data_t * cdp)178 mca_cpu_alloc(cpu_data_t *cdp)
179 {
180 vm_size_t mca_state_size;
181
182 /*
183 * Allocate space for an array of error banks.
184 */
185 mca_state_size = sizeof(mca_state_t) +
186 sizeof(mca_mci_bank_t) * mca_error_bank_count;
187 cdp->cpu_mca_state = zalloc_permanent_tag(mca_state_size, ZALIGN_PTR,
188 VM_KERN_MEMORY_CPU);
189 if (cdp->cpu_mca_state == NULL) {
190 printf("mca_cpu_alloc() failed for cpu %d\n", cdp->cpu_number);
191 return;
192 }
193
194 /*
195 * If the boot processor is yet have its allocation made,
196 * do this now.
197 */
198 if (cpu_datap(master_cpu)->cpu_mca_state == NULL) {
199 mca_cpu_alloc(cpu_datap(master_cpu));
200 }
201 }
202
203 static void
mca_save_state(mca_state_t * mca_state)204 mca_save_state(mca_state_t *mca_state)
205 {
206 mca_mci_bank_t *bank;
207 unsigned int i;
208
209 assert(!ml_get_interrupts_enabled() || get_preemption_level() > 0);
210
211 if (mca_state == NULL) {
212 return;
213 }
214
215 mca_state->mca_mcg_ctl = mca_control_MSR_present ?
216 rdmsr64(IA32_MCG_CTL) : 0ULL;
217 mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);
218
219 bank = (mca_mci_bank_t *) &mca_state->mca_error_bank[0];
220 for (i = 0; i < mca_error_bank_count; i++, bank++) {
221 bank->mca_mci_ctl = rdmsr64(IA32_MCi_CTL(i));
222 bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));
223 if (!bank->mca_mci_status.bits.val) {
224 continue;
225 }
226 bank->mca_mci_misc = (bank->mca_mci_status.bits.miscv)?
227 rdmsr64(IA32_MCi_MISC(i)) : 0ULL;
228 bank->mca_mci_addr = (bank->mca_mci_status.bits.addrv)?
229 rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;
230 mca_state->mca_is_valid = TRUE;
231 }
232
233 /*
234 * If we're the first thread with MCA state, point our package to it
235 * and don't care about races
236 */
237 if (x86_package()->mca_state == NULL) {
238 x86_package()->mca_state = mca_state;
239 }
240
241 mca_state->mca_is_saved = TRUE;
242 }
243
244 void
mca_check_save(void)245 mca_check_save(void)
246 {
247 if (mca_dump_state > CLEAR) {
248 mca_save_state(current_cpu_datap()->cpu_mca_state);
249 }
250 }
251
252 static void
mca_report_cpu_info(void)253 mca_report_cpu_info(void)
254 {
255 i386_cpu_info_t *infop = cpuid_info();
256
257 paniclog_append_noflush(" family: %d model: %d stepping: %d microcode: %d\n",
258 infop->cpuid_family,
259 infop->cpuid_model,
260 infop->cpuid_stepping,
261 infop->cpuid_microcode_version);
262 paniclog_append_noflush(" signature: 0x%x\n",
263 infop->cpuid_signature);
264 paniclog_append_noflush(" %s\n",
265 infop->cpuid_brand_string);
266 }
267
268 static void
mca_dump_bank(mca_state_t * state,int i)269 mca_dump_bank(mca_state_t *state, int i)
270 {
271 mca_mci_bank_t *bank;
272 ia32_mci_status_t status;
273
274 bank = &state->mca_error_bank[i];
275 status = bank->mca_mci_status;
276 if (!status.bits.val) {
277 return;
278 }
279
280 paniclog_append_noflush(" IA32_MC%d_STATUS(0x%x): 0x%016qx\n",
281 i, IA32_MCi_STATUS(i), status.u64);
282
283 if (status.bits.addrv) {
284 paniclog_append_noflush(" IA32_MC%d_ADDR(0x%x): 0x%016qx\n",
285 i, IA32_MCi_ADDR(i), bank->mca_mci_addr);
286 }
287
288 if (status.bits.miscv) {
289 paniclog_append_noflush(" IA32_MC%d_MISC(0x%x): 0x%016qx\n",
290 i, IA32_MCi_MISC(i), bank->mca_mci_misc);
291 }
292 }
293
294 static void
mca_cpu_dump_error_banks(mca_state_t * state)295 mca_cpu_dump_error_banks(mca_state_t *state)
296 {
297 unsigned int i;
298
299 if (!state->mca_is_valid) {
300 return;
301 }
302
303 for (i = 0; i < mca_error_bank_count; i++) {
304 mca_dump_bank(state, i);
305 }
306 }
307
308 void
mca_dump(void)309 mca_dump(void)
310 {
311 mca_state_t *mca_state = current_cpu_datap()->cpu_mca_state;
312 uint64_t deadline;
313 unsigned int i = 0;
314
315 /*
316 * Capture local MCA registers to per-cpu data.
317 */
318 mca_save_state(mca_state);
319
320 /*
321 * Serialize: the first caller controls dumping MCA registers,
322 * other threads spin meantime.
323 */
324 simple_lock(&mca_lock, LCK_GRP_NULL);
325 if (mca_dump_state > CLEAR) {
326 simple_unlock(&mca_lock);
327 while (mca_dump_state == DUMPING) {
328 cpu_pause();
329 }
330 return;
331 }
332 mca_dump_state = DUMPING;
333 simple_unlock(&mca_lock);
334
335 /*
336 * Wait for all other hardware threads to save their state.
337 * Or timeout.
338 */
339 deadline = mach_absolute_time() + LockTimeOut;
340 while (mach_absolute_time() < deadline && i < real_ncpus) {
341 if (!cpu_datap(i)->cpu_mca_state->mca_is_saved) {
342 cpu_pause();
343 continue;
344 }
345 i += 1;
346 }
347
348 /*
349 * Report machine-check capabilities:
350 */
351 paniclog_append_noflush("Machine-check capabilities: 0x%016qx\n", ia32_mcg_cap.u64);
352
353 mca_report_cpu_info();
354
355 paniclog_append_noflush(" %d error-reporting banks\n", mca_error_bank_count);
356
357 /*
358 * Dump all processor state:
359 */
360 for (i = 0; i < real_ncpus; i++) {
361 mca_state_t *mcsp = cpu_datap(i)->cpu_mca_state;
362 ia32_mcg_status_t status;
363
364 if (mcsp == NULL ||
365 mcsp->mca_is_saved == FALSE ||
366 mcsp->mca_mcg_status.u64 == 0 ||
367 !mcsp->mca_is_valid) {
368 continue;
369 }
370 status = mcsp->mca_mcg_status;
371 paniclog_append_noflush("Processor %d: IA32_MCG_STATUS: 0x%016qx\n",
372 i, status.u64);
373 mca_cpu_dump_error_banks(mcsp);
374 }
375
376 /* Update state to release any other threads. */
377 mca_dump_state = DUMPED;
378 }
379
380
381 #if DEVELOPMENT || DEBUG
382 extern void mca_exception_panic(void);
383 extern void lapic_trigger_MC(void);
384 void
mca_exception_panic(void)385 mca_exception_panic(void)
386 {
387 lapic_trigger_MC();
388 }
389 #endif
390