1 /*
2 * Copyright (c) 2003-2021 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989, 1988 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or [email protected]
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56
57
58 #include <mach/i386/vm_param.h>
59
60 #include <string.h>
61 #include <stdint.h>
62 #include <mach/vm_param.h>
63 #include <mach/vm_prot.h>
64 #include <mach/machine.h>
65 #include <mach/time_value.h>
66 #include <kern/spl.h>
67 #include <kern/assert.h>
68 #include <kern/debug.h>
69 #include <kern/misc_protos.h>
70 #include <kern/startup.h>
71 #include <kern/clock.h>
72 #include <kern/pms.h>
73 #include <kern/cpu_data.h>
74 #include <kern/processor.h>
75 #include <sys/kdebug.h>
76 #include <console/serial_protos.h>
77 #include <vm/vm_page.h>
78 #include <vm/pmap.h>
79 #include <vm/vm_kern.h>
80 #include <machine/pal_routines.h>
81 #include <i386/fpu.h>
82 #include <i386/pmap.h>
83 #include <i386/misc_protos.h>
84 #include <i386/cpu_threads.h>
85 #include <i386/cpuid.h>
86 #include <i386/lapic.h>
87 #include <i386/mp.h>
88 #include <i386/mp_desc.h>
89 #if CONFIG_MTRR
90 #include <i386/mtrr.h>
91 #endif
92 #include <i386/machine_routines.h>
93 #if CONFIG_MCA
94 #include <i386/machine_check.h>
95 #endif
96 #include <i386/ucode.h>
97 #include <i386/postcode.h>
98 #include <i386/Diagnostics.h>
99 #include <i386/pmCPU.h>
100 #include <i386/tsc.h>
101 #include <i386/acpi.h>
102 #if DEBUG
103 #include <machine/pal_routines.h>
104 #endif
105 extern void xcpm_bootstrap(void);
106 #if DEVELOPMENT || DEBUG
107 #include <i386/trap.h>
108 #endif
109
110 #if MONOTONIC
111 #include <kern/monotonic.h>
112 #endif /* MONOTONIC */
113
114 #if KPERF
115 #include <kperf/kptimer.h>
116 #endif /* KPERF */
117
118 #include <san/kasan.h>
119
120 #if DEBUG || DEVELOPMENT
121 #define DBG(x, ...) kprintf(x, ##__VA_ARGS__)
122 #define dyldLogFunc(x, ...) kprintf(x, ##__VA_ARGS__)
123 #else
124 #define DBG(x ...)
125 #endif
126
127 #include <libkern/kernel_mach_header.h>
128 #include <mach/dyld_kernel_fixups.h>
129
130
131 int debug_task;
132
133 int early_boot = 1;
134
135 bool serial_console_enabled = false;
136
137 static boot_args *kernelBootArgs;
138
139 extern int disableConsoleOutput;
140 extern const char version[];
141 extern const char version_variant[];
142 extern int nx_enabled;
143
144 /*
145 * Set initial values so that ml_phys_* routines can use the booter's ID mapping
146 * to touch physical space before the kernel's physical aperture exists.
147 */
148 uint64_t physmap_base = 0;
149 uint64_t physmap_max = 4 * GB;
150
151 pd_entry_t *KPTphys;
152 pd_entry_t *IdlePTD;
153 pdpt_entry_t *IdlePDPT;
154 pml4_entry_t *IdlePML4;
155
156 int kernPhysPML4Index;
157 int kernPhysPML4EntryCount;
158
159 /*
160 * These are 4K mapping page table pages from KPTphys[] that we wound
161 * up not using. They get ml_static_mfree()'d once the VM is initialized.
162 */
163 ppnum_t released_PT_ppn = 0;
164 uint32_t released_PT_cnt = 0;
165
166 #if DEVELOPMENT || DEBUG
167 int panic_on_cacheline_mismatch = -1;
168 char panic_on_trap_procname[64];
169 uint32_t panic_on_trap_mask;
170 #endif
171 lbr_modes_t last_branch_enabled_modes;
172 int insn_copyin_count;
173 #if DEVELOPMENT || DEBUG
174 #define DEFAULT_INSN_COPYIN_COUNT x86_INSTRUCTION_STATE_MAX_INSN_BYTES
175 #else
176 #define DEFAULT_INSN_COPYIN_COUNT 192
177 #endif
178
179 char *physfree;
180 void idt64_remap(void);
181
182 /*
183 * Note: ALLOCPAGES() can only be used safely within Idle_PTs_init()
184 * due to the mutation of physfree.
185 */
186 static void *
ALLOCPAGES(int npages)187 ALLOCPAGES(int npages)
188 {
189 uintptr_t tmp = (uintptr_t)physfree;
190 bzero(physfree, npages * PAGE_SIZE);
191 physfree += npages * PAGE_SIZE;
192 tmp += VM_MIN_KERNEL_ADDRESS & ~LOW_4GB_MASK;
193 return (void *)tmp;
194 }
195
196 static void
fillkpt(pt_entry_t * base,int prot,uintptr_t src,int index,int count)197 fillkpt(pt_entry_t *base, int prot, uintptr_t src, int index, int count)
198 {
199 int i;
200 for (i = 0; i < count; i++) {
201 base[index] = src | prot | INTEL_PTE_VALID;
202 src += PAGE_SIZE;
203 index++;
204 }
205 }
206
207 extern pmap_paddr_t first_avail;
208
209 int break_kprintf = 0;
210
211 uint64_t
x86_64_pre_sleep(void)212 x86_64_pre_sleep(void)
213 {
214 IdlePML4[0] = IdlePML4[KERNEL_PML4_INDEX];
215 uint64_t oldcr3 = get_cr3_raw();
216 set_cr3_raw((uint32_t) (uintptr_t)ID_MAP_VTOP(IdlePML4));
217 return oldcr3;
218 }
219
220 void
x86_64_post_sleep(uint64_t new_cr3)221 x86_64_post_sleep(uint64_t new_cr3)
222 {
223 IdlePML4[0] = 0;
224 set_cr3_raw((uint32_t) new_cr3);
225 }
226
227
228
229
230 // Set up the physical mapping - NPHYSMAP GB of memory mapped at a high address
231 // NPHYSMAP is determined by the maximum supported RAM size plus 4GB to account
232 // the PCI hole (which is less 4GB but not more).
233
234 static int
physmap_init_L2(uint64_t * physStart,pt_entry_t ** l2ptep)235 physmap_init_L2(uint64_t *physStart, pt_entry_t **l2ptep)
236 {
237 unsigned i;
238 pt_entry_t *physmapL2 = ALLOCPAGES(1);
239
240 if (physmapL2 == NULL) {
241 DBG("physmap_init_L2 page alloc failed when initting L2 for physAddr 0x%llx.\n", *physStart);
242 *l2ptep = NULL;
243 return -1;
244 }
245
246 for (i = 0; i < NPDPG; i++) {
247 physmapL2[i] = *physStart
248 | INTEL_PTE_PS
249 | INTEL_PTE_VALID
250 | INTEL_PTE_NX
251 | INTEL_PTE_WRITE;
252
253 *physStart += NBPD;
254 }
255 *l2ptep = physmapL2;
256 return 0;
257 }
258
259 static int
physmap_init_L3(int startIndex,uint64_t highest_phys,uint64_t * physStart,pt_entry_t ** l3ptep)260 physmap_init_L3(int startIndex, uint64_t highest_phys, uint64_t *physStart, pt_entry_t **l3ptep)
261 {
262 unsigned i;
263 int ret;
264 pt_entry_t *l2pte;
265 pt_entry_t *physmapL3 = ALLOCPAGES(1); /* ALLOCPAGES bzeroes the memory */
266
267 if (physmapL3 == NULL) {
268 DBG("physmap_init_L3 page alloc failed when initting L3 for physAddr 0x%llx.\n", *physStart);
269 *l3ptep = NULL;
270 return -1;
271 }
272
273 for (i = startIndex; i < NPDPTPG && *physStart < highest_phys; i++) {
274 if ((ret = physmap_init_L2(physStart, &l2pte)) < 0) {
275 return ret;
276 }
277
278 physmapL3[i] = ((uintptr_t)ID_MAP_VTOP(l2pte))
279 | INTEL_PTE_VALID
280 | INTEL_PTE_NX
281 | INTEL_PTE_WRITE;
282 }
283
284 *l3ptep = physmapL3;
285
286 return 0;
287 }
288
289 static void
physmap_init(uint8_t phys_random_L3,uint64_t * new_physmap_base,uint64_t * new_physmap_max)290 physmap_init(uint8_t phys_random_L3, uint64_t *new_physmap_base, uint64_t *new_physmap_max)
291 {
292 pt_entry_t *l3pte;
293 int pml4_index, i;
294 int L3_start_index;
295 uint64_t physAddr = 0;
296 uint64_t highest_physaddr;
297 unsigned pdpte_count;
298
299 #if DEVELOPMENT || DEBUG
300 if (kernelBootArgs->PhysicalMemorySize > K64_MAXMEM) {
301 panic("Installed physical memory exceeds configured maximum.");
302 }
303 #endif
304
305 /*
306 * Add 4GB to the loader-provided physical memory size to account for MMIO space
307 * XXX in a perfect world, we'd scan PCI buses and count the max memory requested in BARs by
308 * XXX all enumerated device, then add more for hot-pluggable devices.
309 */
310 highest_physaddr = kernelBootArgs->PhysicalMemorySize + 4 * GB;
311
312 /*
313 * Calculate the number of PML4 entries we'll need. The total number of entries is
314 * pdpte_count = (((highest_physaddr) >> PDPT_SHIFT) + entropy_value +
315 * ((highest_physaddr & PDPT_MASK) == 0 ? 0 : 1))
316 * pml4e_count = pdpte_count >> (PML4_SHIFT - PDPT_SHIFT)
317 */
318 assert(highest_physaddr < (UINT64_MAX - PDPTMASK));
319 pdpte_count = (unsigned) (((highest_physaddr + PDPTMASK) >> PDPTSHIFT) + phys_random_L3);
320 kernPhysPML4EntryCount = (pdpte_count + ((1U << (PML4SHIFT - PDPTSHIFT)) - 1)) >> (PML4SHIFT - PDPTSHIFT);
321 if (kernPhysPML4EntryCount == 0) {
322 kernPhysPML4EntryCount = 1;
323 }
324 if (kernPhysPML4EntryCount > KERNEL_PHYSMAP_PML4_COUNT_MAX) {
325 #if DEVELOPMENT || DEBUG
326 panic("physmap too large");
327 #else
328 kprintf("[pmap] Limiting physmap to %d PML4s (was %d)\n", KERNEL_PHYSMAP_PML4_COUNT_MAX,
329 kernPhysPML4EntryCount);
330 kernPhysPML4EntryCount = KERNEL_PHYSMAP_PML4_COUNT_MAX;
331 #endif
332 }
333
334 kernPhysPML4Index = KERNEL_KEXTS_INDEX - kernPhysPML4EntryCount; /* utb: KERNEL_PHYSMAP_PML4_INDEX */
335
336 /*
337 * XXX: Make sure that the addresses returned for physmapL3 and physmapL2 plus their extents
338 * are in the system-available memory range
339 */
340
341
342 /* We assume NX support. Mark all levels of the PHYSMAP NX
343 * to avoid granting executability via a single bit flip.
344 */
345 #if DEVELOPMENT || DEBUG
346 uint32_t reg[4];
347 do_cpuid(0x80000000, reg);
348 if (reg[eax] >= 0x80000001) {
349 do_cpuid(0x80000001, reg);
350 assert(reg[edx] & CPUID_EXTFEATURE_XD);
351 }
352 #endif /* DEVELOPMENT || DEBUG */
353
354 L3_start_index = phys_random_L3;
355
356 for (pml4_index = kernPhysPML4Index;
357 pml4_index < (kernPhysPML4Index + kernPhysPML4EntryCount) && physAddr < highest_physaddr;
358 pml4_index++) {
359 if (physmap_init_L3(L3_start_index, highest_physaddr, &physAddr, &l3pte) < 0) {
360 panic("Physmap page table initialization failed");
361 /* NOTREACHED */
362 }
363
364 L3_start_index = 0;
365
366 IdlePML4[pml4_index] = ((uintptr_t)ID_MAP_VTOP(l3pte))
367 | INTEL_PTE_VALID
368 | INTEL_PTE_NX
369 | INTEL_PTE_WRITE;
370 }
371
372 *new_physmap_base = KVADDR(kernPhysPML4Index, phys_random_L3, 0, 0);
373 /*
374 * physAddr contains the last-mapped physical address, so that's what we
375 * add to physmap_base to derive the ending VA for the physmap.
376 */
377 *new_physmap_max = *new_physmap_base + physAddr;
378
379 DBG("Physical address map base: 0x%qx\n", *new_physmap_base);
380 for (i = kernPhysPML4Index; i < (kernPhysPML4Index + kernPhysPML4EntryCount); i++) {
381 DBG("Physical map idlepml4[%d]: 0x%llx\n", i, IdlePML4[i]);
382 }
383 }
384
385 void doublemap_init(uint8_t);
386
387 static void
Idle_PTs_init(void)388 Idle_PTs_init(void)
389 {
390 uint64_t rand64;
391 uint64_t new_physmap_base, new_physmap_max;
392
393 /* Allocate the "idle" kernel page tables: */
394 KPTphys = ALLOCPAGES(NKPT); /* level 1 */
395 IdlePTD = ALLOCPAGES(NPGPTD); /* level 2 */
396 IdlePDPT = ALLOCPAGES(1); /* level 3 */
397 IdlePML4 = ALLOCPAGES(1); /* level 4 */
398
399 // Fill the lowest level with everything up to physfree
400 fillkpt(KPTphys,
401 INTEL_PTE_WRITE, 0, 0, (int)(((uintptr_t)physfree) >> PAGE_SHIFT));
402
403 /* IdlePTD */
404 fillkpt(IdlePTD,
405 INTEL_PTE_WRITE, (uintptr_t)ID_MAP_VTOP(KPTphys), 0, NKPT);
406
407 // IdlePDPT entries
408 fillkpt(IdlePDPT,
409 INTEL_PTE_WRITE, (uintptr_t)ID_MAP_VTOP(IdlePTD), 0, NPGPTD);
410
411 // IdlePML4 single entry for kernel space.
412 fillkpt(IdlePML4 + KERNEL_PML4_INDEX,
413 INTEL_PTE_WRITE, (uintptr_t)ID_MAP_VTOP(IdlePDPT), 0, 1);
414
415 postcode(VSTART_PHYSMAP_INIT);
416
417 /*
418 * early_random() cannot be called more than one time before the cpu's
419 * gsbase is initialized, so use the full 64-bit value to extract the
420 * two 8-bit entropy values needed for address randomization.
421 */
422 rand64 = early_random();
423 physmap_init(rand64 & 0xFF, &new_physmap_base, &new_physmap_max);
424 doublemap_init((rand64 >> 8) & 0xFF);
425 idt64_remap();
426
427 postcode(VSTART_SET_CR3);
428
429 /*
430 * Switch to the page tables. We set physmap_base and physmap_max just
431 * before switching to the new page tables to avoid someone calling
432 * kprintf() or otherwise using physical memory in between.
433 * This is needed because kprintf() writes to physical memory using
434 * ml_phys_read_data and PHYSMAP_PTOV, which requires physmap_base to be
435 * set correctly.
436 */
437 physmap_base = new_physmap_base;
438 physmap_max = new_physmap_max;
439 set_cr3_raw((uintptr_t)ID_MAP_VTOP(IdlePML4));
440 }
441
442 /*
443 * Release any still unused, preallocated boot kernel page tables.
444 * start..end is the VA range currently unused.
445 */
446 void
Idle_PTs_release(vm_offset_t start,vm_offset_t end)447 Idle_PTs_release(vm_offset_t start, vm_offset_t end)
448 {
449 uint32_t i;
450 uint32_t index_start;
451 uint32_t index_limit;
452 ppnum_t pn_first;
453 ppnum_t pn;
454 uint32_t cnt;
455
456 /*
457 * Align start to the next large page boundary
458 */
459 start = ((start + I386_LPGMASK) & ~I386_LPGMASK);
460
461 /*
462 * convert start into an index in KPTphys[]
463 */
464 index_start = (uint32_t)((start - KERNEL_BASE) >> PAGE_SHIFT);
465
466 /*
467 * Find the ending index in KPTphys[]
468 */
469 index_limit = (uint32_t)((end - KERNEL_BASE) >> PAGE_SHIFT);
470
471 if (index_limit > NKPT * PTE_PER_PAGE) {
472 index_limit = NKPT * PTE_PER_PAGE;
473 }
474
475 /*
476 * Make sure all the 4K page tables are empty.
477 * If not, panic a development/debug kernel.
478 * On a production kernel, since this would stop us from booting,
479 * just abort the operation.
480 */
481 for (i = index_start; i < index_limit; ++i) {
482 assert(KPTphys[i] == 0);
483 if (KPTphys[i] != 0) {
484 return;
485 }
486 }
487
488 /*
489 * Now figure out the indices into the 2nd level page tables, IdlePTD[].
490 */
491 index_start >>= PTPGSHIFT;
492 index_limit >>= PTPGSHIFT;
493 if (index_limit > NPGPTD * PTE_PER_PAGE) {
494 index_limit = NPGPTD * PTE_PER_PAGE;
495 }
496
497 if (index_limit <= index_start) {
498 return;
499 }
500
501
502 /*
503 * Now check the pages referenced from Level 2 tables.
504 * They should be contiguous, assert fail if not on development/debug.
505 * In production, just fail the removal to allow the system to boot.
506 */
507 pn_first = 0;
508 cnt = 0;
509 for (i = index_start; i < index_limit; ++i) {
510 assert(IdlePTD[i] != 0);
511 if (IdlePTD[i] == 0) {
512 return;
513 }
514
515 pn = (ppnum_t)((PG_FRAME & IdlePTD[i]) >> PTSHIFT);
516 if (cnt == 0) {
517 pn_first = pn;
518 } else {
519 assert(pn == pn_first + cnt);
520 if (pn != pn_first + cnt) {
521 return;
522 }
523 }
524 ++cnt;
525 }
526
527 /*
528 * Good to go, clear the level 2 entries and invalidate the TLB
529 */
530 for (i = index_start; i < index_limit; ++i) {
531 IdlePTD[i] = 0;
532 }
533 set_cr3_raw(get_cr3_raw());
534
535 /*
536 * Remember these PFNs to be released later in pmap_lowmem_finalize()
537 */
538 released_PT_ppn = pn_first;
539 released_PT_cnt = cnt;
540 #if DEVELOPMENT || DEBUG
541 printf("Idle_PTs_release %d pages from PFN 0x%x\n", released_PT_cnt, released_PT_ppn);
542 #endif
543 }
544
545 extern void vstart_trap_handler;
546
547 #define BOOT_TRAP_VECTOR(t) \
548 [t] = { \
549 (uintptr_t) &vstart_trap_handler, \
550 KERNEL64_CS, \
551 0, \
552 ACC_P|ACC_PL_K|ACC_INTR_GATE, \
553 0 \
554 },
555
556 /* Recursive macro to iterate 0..31 */
557 #define L0(x, n) x(n)
558 #define L1(x, n) L0(x,n-1) L0(x,n)
559 #define L2(x, n) L1(x,n-2) L1(x,n)
560 #define L3(x, n) L2(x,n-4) L2(x,n)
561 #define L4(x, n) L3(x,n-8) L3(x,n)
562 #define L5(x, n) L4(x,n-16) L4(x,n)
563 #define FOR_0_TO_31(x) L5(x,31)
564
565 /*
566 * Bootstrap IDT. Active only during early startup.
567 * Only the trap vectors are defined since interrupts are masked.
568 * All traps point to a common handler.
569 */
570 struct fake_descriptor64 master_boot_idt64[IDTSZ]
571 __attribute__((section("__HIB,__desc")))
572 __attribute__((aligned(PAGE_SIZE))) = {
573 FOR_0_TO_31(BOOT_TRAP_VECTOR)
574 };
575
576 static void
vstart_idt_init(boolean_t master)577 vstart_idt_init(boolean_t master)
578 {
579 x86_64_desc_register_t vstart_idt = {
580 sizeof(master_boot_idt64),
581 master_boot_idt64
582 };
583
584 if (master) {
585 fix_desc64(master_boot_idt64, 32);
586 }
587 lidt((void *)&vstart_idt);
588 }
589
590 extern void *collection_base_pointers[KCNumKinds];
591
592 kern_return_t
i386_slide_individual_kext(kernel_mach_header_t * mh,uintptr_t slide)593 i386_slide_individual_kext(kernel_mach_header_t *mh, uintptr_t slide)
594 {
595 int ret = kernel_collection_slide(mh, (const void **) (void *)collection_base_pointers);
596 if (ret != 0) {
597 printf("Sliding pageable kc was stopped\n");
598 return KERN_FAILURE;
599 }
600
601 kernel_collection_adjust_fileset_entry_addrs(mh, slide);
602 return KERN_SUCCESS;
603 }
604
605 kern_return_t
i386_slide_kext_collection_mh_addrs(kernel_mach_header_t * mh,uintptr_t slide,bool adjust_mach_headers)606 i386_slide_kext_collection_mh_addrs(kernel_mach_header_t *mh, uintptr_t slide, bool adjust_mach_headers)
607 {
608 int ret = kernel_collection_slide(mh, (const void **) (void *)collection_base_pointers);
609 if (ret != KERN_SUCCESS) {
610 printf("Kernel Collection slide was stopped with value %d\n", ret);
611 return KERN_FAILURE;
612 }
613
614 kernel_collection_adjust_mh_addrs(mh, slide, adjust_mach_headers,
615 NULL, NULL, NULL, NULL, NULL, NULL, NULL);
616
617 return KERN_SUCCESS;
618 }
619
620 static void
i386_slide_and_rebase_image(uintptr_t kstart_addr)621 i386_slide_and_rebase_image(uintptr_t kstart_addr)
622 {
623 extern uintptr_t kc_highest_nonlinkedit_vmaddr;
624 kernel_mach_header_t *k_mh, *kc_mh = NULL;
625 kernel_segment_command_t *seg;
626 uintptr_t slide;
627
628 k_mh = &_mh_execute_header;
629 /*
630 * If we're not booting, an MH_FILESET, we don't need to slide
631 * anything because EFI has done that for us. When booting an
632 * MH_FILESET, EFI will slide the kernel proper, but not the kexts.
633 * Below, we infer the slide by comparing the slid address of the
634 * kernel's mach-o header and the unslid vmaddr of the first segment
635 * of the mach-o (which is assumed to always point to the mach-o
636 * header).
637 */
638 if (!kernel_mach_header_is_in_fileset(k_mh)) {
639 DBG("[MH] kcgen-style KC\n");
640 return;
641 }
642
643 /*
644 * The kernel is part of a MH_FILESET kernel collection: determine slide
645 * based on first segment's mach-o vmaddr.
646 */
647 seg = (kernel_segment_command_t *)((uintptr_t)k_mh + sizeof(*k_mh));
648 assert(seg->cmd == LC_SEGMENT_KERNEL);
649 slide = (uintptr_t)k_mh - seg->vmaddr;
650 DBG("[MH] Sliding new-style KC: %llu\n", (unsigned long long)slide);
651
652 /*
653 * The kernel collection mach-o header should be the start address
654 * passed to us by EFI.
655 */
656 kc_mh = (kernel_mach_header_t *)(kstart_addr);
657 assert(kc_mh->filetype == MH_FILESET);
658
659 PE_set_kc_header(KCKindPrimary, kc_mh, slide);
660
661 /*
662 * rebase/slide all the kexts in the collection
663 * (EFI should have already rebased the kernel)
664 */
665 kernel_collection_slide(kc_mh, (const void **) (void *)collection_base_pointers);
666
667
668 /*
669 * Now adjust the vmaddr fields of all mach-o headers
670 * and symbols in this MH_FILESET
671 */
672 kernel_collection_adjust_mh_addrs(kc_mh, slide, false,
673 NULL, NULL, NULL, NULL, NULL, NULL, &kc_highest_nonlinkedit_vmaddr);
674 }
675
676 /*
677 * vstart() is called in the natural mode (64bit for K64, 32 for K32)
678 * on a set of bootstrap pagetables which use large, 2MB pages to map
679 * all of physical memory in both. See idle_pt.c for details.
680 *
681 * In K64 this identity mapping is mirrored the top and bottom 512GB
682 * slots of PML4.
683 *
684 * The bootstrap processor called with argument boot_args_start pointing to
685 * the boot-args block. The kernel's (4K page) page tables are allocated and
686 * initialized before switching to these.
687 *
688 * Non-bootstrap processors are called with argument boot_args_start NULL.
689 * These processors switch immediately to the existing kernel page tables.
690 */
691 __attribute__((noreturn))
692 void
vstart(vm_offset_t boot_args_start)693 vstart(vm_offset_t boot_args_start)
694 {
695 boolean_t is_boot_cpu = !(boot_args_start == 0);
696 int cpu = 0;
697 uint32_t lphysfree;
698 #if DEBUG
699 uint64_t gsbase;
700 #endif
701
702
703 postcode(VSTART_ENTRY);
704
705 /*
706 * Set-up temporary trap handlers during page-table set-up.
707 */
708
709 if (is_boot_cpu) {
710 vstart_idt_init(TRUE);
711 postcode(VSTART_IDT_INIT);
712
713 /*
714 * Ensure that any %gs-relative access results in an immediate fault
715 * until gsbase is properly initialized below
716 */
717 wrmsr64(MSR_IA32_GS_BASE, EARLY_GSBASE_MAGIC);
718
719 /*
720 * Get startup parameters.
721 */
722 kernelBootArgs = (boot_args *)boot_args_start;
723 lphysfree = kernelBootArgs->kaddr + kernelBootArgs->ksize;
724 physfree = (void *)(uintptr_t)((lphysfree + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1));
725
726 pal_serial_init();
727
728 DBG("revision 0x%x\n", kernelBootArgs->Revision);
729 DBG("version 0x%x\n", kernelBootArgs->Version);
730 DBG("command line %s\n", kernelBootArgs->CommandLine);
731 DBG("memory map 0x%x\n", kernelBootArgs->MemoryMap);
732 DBG("memory map sz 0x%x\n", kernelBootArgs->MemoryMapSize);
733 DBG("kaddr 0x%x\n", kernelBootArgs->kaddr);
734 DBG("ksize 0x%x\n", kernelBootArgs->ksize);
735 DBG("physfree %p\n", physfree);
736 DBG("bootargs: %p, &ksize: %p &kaddr: %p\n",
737 kernelBootArgs,
738 &kernelBootArgs->ksize,
739 &kernelBootArgs->kaddr);
740 DBG("SMBIOS mem sz 0x%llx\n", kernelBootArgs->PhysicalMemorySize);
741 DBG("KC_hdrs_vaddr %p\n", (void *)kernelBootArgs->KC_hdrs_vaddr);
742
743 if (kernelBootArgs->Version >= 2 && kernelBootArgs->Revision >= 1 &&
744 kernelBootArgs->KC_hdrs_vaddr != 0) {
745 /*
746 * slide the header addresses in all mach-o segments and sections, and
747 * perform any new-style chained-fixup sliding for kexts, as necessary.
748 * Note that efiboot has already loaded the kernel and all LC_SEGMENT_64s
749 * that correspond to the kexts present in the primary KC, into slid addresses.
750 */
751 i386_slide_and_rebase_image((uintptr_t)ml_static_ptovirt(kernelBootArgs->KC_hdrs_vaddr));
752 }
753
754 /*
755 * Setup boot args given the physical start address.
756 * Note: PE_init_platform needs to be called before Idle_PTs_init
757 * because access to the DeviceTree is required to read the
758 * random seed before generating a random physical map slide.
759 */
760 kernelBootArgs = (boot_args *)
761 ml_static_ptovirt(boot_args_start);
762 DBG("i386_init(0x%lx) kernelBootArgs=%p\n",
763 (unsigned long)boot_args_start, kernelBootArgs);
764
765 #if KASAN
766 kasan_reserve_memory(kernelBootArgs);
767 #endif
768
769 PE_init_platform(FALSE, kernelBootArgs);
770 postcode(PE_INIT_PLATFORM_D);
771
772 Idle_PTs_init();
773 postcode(VSTART_IDLE_PTS_INIT);
774
775 #if KASAN
776 /* Init kasan and map whatever was stolen from physfree */
777 kasan_init();
778 kasan_notify_stolen((uintptr_t)ml_static_ptovirt((vm_offset_t)physfree));
779 #endif
780
781 #if MONOTONIC
782 mt_early_init();
783 #endif /* MONOTONIC */
784
785 first_avail = (vm_offset_t)ID_MAP_VTOP(physfree);
786
787 cpu_data_alloc(TRUE);
788
789 cpu_desc_init(cpu_datap(0));
790 postcode(VSTART_CPU_DESC_INIT);
791 cpu_desc_load(cpu_datap(0));
792
793 postcode(VSTART_CPU_MODE_INIT);
794 cpu_syscall_init(cpu_datap(0)); /* cpu_syscall_init() will be
795 * invoked on the APs
796 * via i386_init_slave()
797 */
798 } else {
799 /* Slave CPUs should use the basic IDT until i386_init_slave() */
800 vstart_idt_init(FALSE);
801
802 /* Switch to kernel's page tables (from the Boot PTs) */
803 set_cr3_raw((uintptr_t)ID_MAP_VTOP(IdlePML4));
804
805 /* Find our logical cpu number */
806 cpu = lapic_to_cpu[lapic_safe_apicid()];
807 #if DEBUG
808 gsbase = rdmsr64(MSR_IA32_GS_BASE);
809 #endif
810 cpu_desc_load(cpu_datap(cpu));
811 #if DEBUG
812 DBG("CPU: %d, GSBASE initial value: 0x%llx\n", cpu, (unsigned long long)gsbase);
813 #endif
814
815 /*
816 * Before we can discover our local APIC ID, we need to potentially
817 * initialize X2APIC, if it's enabled and firmware started us with
818 * the APIC in legacy mode.
819 */
820 lapic_init_slave();
821 }
822
823 early_boot = 0;
824 postcode(VSTART_EXIT);
825 x86_init_wrapper(is_boot_cpu ? (uintptr_t) i386_init
826 : (uintptr_t) i386_init_slave,
827 cpu_datap(cpu)->cpu_int_stack_top);
828 }
829
830 void
pstate_trace(void)831 pstate_trace(void)
832 {
833 }
834
835 /*
836 * Cpu initialization. Running virtual, but without MACH VM
837 * set up.
838 */
839 void
i386_init(void)840 i386_init(void)
841 {
842 unsigned int maxmem;
843 uint64_t maxmemtouse;
844 unsigned int cpus = 0;
845 boolean_t fidn;
846 boolean_t IA32e = TRUE;
847
848 postcode(I386_INIT_ENTRY);
849
850 pal_i386_init();
851 tsc_init();
852 rtclock_early_init(); /* mach_absolute_time() now functional */
853
854 kernel_debug_string_early("i386_init");
855 pstate_trace();
856
857 #if CONFIG_MCA
858 /* Initialize machine-check handling */
859 mca_cpu_init();
860 #endif
861
862 master_cpu = 0;
863
864 kernel_debug_string_early("kernel_startup_bootstrap");
865 kernel_startup_bootstrap();
866
867 /*
868 * Initialize the timer callout world
869 */
870 timer_call_init();
871
872 cpu_init();
873
874 postcode(CPU_INIT_D);
875
876 /* setup debugging output if one has been chosen */
877 kernel_startup_initialize_upto(STARTUP_SUB_KPRINTF);
878 kprintf("kprintf initialized\n");
879
880 if (!PE_parse_boot_argn("diag", &dgWork.dgFlags, sizeof(dgWork.dgFlags))) {
881 dgWork.dgFlags = 0;
882 }
883
884 if (PE_parse_boot_argn("insn_capcnt", &insn_copyin_count, sizeof(insn_copyin_count))) {
885 /*
886 * Enforce max and min values (allowing 0 to disable copying completely)
887 * for the instruction copyin count
888 */
889 if (insn_copyin_count > x86_INSTRUCTION_STATE_MAX_INSN_BYTES ||
890 (insn_copyin_count != 0 && insn_copyin_count < 64)) {
891 insn_copyin_count = DEFAULT_INSN_COPYIN_COUNT;
892 }
893 } else {
894 insn_copyin_count = DEFAULT_INSN_COPYIN_COUNT;
895 }
896
897 #if DEVELOPMENT || DEBUG
898 if (!PE_parse_boot_argn("panic_clmismatch", &panic_on_cacheline_mismatch,
899 sizeof(panic_on_cacheline_mismatch))) {
900 panic_on_cacheline_mismatch = 0;
901 }
902
903 if (!PE_parse_boot_argn("panic_on_trap_procname", &panic_on_trap_procname[0],
904 sizeof(panic_on_trap_procname))) {
905 panic_on_trap_procname[0] = 0;
906 }
907
908 if (!PE_parse_boot_argn("panic_on_trap_mask", &panic_on_trap_mask,
909 sizeof(panic_on_trap_mask))) {
910 if (panic_on_trap_procname[0] != 0) {
911 panic_on_trap_mask = DEFAULT_PANIC_ON_TRAP_MASK;
912 } else {
913 panic_on_trap_mask = 0;
914 }
915 }
916 #endif
917 /* But allow that to be overridden via boot-arg: */
918 if (!PE_parse_boot_argn("lbr_support", &last_branch_enabled_modes,
919 sizeof(last_branch_enabled_modes))) {
920 /* Disable LBR support by default due to its high context switch overhead */
921 last_branch_enabled_modes = LBR_ENABLED_NONE;
922 }
923
924 serialmode = 0;
925 if (PE_parse_boot_argn("serial", &serialmode, sizeof(serialmode))) {
926 /* We want a serial keyboard and/or console */
927 kprintf("Serial mode specified: %08X\n", serialmode);
928 int force_sync = serialmode & SERIALMODE_SYNCDRAIN;
929 disable_iolog_serial_output = (serialmode & SERIALMODE_NO_IOLOG) != 0;
930 enable_dklog_serial_output = (serialmode & SERIALMODE_DKLOG) != 0;
931 if (force_sync || PE_parse_boot_argn("drain_uart_sync", &force_sync, sizeof(force_sync))) {
932 if (force_sync) {
933 serialmode |= SERIALMODE_SYNCDRAIN;
934 kprintf(
935 "WARNING: Forcing uart driver to output synchronously."
936 "printf()s/IOLogs will impact kernel performance.\n"
937 "You are advised to avoid using 'drain_uart_sync' boot-arg.\n");
938 }
939 }
940 }
941 if (serialmode & SERIALMODE_OUTPUT) {
942 serial_console_enabled = true;
943 (void)switch_to_serial_console();
944 disableConsoleOutput = FALSE; /* Allow printfs to happen */
945 }
946
947 /* setup console output */
948 kernel_debug_string_early("PE_init_printf");
949 PE_init_printf(FALSE);
950
951 kprintf("version_variant = %s\n", version_variant);
952 kprintf("version = %s\n", version);
953
954 if (!PE_parse_boot_argn("maxmem", &maxmem, sizeof(maxmem))) {
955 maxmemtouse = 0;
956 } else {
957 maxmemtouse = ((uint64_t)maxmem) * MB;
958 }
959
960 max_cpus_from_firmware = acpi_count_enabled_logical_processors();
961
962 if (PE_parse_boot_argn("cpus", &cpus, sizeof(cpus))) {
963 if ((0 < cpus) && (cpus < max_ncpus)) {
964 max_ncpus = cpus;
965 }
966 }
967
968 /*
969 * debug support for > 4G systems
970 */
971 PE_parse_boot_argn("himemory_mode", &vm_himemory_mode, sizeof(vm_himemory_mode));
972 if (!vm_himemory_mode) {
973 kprintf("himemory_mode disabled\n");
974 }
975
976 if (!PE_parse_boot_argn("immediate_NMI", &fidn, sizeof(fidn))) {
977 force_immediate_debugger_NMI = FALSE;
978 } else {
979 force_immediate_debugger_NMI = fidn;
980 }
981
982 #if DEBUG
983 nanoseconds_to_absolutetime(URGENCY_NOTIFICATION_ASSERT_NS, &urgency_notification_assert_abstime_threshold);
984 #endif
985 PE_parse_boot_argn("urgency_notification_abstime",
986 &urgency_notification_assert_abstime_threshold,
987 sizeof(urgency_notification_assert_abstime_threshold));
988
989 if (!(cpuid_extfeatures() & CPUID_EXTFEATURE_XD)) {
990 nx_enabled = 0;
991 }
992
993 /*
994 * VM initialization, after this we're using page tables...
995 * Thn maximum number of cpus must be set beforehand.
996 */
997 kernel_debug_string_early("i386_vm_init");
998 i386_vm_init(maxmemtouse, IA32e, kernelBootArgs);
999
1000 /* create the console for verbose or pretty mode */
1001 /* Note: doing this prior to tsc_init() allows for graceful panic! */
1002 PE_init_platform(TRUE, kernelBootArgs);
1003 PE_create_console();
1004
1005 /* set %gs early so that power management can use locks */
1006 thread_t thread = thread_bootstrap();
1007 machine_set_current_thread(thread);
1008
1009 kernel_debug_string_early("power_management_init");
1010 power_management_init();
1011 xcpm_bootstrap();
1012
1013 #if MONOTONIC
1014 mt_cpu_up(cpu_datap(0));
1015 #endif /* MONOTONIC */
1016
1017 processor_bootstrap();
1018
1019 pstate_trace();
1020 kernel_debug_string_early("machine_startup");
1021 machine_startup();
1022 pstate_trace();
1023 }
1024
1025 static void __dead2
do_init_slave(boolean_t fast_restart)1026 do_init_slave(boolean_t fast_restart)
1027 {
1028 void *init_param = FULL_SLAVE_INIT;
1029
1030 postcode(I386_INIT_SLAVE);
1031
1032 if (!fast_restart) {
1033 /* Ensure that caching and write-through are enabled */
1034 set_cr0(get_cr0() & ~(CR0_NW | CR0_CD));
1035
1036 DBG("i386_init_slave() CPU%d: phys (%d) active.\n",
1037 get_cpu_number(), get_cpu_phys_number());
1038
1039 assert(!ml_get_interrupts_enabled());
1040
1041 cpu_syscall_init(current_cpu_datap());
1042 pmap_cpu_init();
1043
1044 #if CONFIG_MCA
1045 mca_cpu_init();
1046 #endif
1047
1048 LAPIC_INIT();
1049 /*
1050 * Note that the true argument here does not necessarily mean we're
1051 * here from a resume (this code path is also executed on boot).
1052 * The implementation of lapic_configure checks to see if the
1053 * state variable has been initialized, as it would be before
1054 * sleep. If it has not been, it's construed as an indicator of
1055 * first boot.
1056 */
1057 lapic_configure(true);
1058 LAPIC_DUMP();
1059 LAPIC_CPU_MAP_DUMP();
1060
1061 init_fpu();
1062
1063 #if CONFIG_MTRR
1064 mtrr_update_cpu();
1065 #endif
1066 /* update CPU microcode and apply CPU workarounds */
1067 ucode_update_wake_and_apply_cpu_was();
1068
1069 /* Enable LBRs on non-boot CPUs */
1070 i386_lbr_init(cpuid_info(), false);
1071 } else {
1072 init_param = FAST_SLAVE_INIT;
1073 }
1074
1075 #if CONFIG_VMX
1076 /* resume VT operation */
1077 vmx_resume(FALSE);
1078 #endif
1079
1080 #if CONFIG_MTRR
1081 if (!fast_restart) {
1082 pat_init();
1083 }
1084 #endif
1085
1086 cpu_thread_init(); /* not strictly necessary */
1087
1088 cpu_init(); /* Sets cpu_running which starter cpu waits for */
1089
1090
1091 #if MONOTONIC
1092 mt_cpu_up(current_cpu_datap());
1093 #endif /* MONOTONIC */
1094
1095 #if KPERF
1096 /*
1097 * We can only directly invoke kptimer_curcpu_up() when there is already an
1098 * active thread (that is, that this CPU has already been started at some point),
1099 * otherwise the ktrace calls within the kptimer operations will try to deref
1100 * the current thread and will instead cause a system reset.
1101 * If this is the first time the CPU is being started, we don't need to call
1102 * kptimer_curcpu_up().
1103 */
1104 if (current_processor()->active_thread != THREAD_NULL) {
1105 kptimer_curcpu_up();
1106 }
1107 #endif /* KPERF */
1108
1109 slave_main(init_param);
1110
1111 panic("do_init_slave() returned from slave_main()");
1112 }
1113
1114 /*
1115 * i386_init_slave() is called from pstart.
1116 * We're in the cpu's interrupt stack with interrupts disabled.
1117 * At this point we are in legacy mode. We need to switch on IA32e
1118 * if the mode is set to 64-bits.
1119 */
1120 void
i386_init_slave(void)1121 i386_init_slave(void)
1122 {
1123 do_init_slave(FALSE);
1124 }
1125
1126 /*
1127 * i386_init_slave_fast() is called from pmCPUHalt.
1128 * We're running on the idle thread and need to fix up
1129 * some accounting and get it so that the scheduler sees this
1130 * CPU again.
1131 */
1132 void
i386_init_slave_fast(void)1133 i386_init_slave_fast(void)
1134 {
1135 do_init_slave(TRUE);
1136 }
1137
1138
1139 /* TODO: Evaluate global PTEs for the double-mapped translations */
1140
1141 uint64_t dblmap_base, dblmap_max;
1142 kernel_segment_command_t *hdescseg;
1143
1144 pt_entry_t *dblmapL3;
1145 unsigned int dblallocs;
1146 uint64_t dblmap_dist;
1147 extern uint64_t idt64_hndl_table0[];
1148
1149
1150 void
doublemap_init(uint8_t randL3)1151 doublemap_init(uint8_t randL3)
1152 {
1153 dblmapL3 = ALLOCPAGES(1); // for 512 1GiB entries
1154 dblallocs++;
1155
1156 struct {
1157 pt_entry_t entries[PTE_PER_PAGE];
1158 } * dblmapL2 = ALLOCPAGES(1); // for 512 2MiB entries
1159 dblallocs++;
1160
1161 dblmapL3[randL3] = ((uintptr_t)ID_MAP_VTOP(&dblmapL2[0]))
1162 | INTEL_PTE_VALID
1163 | INTEL_PTE_WRITE;
1164
1165 hdescseg = getsegbynamefromheader(&_mh_execute_header, "__HIB");
1166
1167 vm_offset_t hdescb = hdescseg->vmaddr;
1168 unsigned long hdescsz = hdescseg->vmsize;
1169 unsigned long hdescszr = round_page_64(hdescsz);
1170 vm_offset_t hdescc = hdescb, hdesce = hdescb + hdescszr;
1171
1172 kernel_section_t *thdescsect = getsectbynamefromheader(&_mh_execute_header, "__HIB", "__text");
1173 vm_offset_t thdescb = thdescsect->addr;
1174 unsigned long thdescsz = thdescsect->size;
1175 unsigned long thdescszr = round_page_64(thdescsz);
1176 vm_offset_t thdesce = thdescb + thdescszr;
1177
1178 assert((hdescb & 0xFFF) == 0);
1179 /* Mirror HIB translations into the double-mapped pagetable subtree*/
1180 for (int i = 0; hdescc < hdesce; i++) {
1181 struct {
1182 pt_entry_t entries[PTE_PER_PAGE];
1183 } * dblmapL1 = ALLOCPAGES(1);
1184 dblallocs++;
1185 dblmapL2[0].entries[i] = ((uintptr_t)ID_MAP_VTOP(&dblmapL1[0])) | INTEL_PTE_VALID | INTEL_PTE_WRITE | INTEL_PTE_REF;
1186 int hdescn = (int) ((hdesce - hdescc) / PAGE_SIZE);
1187 for (int j = 0; j < MIN(PTE_PER_PAGE, hdescn); j++) {
1188 uint64_t template = INTEL_PTE_VALID;
1189 if ((hdescc >= thdescb) && (hdescc < thdesce)) {
1190 /* executable */
1191 } else {
1192 template |= INTEL_PTE_WRITE | INTEL_PTE_NX; /* Writeable, NX */
1193 }
1194 dblmapL1[0].entries[j] = ((uintptr_t)ID_MAP_VTOP(hdescc)) | template;
1195 hdescc += PAGE_SIZE;
1196 }
1197 }
1198
1199 IdlePML4[KERNEL_DBLMAP_PML4_INDEX] = ((uintptr_t)ID_MAP_VTOP(dblmapL3)) | INTEL_PTE_VALID | INTEL_PTE_WRITE | INTEL_PTE_REF;
1200
1201 dblmap_base = KVADDR(KERNEL_DBLMAP_PML4_INDEX, randL3, 0, 0);
1202 dblmap_max = dblmap_base + hdescszr;
1203 /* Calculate the double-map distance, which accounts for the current
1204 * KASLR slide
1205 */
1206
1207 dblmap_dist = dblmap_base - hdescb;
1208 idt64_hndl_table0[1] = DBLMAP(idt64_hndl_table0[1]); /* 64-bit exit trampoline */
1209 idt64_hndl_table0[3] = DBLMAP(idt64_hndl_table0[3]); /* 32-bit exit trampoline */
1210 idt64_hndl_table0[6] = (uint64_t)(uintptr_t)&kernel_stack_mask;
1211
1212 extern cpu_data_t cpshadows[], scdatas[];
1213 uintptr_t cd1 = (uintptr_t) &cpshadows[0];
1214 uintptr_t cd2 = (uintptr_t) &scdatas[0];
1215 /* Record the displacement from the kernel's per-CPU data pointer, eventually
1216 * programmed into GSBASE, to the "shadows" in the doublemapped
1217 * region. These are not aliases, but separate physical allocations
1218 * containing data required in the doublemapped trampolines.
1219 */
1220 idt64_hndl_table0[2] = dblmap_dist + cd1 - cd2;
1221
1222 DBG("Double map base: 0x%qx\n", dblmap_base);
1223 DBG("double map idlepml4[%d]: 0x%llx\n", KERNEL_DBLMAP_PML4_INDEX, IdlePML4[KERNEL_DBLMAP_PML4_INDEX]);
1224 assert(LDTSZ > LDTSZ_MIN);
1225 }
1226
1227 vm_offset_t dyn_dblmap(vm_offset_t, vm_offset_t);
1228
1229 #include <i386/pmap_internal.h>
1230
1231 /* Use of this routine is expected to be synchronized by callers
1232 * Creates non-executable aliases.
1233 */
1234 vm_offset_t
dyn_dblmap(vm_offset_t cva,vm_offset_t sz)1235 dyn_dblmap(vm_offset_t cva, vm_offset_t sz)
1236 {
1237 vm_offset_t ava = dblmap_max;
1238
1239 assert((sz & PAGE_MASK) == 0);
1240 assert(cva != 0);
1241
1242 pmap_alias(ava, cva, cva + sz, VM_PROT_READ | VM_PROT_WRITE, PMAP_EXPAND_OPTIONS_ALIASMAP);
1243 dblmap_max += sz;
1244 return ava - cva;
1245 }
1246 /* Adjust offsets interior to the bootstrap interrupt descriptor table to redirect
1247 * control to the double-mapped interrupt vectors. The IDTR proper will be
1248 * programmed via cpu_desc_load()
1249 */
1250 void
idt64_remap(void)1251 idt64_remap(void)
1252 {
1253 for (int i = 0; i < IDTSZ; i++) {
1254 master_idt64[i].offset64 = DBLMAP(master_idt64[i].offset64);
1255 }
1256 }
1257