1 /*
2 * Copyright (c) 2000-2020 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or [email protected]
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56
57 #include <mach_ldebug.h>
58
59 #include <sys/kdebug.h>
60
61 #include <mach/kern_return.h>
62 #include <mach/thread_status.h>
63 #include <mach/vm_param.h>
64
65 #include <kern/mach_param.h>
66 #include <kern/processor.h>
67 #include <kern/cpu_data.h>
68 #include <kern/cpu_number.h>
69 #include <kern/task.h>
70 #include <kern/thread.h>
71 #include <kern/sched_prim.h>
72 #include <kern/misc_protos.h>
73 #include <kern/assert.h>
74 #include <kern/spl.h>
75 #include <kern/machine.h>
76 #include <ipc/ipc_port.h>
77 #include <vm/vm_kern.h>
78 #include <vm/vm_map.h>
79 #include <vm/pmap.h>
80 #include <vm/vm_protos.h>
81
82 #include <i386/commpage/commpage.h>
83 #include <i386/cpu_data.h>
84 #include <i386/cpu_number.h>
85 #include <i386/cpuid.h>
86 #include <i386/eflags.h>
87 #include <i386/proc_reg.h>
88 #include <i386/tss.h>
89 #include <i386/user_ldt.h>
90 #include <i386/fpu.h>
91 #include <i386/mp_desc.h>
92 #include <i386/misc_protos.h>
93 #include <i386/thread.h>
94 #include <i386/seg.h>
95 #include <i386/machine_routines.h>
96 #include <i386/lbr.h>
97
98 #if HYPERVISOR
99 #include <kern/hv_support.h>
100 #endif
101
102 #define ASSERT_IS_16BYTE_MULTIPLE_SIZEOF(_type_) \
103 extern char assert_is_16byte_multiple_sizeof_ ## _type_ \
104 [(sizeof(_type_) % 16) == 0 ? 1 : -1]
105
106 /* Compile-time checks for vital save area sizing: */
107 ASSERT_IS_16BYTE_MULTIPLE_SIZEOF(x86_64_intr_stack_frame_t);
108 ASSERT_IS_16BYTE_MULTIPLE_SIZEOF(x86_saved_state_t);
109
110 #define DIRECTION_FLAG_DEBUG (DEBUG | DEVELOPMENT)
111
112 extern zone_t iss_zone; /* zone for saved_state area */
113 extern zone_t ids_zone; /* zone for debug_state area */
114 extern int tecs_mode_supported;
115 extern boolean_t cpuid_tsx_supported;
116
117 bool lbr_need_tsx_workaround = false;
118
119 int force_thread_policy_tecs;
120
121 struct lbr_group {
122 uint32_t msr_from;
123 uint32_t msr_to;
124 uint32_t msr_info;
125 };
126
127 struct cpu_lbrs {
128 uint32_t lbr_count;
129 struct lbr_group msr_lbrs[X86_MAX_LBRS];
130 };
131
132 const struct cpu_lbrs *cpu_lbr_setp = NULL;
133 int cpu_lbr_type;
134
135 const struct cpu_lbrs nhm_cpu_lbrs = {
136 16 /* LBR count */,
137 {
138 { 0x680 /* FROM_0 */, 0x6c0 /* TO_0 */, 0 /* INFO_0 */ },
139 { 0x681 /* FROM_1 */, 0x6c1 /* TO_1 */, 0 /* INFO_1 */ },
140 { 0x682 /* FROM_2 */, 0x6c2 /* TO_2 */, 0 /* INFO_2 */ },
141 { 0x683 /* FROM_3 */, 0x6c3 /* TO_3 */, 0 /* INFO_3 */ },
142 { 0x684 /* FROM_4 */, 0x6c4 /* TO_4 */, 0 /* INFO_4 */ },
143 { 0x685 /* FROM_5 */, 0x6c5 /* TO_5 */, 0 /* INFO_5 */ },
144 { 0x686 /* FROM_6 */, 0x6c6 /* TO_6 */, 0 /* INFO_6 */ },
145 { 0x687 /* FROM_7 */, 0x6c7 /* TO_7 */, 0 /* INFO_7 */ },
146 { 0x688 /* FROM_8 */, 0x6c8 /* TO_8 */, 0 /* INFO_8 */ },
147 { 0x689 /* FROM_9 */, 0x6c9 /* TO_9 */, 0 /* INFO_9 */ },
148 { 0x68A /* FROM_10 */, 0x6ca /* TO_10 */, 0 /* INFO_10 */ },
149 { 0x68B /* FROM_11 */, 0x6cb /* TO_11 */, 0 /* INFO_11 */ },
150 { 0x68C /* FROM_12 */, 0x6cc /* TO_12 */, 0 /* INFO_12 */ },
151 { 0x68D /* FROM_13 */, 0x6cd /* TO_13 */, 0 /* INFO_13 */ },
152 { 0x68E /* FROM_14 */, 0x6ce /* TO_14 */, 0 /* INFO_14 */ },
153 { 0x68F /* FROM_15 */, 0x6cf /* TO_15 */, 0 /* INFO_15 */ }
154 }
155 },
156 skl_cpu_lbrs = {
157 32 /* LBR count */,
158 {
159 { 0x680 /* FROM_0 */, 0x6c0 /* TO_0 */, 0xdc0 /* INFO_0 */ },
160 { 0x681 /* FROM_1 */, 0x6c1 /* TO_1 */, 0xdc1 /* INFO_1 */ },
161 { 0x682 /* FROM_2 */, 0x6c2 /* TO_2 */, 0xdc2 /* INFO_2 */ },
162 { 0x683 /* FROM_3 */, 0x6c3 /* TO_3 */, 0xdc3 /* INFO_3 */ },
163 { 0x684 /* FROM_4 */, 0x6c4 /* TO_4 */, 0xdc4 /* INFO_4 */ },
164 { 0x685 /* FROM_5 */, 0x6c5 /* TO_5 */, 0xdc5 /* INFO_5 */ },
165 { 0x686 /* FROM_6 */, 0x6c6 /* TO_6 */, 0xdc6 /* INFO_6 */ },
166 { 0x687 /* FROM_7 */, 0x6c7 /* TO_7 */, 0xdc7 /* INFO_7 */ },
167 { 0x688 /* FROM_8 */, 0x6c8 /* TO_8 */, 0xdc8 /* INFO_8 */ },
168 { 0x689 /* FROM_9 */, 0x6c9 /* TO_9 */, 0xdc9 /* INFO_9 */ },
169 { 0x68A /* FROM_10 */, 0x6ca /* TO_10 */, 0xdca /* INFO_10 */ },
170 { 0x68B /* FROM_11 */, 0x6cb /* TO_11 */, 0xdcb /* INFO_11 */ },
171 { 0x68C /* FROM_12 */, 0x6cc /* TO_12 */, 0xdcc /* INFO_12 */ },
172 { 0x68D /* FROM_13 */, 0x6cd /* TO_13 */, 0xdcd /* INFO_13 */ },
173 { 0x68E /* FROM_14 */, 0x6ce /* TO_14 */, 0xdce /* INFO_14 */ },
174 { 0x68F /* FROM_15 */, 0x6cf /* TO_15 */, 0xdcf /* INFO_15 */ },
175 { 0x690 /* FROM_16 */, 0x6d0 /* TO_16 */, 0xdd0 /* INFO_16 */ },
176 { 0x691 /* FROM_17 */, 0x6d1 /* TO_17 */, 0xdd1 /* INFO_17 */ },
177 { 0x692 /* FROM_18 */, 0x6d2 /* TO_18 */, 0xdd2 /* INFO_18 */ },
178 { 0x693 /* FROM_19 */, 0x6d3 /* TO_19 */, 0xdd3 /* INFO_19 */ },
179 { 0x694 /* FROM_20 */, 0x6d4 /* TO_20 */, 0xdd4 /* INFO_20 */ },
180 { 0x695 /* FROM_21 */, 0x6d5 /* TO_21 */, 0xdd5 /* INFO_21 */ },
181 { 0x696 /* FROM_22 */, 0x6d6 /* TO_22 */, 0xdd6 /* INFO_22 */ },
182 { 0x697 /* FROM_23 */, 0x6d7 /* TO_23 */, 0xdd7 /* INFO_23 */ },
183 { 0x698 /* FROM_24 */, 0x6d8 /* TO_24 */, 0xdd8 /* INFO_24 */ },
184 { 0x699 /* FROM_25 */, 0x6d9 /* TO_25 */, 0xdd9 /* INFO_25 */ },
185 { 0x69a /* FROM_26 */, 0x6da /* TO_26 */, 0xdda /* INFO_26 */ },
186 { 0x69b /* FROM_27 */, 0x6db /* TO_27 */, 0xddb /* INFO_27 */ },
187 { 0x69c /* FROM_28 */, 0x6dc /* TO_28 */, 0xddc /* INFO_28 */ },
188 { 0x69d /* FROM_29 */, 0x6dd /* TO_29 */, 0xddd /* INFO_29 */ },
189 { 0x69e /* FROM_30 */, 0x6de /* TO_30 */, 0xdde /* INFO_30 */ },
190 { 0x69f /* FROM_31 */, 0x6df /* TO_31 */, 0xddf /* INFO_31 */ }
191 }
192 };
193
194 void
i386_lbr_disable(void)195 i386_lbr_disable(void)
196 {
197 /* Enable LBRs */
198 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) & ~DEBUGCTL_LBR_ENA);
199 }
200
201 /*
202 * Disable ASAN for i386_lbr_enable and i386_lbr_init, otherwise we get a KASAN panic
203 * because the shadow map is not been initialized when these functions are called in
204 * early boot.
205 */
206 void __attribute__((no_sanitize("address")))
i386_lbr_enable(void)207 i386_lbr_enable(void)
208 {
209 /* last_branch_kmode_only_enabled controls LBR data collection for core files and paniclogs */
210 switch (last_branch_enabled_modes) {
211 case LBR_ENABLED_USERMODE:
212 case LBR_ENABLED_KERNELMODE:
213 /* Enable LBRs */
214 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) | DEBUGCTL_LBR_ENA);
215 break;
216 case LBR_ENABLED_NONE:
217 case LBR_ENABLED_ALLMODES:
218 default:
219 break;
220 }
221 }
222
223 void __attribute__((no_sanitize("address")))
i386_lbr_init(i386_cpu_info_t * info_p,bool is_master)224 i386_lbr_init(i386_cpu_info_t *info_p, bool is_master)
225 {
226 if (last_branch_enabled_modes == LBR_ENABLED_NONE) {
227 i386_lbr_disable();
228 return;
229 }
230 if (last_branch_enabled_modes == LBR_ENABLED_ALLMODES) {
231 panic("Collecting LBR data from both user and kernel mode is not supported.");
232 }
233
234 if (is_master) {
235 /* All NHM+ CPUs support PERF_CAPABILITIES, so no need to check cpuid for its presence */
236 cpu_lbr_type = PERFCAP_LBR_TYPE(rdmsr64(MSR_IA32_PERF_CAPABILITIES));
237
238 /* Sanity-check the LBR type -- some VMMs do not properly support it */
239 if (cpu_lbr_type < PERFCAP_LBR_TYPE_MISPRED || cpu_lbr_type > PERFCAP_LBR_TYPE_EIP_WITH_LBRINFO) {
240 kprintf("CPU-reported LBR type is invalid or is not supported (%d)."
241 " Disabling LBR support.\n", cpu_lbr_type);
242 last_branch_enabled_modes = LBR_ENABLED_NONE;
243 i386_lbr_disable();
244 return;
245 }
246
247 switch (info_p->cpuid_cpufamily) {
248 case CPUFAMILY_INTEL_NEHALEM:
249 case CPUFAMILY_INTEL_WESTMERE:
250 /* NHM family shares an LBR_SELECT MSR for both logical CPUs per core */
251 cpu_lbr_setp = &nhm_cpu_lbrs;
252 break;
253
254 case CPUFAMILY_INTEL_SANDYBRIDGE:
255 case CPUFAMILY_INTEL_IVYBRIDGE:
256 /* SNB+ has dedicated LBR_SELECT MSRs for each logical CPU per core */
257 cpu_lbr_setp = &nhm_cpu_lbrs;
258 break;
259
260 case CPUFAMILY_INTEL_HASWELL:
261 case CPUFAMILY_INTEL_BROADWELL:
262 lbr_need_tsx_workaround = cpuid_tsx_supported ? false : true;
263 cpu_lbr_setp = &nhm_cpu_lbrs;
264 break;
265
266 case CPUFAMILY_INTEL_SKYLAKE:
267 case CPUFAMILY_INTEL_KABYLAKE:
268 case CPUFAMILY_INTEL_ICELAKE:
269 cpu_lbr_setp = &skl_cpu_lbrs;
270 break;
271
272 default:
273 panic("Unknown CPU family");
274 }
275 if (last_branch_enabled_modes == LBR_ENABLED_KERNELMODE) {
276 /* This depends on cpu_lbr_setp being setup first */
277 lbr_for_kmode_init(cpu_lbr_setp->lbr_count);
278 }
279 }
280
281 /* Configure LBR_SELECT for CPL > 0 records only or CPL = 0 for use in panic logs and core files */
282 switch (last_branch_enabled_modes) {
283 case LBR_ENABLED_USERMODE:
284 wrmsr64(MSR_IA32_LBR_SELECT, LBR_SELECT_CPL_EQ_0);
285 break;
286 case LBR_ENABLED_KERNELMODE:
287 #if DEBUG || DEVELOPMENT
288 wrmsr64(MSR_IA32_LBR_SELECT, 0);
289 #else
290 wrmsr64(MSR_IA32_LBR_SELECT, LBR_SELECT_CPL_NEQ_0);
291 #endif
292 break;
293 case LBR_ENABLED_NONE:
294 case LBR_ENABLED_ALLMODES:
295 default:
296 break;
297 }
298
299 /* Enable LBRs */
300 wrmsr64(MSR_IA32_DEBUGCTLMSR, rdmsr64(MSR_IA32_DEBUGCTLMSR) | DEBUGCTL_LBR_ENA);
301 }
302
303 static uint64_t
lbr_mode_based_filter(uint64_t record,__unused boolean_t from_userspace)304 lbr_mode_based_filter(uint64_t record, __unused boolean_t from_userspace)
305 {
306 uint64_t filtered_record;
307 #define LBR_SENTINEL_KERNEL_MODE (0x66726d6b65726e6cULL /* "frmkernl" */ )
308 #define LBR_SENTINEL_USER_MODE (0x757365726C616E64ULL /* "userland" */ )
309 switch (last_branch_enabled_modes) {
310 case LBR_ENABLED_USERMODE:
311 filtered_record = (record > VM_MAX_USER_PAGE_ADDRESS) ? LBR_SENTINEL_KERNEL_MODE : record;
312 break;
313 case LBR_ENABLED_KERNELMODE:
314 /* For internal builds don't filter out userspace addresses from panic logs and core files. */
315 #if DEBUG || DEVELOPMENT
316 filtered_record = record;
317 #else
318 /* If coming from user space use the correct filter in release builds
319 * When LBRs are enabled for kernel mode and user space requests LBR data: remove kernel addresses
320 * " " and kernel mode requests LBR data: remove usermode addresses
321 */
322 if (from_userspace) {
323 filtered_record = (record > VM_MAX_USER_PAGE_ADDRESS) ? LBR_SENTINEL_KERNEL_MODE : record;
324 } else {
325 filtered_record = (VM_KERNEL_ADDRESS(record)) ? record : LBR_SENTINEL_USER_MODE;
326 }
327 #endif
328 break;
329 case LBR_ENABLED_ALLMODES:
330 case LBR_ENABLED_NONE:
331 default:
332 /* Set LBR to 0 for unsupported use cases */
333 filtered_record = 0x0;
334 break;
335 }
336 return filtered_record;
337 }
338
339 static int
i386_lbr_native_state_to_mach_thread_state(pcb_t pcb,last_branch_state_t * machlbrp,boolean_t from_userspace)340 i386_lbr_native_state_to_mach_thread_state(pcb_t pcb, last_branch_state_t *machlbrp, boolean_t from_userspace)
341 {
342 int last_entry;
343 int i, j, lbr_tos;
344 uint64_t from_rip, to_rip;
345
346 machlbrp->lbr_count = cpu_lbr_setp->lbr_count;
347 lbr_tos = pcb->lbrs.lbr_tos & (X86_MAX_LBRS - 1);
348 last_entry = (lbr_tos == (cpu_lbr_setp->lbr_count - 1)) ? 0 : (lbr_tos + 1);
349
350 switch (cpu_lbr_type) {
351 case PERFCAP_LBR_TYPE_MISPRED: /* NHM */
352
353 machlbrp->lbr_supported_tsx = 0;
354 machlbrp->lbr_supported_cycle_count = 0;
355 for (j = 0, i = lbr_tos;; (i = (i == 0) ? (cpu_lbr_setp->lbr_count - 1) : (i - 1)), j++) {
356 to_rip = pcb->lbrs.lbrs[i].to_rip;
357 machlbrp->lbrs[j].to_ip = lbr_mode_based_filter(to_rip, from_userspace);
358 from_rip = LBR_TYPE_MISPRED_FROMRIP(pcb->lbrs.lbrs[i].from_rip);
359 machlbrp->lbrs[j].from_ip = lbr_mode_based_filter(from_rip, from_userspace);
360 machlbrp->lbrs[j].mispredict = LBR_TYPE_MISPRED_MISPREDICT(pcb->lbrs.lbrs[i].from_rip);
361 machlbrp->lbrs[j].tsx_abort = machlbrp->lbrs[j].in_tsx = 0; /* Not Supported */
362 if (i == last_entry) {
363 break;
364 }
365 }
366 break;
367
368 case PERFCAP_LBR_TYPE_TSXINFO: /* HSW/BDW */
369
370 machlbrp->lbr_supported_tsx = cpuid_tsx_supported ? 1 : 0;
371 machlbrp->lbr_supported_cycle_count = 0;
372 for (j = 0, i = lbr_tos;; (i = (i == 0) ? (cpu_lbr_setp->lbr_count - 1) : (i - 1)), j++) {
373 to_rip = pcb->lbrs.lbrs[i].to_rip;
374 machlbrp->lbrs[j].to_ip = lbr_mode_based_filter(to_rip, from_userspace);
375
376 from_rip = LBR_TYPE_TSXINFO_FROMRIP(pcb->lbrs.lbrs[i].from_rip);
377 machlbrp->lbrs[j].from_ip = lbr_mode_based_filter(from_rip, from_userspace);
378 machlbrp->lbrs[j].mispredict = LBR_TYPE_TSXINFO_MISPREDICT(pcb->lbrs.lbrs[i].from_rip);
379 if (cpuid_tsx_supported) {
380 machlbrp->lbrs[j].tsx_abort = LBR_TYPE_TSXINFO_TSX_ABORT(pcb->lbrs.lbrs[i].from_rip);
381 machlbrp->lbrs[j].in_tsx = LBR_TYPE_TSXINFO_IN_TSX(pcb->lbrs.lbrs[i].from_rip);
382 } else {
383 machlbrp->lbrs[j].tsx_abort = 0;
384 machlbrp->lbrs[j].in_tsx = 0;
385 }
386 if (i == last_entry) {
387 break;
388 }
389 }
390 break;
391
392 case PERFCAP_LBR_TYPE_EIP_WITH_LBRINFO: /* SKL+ */
393
394 machlbrp->lbr_supported_tsx = cpuid_tsx_supported ? 1 : 0;
395 machlbrp->lbr_supported_cycle_count = 1;
396 for (j = 0, i = lbr_tos;; (i = (i == 0) ? (cpu_lbr_setp->lbr_count - 1) : (i - 1)), j++) {
397 from_rip = pcb->lbrs.lbrs[i].from_rip;
398 machlbrp->lbrs[j].from_ip = lbr_mode_based_filter(from_rip, from_userspace);
399 to_rip = pcb->lbrs.lbrs[i].to_rip;
400 machlbrp->lbrs[j].to_ip = lbr_mode_based_filter(to_rip, from_userspace);
401 machlbrp->lbrs[j].mispredict = LBR_TYPE_EIP_WITH_LBRINFO_MISPREDICT(pcb->lbrs.lbrs[i].info);
402 machlbrp->lbrs[j].tsx_abort = LBR_TYPE_EIP_WITH_LBRINFO_TSX_ABORT(pcb->lbrs.lbrs[i].info);
403 machlbrp->lbrs[j].in_tsx = LBR_TYPE_EIP_WITH_LBRINFO_IN_TSX(pcb->lbrs.lbrs[i].info);
404 machlbrp->lbrs[j].cycle_count = LBR_TYPE_EIP_WITH_LBRINFO_CYC_COUNT(pcb->lbrs.lbrs[i].info);
405 if (i == last_entry) {
406 break;
407 }
408 }
409 break;
410
411 default:
412 #if DEBUG || DEVELOPMENT
413 /* This should be impossible, based on the filtering we do in i386_lbr_init() */
414 panic("Unknown LBR format: %d!", cpu_lbr_type);
415 /*NOTREACHED*/
416 #else
417 return -1;
418 #endif
419 }
420
421 return 0;
422 }
423
424 int
i386_filtered_lbr_state_to_mach_thread_state(thread_t thr_act,last_branch_state_t * machlbrp,boolean_t from_userspace)425 i386_filtered_lbr_state_to_mach_thread_state(thread_t thr_act, last_branch_state_t *machlbrp, boolean_t from_userspace)
426 {
427 boolean_t istate;
428
429 istate = ml_set_interrupts_enabled(FALSE);
430 /* If the current thread is asking for its own LBR data, synch the LBRs first */
431 if (thr_act == current_thread()) {
432 i386_lbr_synch(thr_act);
433 }
434 ml_set_interrupts_enabled(istate);
435
436 return i386_lbr_native_state_to_mach_thread_state(THREAD_TO_PCB(thr_act), machlbrp, from_userspace);
437 }
438
439 void
i386_lbr_synch(thread_t thr)440 i386_lbr_synch(thread_t thr)
441 {
442 pcb_t old_pcb = THREAD_TO_PCB(thr);
443 int i;
444
445 /* First, save current LBRs to the old thread's PCB */
446 if (cpu_lbr_setp->msr_lbrs[0].msr_info != 0) {
447 for (i = 0; i < cpu_lbr_setp->lbr_count; i++) {
448 old_pcb->lbrs.lbrs[i].from_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from);
449 old_pcb->lbrs.lbrs[i].to_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to);
450 old_pcb->lbrs.lbrs[i].info = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_info);
451 }
452 } else {
453 for (i = 0; i < cpu_lbr_setp->lbr_count; i++) {
454 old_pcb->lbrs.lbrs[i].from_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from);
455 old_pcb->lbrs.lbrs[i].to_rip = rdmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to);
456 }
457 }
458
459 /* Finally, save the TOS */
460 old_pcb->lbrs.lbr_tos = rdmsr64(MSR_IA32_LASTBRANCH_TOS);
461 }
462
463 void
i386_switch_lbrs(thread_t old,thread_t new)464 i386_switch_lbrs(thread_t old, thread_t new)
465 {
466 pcb_t new_pcb;
467 int i;
468 bool save_old = (old != NULL && get_threadtask(old) != kernel_task);
469 bool restore_new = (get_threadtask(new) != kernel_task);
470
471 if (!save_old && !restore_new) {
472 return;
473 }
474
475 assert(cpu_lbr_setp != NULL);
476
477 new_pcb = THREAD_TO_PCB(new);
478
479 i386_lbr_disable();
480
481 if (save_old) {
482 i386_lbr_synch(old);
483 }
484
485 if (restore_new) {
486 /* Now restore the new threads's LBRs */
487 if (cpu_lbr_setp->msr_lbrs[0].msr_info != 0) {
488 for (i = 0; i < cpu_lbr_setp->lbr_count; i++) {
489 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from, new_pcb->lbrs.lbrs[i].from_rip);
490 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to, new_pcb->lbrs.lbrs[i].to_rip);
491 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_info, new_pcb->lbrs.lbrs[i].info);
492 }
493 } else {
494 if (lbr_need_tsx_workaround) {
495 for (i = 0; i < cpu_lbr_setp->lbr_count; i++) {
496 /*
497 * If TSX has been disabled, the hardware expects those two bits to be sign
498 * extensions of bit 47 (even though it didn't return them that way via the rdmsr!)
499 */
500 #define BIT_47 (1ULL << 47)
501 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from,
502 new_pcb->lbrs.lbrs[i].from_rip |
503 ((new_pcb->lbrs.lbrs[i].from_rip & BIT_47) ? 0x6000000000000000ULL : 0));
504 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to,
505 new_pcb->lbrs.lbrs[i].to_rip |
506 ((new_pcb->lbrs.lbrs[i].to_rip & BIT_47) ? 0x6000000000000000ULL : 0));
507 }
508 } else {
509 for (i = 0; i < cpu_lbr_setp->lbr_count; i++) {
510 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_from, new_pcb->lbrs.lbrs[i].from_rip);
511 wrmsr64(cpu_lbr_setp->msr_lbrs[i].msr_to, new_pcb->lbrs.lbrs[i].to_rip);
512 }
513 }
514 }
515
516 /* Lastly, restore the new threads's TOS */
517 wrmsr64(MSR_IA32_LASTBRANCH_TOS, new_pcb->lbrs.lbr_tos);
518 }
519
520 i386_lbr_enable();
521 }
522
523 void
act_machine_switch_pcb(thread_t old,thread_t new)524 act_machine_switch_pcb(thread_t old, thread_t new)
525 {
526 pcb_t pcb = THREAD_TO_PCB(new);
527 cpu_data_t *cdp = current_cpu_datap();
528 struct real_descriptor *ldtp;
529 mach_vm_offset_t pcb_stack_top;
530
531 assert(new->kernel_stack != 0);
532 assert(ml_get_interrupts_enabled() == FALSE);
533 #ifdef DIRECTION_FLAG_DEBUG
534 if (x86_get_flags() & EFL_DF) {
535 panic("Direction flag detected: 0x%lx", x86_get_flags());
536 }
537 #endif
538
539 /*
540 * Clear segment state
541 * unconditionally for DS/ES/FS but more carefully for GS whose
542 * cached state we track.
543 */
544 set_ds(NULL_SEG);
545 set_es(NULL_SEG);
546 set_fs(NULL_SEG);
547
548 if (get_gs() != NULL_SEG) {
549 swapgs(); /* switch to user's GS context */
550 set_gs(NULL_SEG);
551 swapgs(); /* and back to kernel */
552
553 /* record the active machine state lost */
554 cdp->cpu_uber.cu_user_gs_base = 0;
555 }
556
557 vm_offset_t isf;
558
559 /*
560 * Set pointer to PCB's interrupt stack frame in cpu data.
561 * Used by syscall and double-fault trap handlers.
562 */
563 isf = (vm_offset_t) &pcb->iss->ss_64.isf;
564 cdp->cpu_uber.cu_isf = isf;
565 pcb_stack_top = (vm_offset_t) (pcb->iss + 1);
566 /* require 16-byte alignment */
567 assert((pcb_stack_top & 0xF) == 0);
568
569 current_ktss64()->rsp0 = cdp->cpu_desc_index.cdi_sstku;
570 /*
571 * Top of temporary sysenter stack points to pcb stack.
572 * Although this is not normally used by 64-bit users,
573 * it needs to be set in case a sysenter is attempted.
574 */
575 *current_sstk64() = pcb_stack_top;
576
577 cdp->cd_estack = cpu_shadowp(cdp->cpu_number)->cd_estack = cdp->cpu_desc_index.cdi_sstku;
578
579 if (is_saved_state64(pcb->iss)) {
580 cdp->cpu_task_map = new->map->pmap->pm_task_map;
581
582 /*
583 * Enable the 64-bit user code segment, USER64_CS.
584 * Disable the 32-bit user code segment, USER_CS.
585 */
586 gdt_desc_p(USER64_CS)->access |= ACC_PL_U;
587 gdt_desc_p(USER_CS)->access &= ~ACC_PL_U;
588
589 /*
590 * Switch user's GS base if necessary
591 * by setting the Kernel's GS base MSR
592 * - this will become the user's on the swapgs when
593 * returning to user-space. Avoid this for
594 * kernel threads (no user TLS support required)
595 * and verify the memory shadow of the segment base
596 * in the event it was altered in user space.
597 */
598 if ((pcb->cthread_self != 0) || (get_threadtask(new) != kernel_task)) {
599 if ((cdp->cpu_uber.cu_user_gs_base != pcb->cthread_self) ||
600 (pcb->cthread_self != rdmsr64(MSR_IA32_KERNEL_GS_BASE))) {
601 cdp->cpu_uber.cu_user_gs_base = pcb->cthread_self;
602 wrmsr64(MSR_IA32_KERNEL_GS_BASE, pcb->cthread_self);
603 }
604 }
605 } else {
606 cdp->cpu_task_map = TASK_MAP_32BIT;
607
608 /*
609 * Disable USER64_CS
610 * Enable USER_CS
611 */
612
613 /* It's possible that writing to the GDT areas
614 * is expensive, if the processor intercepts those
615 * writes to invalidate its internal segment caches
616 * TODO: perhaps only do this if switching bitness
617 */
618 gdt_desc_p(USER64_CS)->access &= ~ACC_PL_U;
619 gdt_desc_p(USER_CS)->access |= ACC_PL_U;
620
621 /*
622 * Set the thread`s cthread (a.k.a pthread)
623 * For 32-bit user this involves setting the USER_CTHREAD
624 * descriptor in the LDT to point to the cthread data.
625 * The involves copying in the pre-initialized descriptor.
626 */
627 ldtp = current_ldt();
628 ldtp[sel_idx(USER_CTHREAD)] = pcb->cthread_desc;
629 if (pcb->uldt_selector != 0) {
630 ldtp[sel_idx(pcb->uldt_selector)] = pcb->uldt_desc;
631 }
632 cdp->cpu_uber.cu_user_gs_base = pcb->cthread_self;
633 }
634
635 cdp->cpu_curthread_do_segchk = new->machine.mthr_do_segchk;
636
637 if (last_branch_enabled_modes == LBR_ENABLED_USERMODE) {
638 i386_switch_lbrs(old, new);
639 }
640
641 /*
642 * Set the thread's LDT or LDT entry.
643 */
644 task_t task = get_threadtask_early(new);
645 if (__probable(task == TASK_NULL || task->i386_ldt == 0)) {
646 /*
647 * Use system LDT.
648 */
649 ml_cpu_set_ldt(KERNEL_LDT);
650 cdp->cpu_curtask_has_ldt = 0;
651 } else {
652 /*
653 * Task has its own LDT.
654 */
655 user_ldt_set(new);
656 cdp->cpu_curtask_has_ldt = 1;
657 }
658 }
659
660 kern_return_t
thread_set_wq_state32(thread_t thread,thread_state_t tstate)661 thread_set_wq_state32(thread_t thread, thread_state_t tstate)
662 {
663 x86_thread_state32_t *state;
664 x86_saved_state32_t *saved_state;
665 thread_t curth = current_thread();
666 spl_t s = 0;
667
668 pal_register_cache_state(thread, DIRTY);
669
670 saved_state = USER_REGS32(thread);
671
672 state = (x86_thread_state32_t *)tstate;
673
674 if (curth != thread) {
675 s = splsched();
676 thread_lock(thread);
677 }
678
679 saved_state->ebp = 0;
680 saved_state->eip = state->eip;
681 saved_state->eax = state->eax;
682 saved_state->ebx = state->ebx;
683 saved_state->ecx = state->ecx;
684 saved_state->edx = state->edx;
685 saved_state->edi = state->edi;
686 saved_state->esi = state->esi;
687 saved_state->uesp = state->esp;
688 saved_state->efl = EFL_USER_SET;
689
690 saved_state->cs = USER_CS;
691 saved_state->ss = USER_DS;
692 saved_state->ds = USER_DS;
693 saved_state->es = USER_DS;
694
695 if (curth != thread) {
696 thread_unlock(thread);
697 splx(s);
698 }
699
700 return KERN_SUCCESS;
701 }
702
703
704 kern_return_t
thread_set_wq_state64(thread_t thread,thread_state_t tstate)705 thread_set_wq_state64(thread_t thread, thread_state_t tstate)
706 {
707 x86_thread_state64_t *state;
708 x86_saved_state64_t *saved_state;
709 thread_t curth = current_thread();
710 spl_t s = 0;
711
712 saved_state = USER_REGS64(thread);
713 state = (x86_thread_state64_t *)tstate;
714
715 /* Disallow setting non-canonical PC or stack */
716 if (!IS_USERADDR64_CANONICAL(state->rsp) ||
717 !IS_USERADDR64_CANONICAL(state->rip)) {
718 return KERN_FAILURE;
719 }
720
721 pal_register_cache_state(thread, DIRTY);
722
723 if (curth != thread) {
724 s = splsched();
725 thread_lock(thread);
726 }
727
728 saved_state->rbp = 0;
729 saved_state->rdi = state->rdi;
730 saved_state->rsi = state->rsi;
731 saved_state->rdx = state->rdx;
732 saved_state->rcx = state->rcx;
733 saved_state->r8 = state->r8;
734 saved_state->r9 = state->r9;
735
736 saved_state->isf.rip = state->rip;
737 saved_state->isf.rsp = state->rsp;
738 saved_state->isf.cs = USER64_CS;
739 saved_state->isf.rflags = EFL_USER_SET;
740
741 if (curth != thread) {
742 thread_unlock(thread);
743 splx(s);
744 }
745
746 return KERN_SUCCESS;
747 }
748
749 /*
750 * Initialize the machine-dependent state for a new thread.
751 */
752 void
machine_thread_create(thread_t thread,task_t task,bool first_thread __unused)753 machine_thread_create(
754 thread_t thread,
755 task_t task,
756 bool first_thread __unused)
757 {
758 pcb_t pcb = THREAD_TO_PCB(thread);
759
760 if ((task->t_flags & TF_TECS) || __improbable(force_thread_policy_tecs)) {
761 thread->machine.mthr_do_segchk = MTHR_SEGCHK;
762 } else {
763 thread->machine.mthr_do_segchk = 0;
764 }
765
766 if (task != kernel_task &&
767 __improbable((cpuid_wa_required(CPU_INTEL_RSBST) & CWA_ON) != 0)) {
768 thread->machine.mthr_do_segchk |= MTHR_RSBST;
769 }
770
771 /*
772 * Allocate save frame only if required.
773 */
774 if (pcb->iss == NULL) {
775 assert((get_preemption_level() == 0));
776 pcb->iss = zalloc_flags(iss_zone, Z_WAITOK | Z_NOFAIL);
777 }
778
779 /*
780 * Ensure that the synthesized 32-bit state including
781 * the 64-bit interrupt state can be acommodated in the
782 * 64-bit state we allocate for both 32-bit and 64-bit threads.
783 */
784 assert(sizeof(pcb->iss->ss_32) + sizeof(pcb->iss->ss_64.isf) <=
785 sizeof(pcb->iss->ss_64));
786
787 bzero((char *)pcb->iss, sizeof(x86_saved_state_t));
788
789 bzero(&pcb->lbrs, sizeof(x86_lbrs_t));
790
791 if (task_has_64Bit_addr(task)) {
792 pcb->iss->flavor = x86_SAVED_STATE64;
793
794 pcb->iss->ss_64.isf.cs = USER64_CS;
795 pcb->iss->ss_64.isf.ss = USER_DS;
796 pcb->iss->ss_64.fs = USER_DS;
797 pcb->iss->ss_64.gs = USER_DS;
798 pcb->iss->ss_64.isf.rflags = EFL_USER_SET;
799 } else {
800 pcb->iss->flavor = x86_SAVED_STATE32;
801
802 pcb->iss->ss_32.cs = USER_CS;
803 pcb->iss->ss_32.ss = USER_DS;
804 pcb->iss->ss_32.ds = USER_DS;
805 pcb->iss->ss_32.es = USER_DS;
806 pcb->iss->ss_32.fs = USER_DS;
807 pcb->iss->ss_32.gs = USER_DS;
808 pcb->iss->ss_32.efl = EFL_USER_SET;
809 }
810
811 simple_lock_init(&pcb->lock, 0);
812
813 pcb->cthread_self = 0;
814 pcb->uldt_selector = 0;
815 pcb->thread_gpu_ns = 0;
816 /* Ensure that the "cthread" descriptor describes a valid
817 * segment.
818 */
819 if ((pcb->cthread_desc.access & ACC_P) == 0) {
820 pcb->cthread_desc = *gdt_desc_p(USER_DS);
821 }
822
823
824 pcb->insn_state_copyin_failure_errorcode = 0;
825 if (pcb->insn_state != 0) { /* Reinit for new thread */
826 bzero(pcb->insn_state, sizeof(x86_instruction_state_t));
827 pcb->insn_state->insn_stream_valid_bytes = -1;
828 }
829
830 pcb->insn_copy_optout = (task->t_flags & TF_INSN_COPY_OPTOUT) ? true : false;
831 }
832
833 /*
834 * Machine-dependent cleanup prior to destroying a thread
835 */
836 void
machine_thread_destroy(thread_t thread)837 machine_thread_destroy(
838 thread_t thread)
839 {
840 pcb_t pcb = THREAD_TO_PCB(thread);
841
842 #if HYPERVISOR
843 if (thread->hv_thread_target) {
844 hv_callbacks.thread_destroy(thread->hv_thread_target);
845 thread->hv_thread_target = NULL;
846 }
847 #endif
848
849 if (pcb->ifps != 0) {
850 fpu_free(thread, pcb->ifps);
851 }
852 if (pcb->iss != 0) {
853 zfree(iss_zone, pcb->iss);
854 pcb->iss = 0;
855 }
856 if (pcb->ids) {
857 zfree(ids_zone, pcb->ids);
858 pcb->ids = NULL;
859 }
860
861 if (pcb->insn_state != 0) {
862 kfree_data(pcb->insn_state, sizeof(x86_instruction_state_t));
863 pcb->insn_state = 0;
864 }
865 pcb->insn_state_copyin_failure_errorcode = 0;
866 pcb->insn_copy_optout = false;
867 }
868
869 /*
870 * machine_thread_process_signature
871 *
872 * Called to allow code signature dependent adjustments to the thread
873 * state. Note that this is usually called twice for the main thread:
874 * Once at thread creation by thread_create, when the signature is
875 * potentially not attached yet (which is usually the case for the
876 * first/main thread of a task), and once after the task's signature
877 * has actually been attached.
878 *
879 */
880 kern_return_t
machine_thread_process_signature(thread_t __unused thread,task_t __unused task)881 machine_thread_process_signature(thread_t __unused thread, task_t __unused task)
882 {
883 return KERN_SUCCESS;
884 }
885
886 kern_return_t
machine_thread_set_tsd_base(thread_t thread,mach_vm_offset_t tsd_base)887 machine_thread_set_tsd_base(
888 thread_t thread,
889 mach_vm_offset_t tsd_base)
890 {
891 if (get_threadtask(thread) == kernel_task) {
892 return KERN_INVALID_ARGUMENT;
893 }
894
895 if (thread_is_64bit_addr(thread)) {
896 /* check for canonical address, set 0 otherwise */
897 if (!IS_USERADDR64_CANONICAL(tsd_base)) {
898 tsd_base = 0ULL;
899 }
900 } else {
901 if (tsd_base > UINT32_MAX) {
902 tsd_base = 0ULL;
903 }
904 }
905
906 pcb_t pcb = THREAD_TO_PCB(thread);
907 pcb->cthread_self = tsd_base;
908
909 if (!thread_is_64bit_addr(thread)) {
910 /* Set up descriptor for later use */
911 struct real_descriptor desc = {
912 .limit_low = 1,
913 .limit_high = 0,
914 .base_low = tsd_base & 0xffff,
915 .base_med = (tsd_base >> 16) & 0xff,
916 .base_high = (tsd_base >> 24) & 0xff,
917 .access = ACC_P | ACC_PL_U | ACC_DATA_W,
918 .granularity = SZ_32 | SZ_G,
919 };
920
921 pcb->cthread_desc = desc;
922 saved_state32(pcb->iss)->gs = USER_CTHREAD;
923 }
924
925 /* For current thread, make the TSD base active immediately */
926 if (thread == current_thread()) {
927 if (thread_is_64bit_addr(thread)) {
928 cpu_data_t *cdp;
929
930 mp_disable_preemption();
931 cdp = current_cpu_datap();
932 if ((cdp->cpu_uber.cu_user_gs_base != pcb->cthread_self) ||
933 (pcb->cthread_self != rdmsr64(MSR_IA32_KERNEL_GS_BASE))) {
934 wrmsr64(MSR_IA32_KERNEL_GS_BASE, tsd_base);
935 }
936 cdp->cpu_uber.cu_user_gs_base = tsd_base;
937 mp_enable_preemption();
938 } else {
939 /* assign descriptor */
940 mp_disable_preemption();
941 *ldt_desc_p(USER_CTHREAD) = pcb->cthread_desc;
942 mp_enable_preemption();
943 }
944 }
945
946 return KERN_SUCCESS;
947 }
948
949 void
machine_tecs(thread_t thr)950 machine_tecs(thread_t thr)
951 {
952 if (tecs_mode_supported) {
953 thr->machine.mthr_do_segchk = 1;
954 }
955 }
956
957 void
machine_thread_set_insn_copy_optout(thread_t thr)958 machine_thread_set_insn_copy_optout(thread_t thr)
959 {
960 thr->machine.insn_copy_optout = true;
961 }
962
963 int
machine_csv(cpuvn_e cve)964 machine_csv(cpuvn_e cve)
965 {
966 switch (cve) {
967 case CPUVN_CI:
968 return (cpuid_wa_required(CPU_INTEL_SEGCHK) & CWA_ON) != 0;
969
970 default:
971 break;
972 }
973
974 return 0;
975 }
976