1 /*
2 * Copyright (c) 2000-2020 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 #include <vm/vm_page.h>
32 #include <pexpert/pexpert.h>
33
34 #include <i386/cpu_threads.h>
35 #include <i386/cpuid.h>
36 #include <i386/machine_routines.h>
37
38 int force_tecs_at_idle;
39 int tecs_mode_supported;
40
41 static boolean_t cpuid_dbg
42 #if DEBUG
43 = TRUE;
44 #else
45 = FALSE;
46 #endif
47 #define DBG(x...) \
48 do { \
49 if (cpuid_dbg) \
50 kprintf(x); \
51 } while (0) \
52
53 #define min(a, b) ((a) < (b) ? (a) : (b))
54 #define quad(hi, lo) (((uint64_t)(hi)) << 32 | (lo))
55
56 /*
57 * Leaf 2 cache descriptor encodings.
58 */
59 typedef enum {
60 _NULL_, /* NULL (empty) descriptor */
61 CACHE, /* Cache */
62 TLB, /* TLB */
63 STLB, /* Shared second-level unified TLB */
64 PREFETCH /* Prefetch size */
65 } cpuid_leaf2_desc_type_t;
66
67 typedef enum {
68 NA, /* Not Applicable */
69 FULLY, /* Fully-associative */
70 TRACE, /* Trace Cache (P4 only) */
71 INST, /* Instruction TLB */
72 DATA, /* Data TLB */
73 DATA0, /* Data TLB, 1st level */
74 DATA1, /* Data TLB, 2nd level */
75 L1, /* L1 (unified) cache */
76 L1_INST, /* L1 Instruction cache */
77 L1_DATA, /* L1 Data cache */
78 L2, /* L2 (unified) cache */
79 L3, /* L3 (unified) cache */
80 L2_2LINESECTOR, /* L2 (unified) cache with 2 lines per sector */
81 L3_2LINESECTOR, /* L3(unified) cache with 2 lines per sector */
82 SMALL, /* Small page TLB */
83 LARGE, /* Large page TLB */
84 BOTH /* Small and Large page TLB */
85 } cpuid_leaf2_qualifier_t;
86
87 typedef struct cpuid_cache_descriptor {
88 uint8_t value; /* descriptor code */
89 uint8_t type; /* cpuid_leaf2_desc_type_t */
90 uint8_t level; /* level of cache/TLB hierachy */
91 uint8_t ways; /* wayness of cache */
92 uint16_t size; /* cachesize or TLB pagesize */
93 uint16_t entries; /* number of TLB entries or linesize */
94 } cpuid_cache_descriptor_t;
95
96 /*
97 * These multipliers are used to encode 1*K .. 64*M in a 16 bit size field
98 */
99 #define K (1)
100 #define M (1024)
101
102 /*
103 * Intel cache descriptor table:
104 */
105 static cpuid_cache_descriptor_t intel_cpuid_leaf2_descriptor_table[] = {
106 // -------------------------------------------------------
107 // value type level ways size entries
108 // -------------------------------------------------------
109 { 0x00, _NULL_, NA, NA, NA, NA },
110 { 0x01, TLB, INST, 4, SMALL, 32 },
111 { 0x02, TLB, INST, FULLY, LARGE, 2 },
112 { 0x03, TLB, DATA, 4, SMALL, 64 },
113 { 0x04, TLB, DATA, 4, LARGE, 8 },
114 { 0x05, TLB, DATA1, 4, LARGE, 32 },
115 { 0x06, CACHE, L1_INST, 4, 8 * K, 32 },
116 { 0x08, CACHE, L1_INST, 4, 16 * K, 32 },
117 { 0x09, CACHE, L1_INST, 4, 32 * K, 64 },
118 { 0x0A, CACHE, L1_DATA, 2, 8 * K, 32 },
119 { 0x0B, TLB, INST, 4, LARGE, 4 },
120 { 0x0C, CACHE, L1_DATA, 4, 16 * K, 32 },
121 { 0x0D, CACHE, L1_DATA, 4, 16 * K, 64 },
122 { 0x0E, CACHE, L1_DATA, 6, 24 * K, 64 },
123 { 0x21, CACHE, L2, 8, 256 * K, 64 },
124 { 0x22, CACHE, L3_2LINESECTOR, 4, 512 * K, 64 },
125 { 0x23, CACHE, L3_2LINESECTOR, 8, 1 * M, 64 },
126 { 0x25, CACHE, L3_2LINESECTOR, 8, 2 * M, 64 },
127 { 0x29, CACHE, L3_2LINESECTOR, 8, 4 * M, 64 },
128 { 0x2C, CACHE, L1_DATA, 8, 32 * K, 64 },
129 { 0x30, CACHE, L1_INST, 8, 32 * K, 64 },
130 { 0x40, CACHE, L2, NA, 0, NA },
131 { 0x41, CACHE, L2, 4, 128 * K, 32 },
132 { 0x42, CACHE, L2, 4, 256 * K, 32 },
133 { 0x43, CACHE, L2, 4, 512 * K, 32 },
134 { 0x44, CACHE, L2, 4, 1 * M, 32 },
135 { 0x45, CACHE, L2, 4, 2 * M, 32 },
136 { 0x46, CACHE, L3, 4, 4 * M, 64 },
137 { 0x47, CACHE, L3, 8, 8 * M, 64 },
138 { 0x48, CACHE, L2, 12, 3 * M, 64 },
139 { 0x49, CACHE, L2, 16, 4 * M, 64 },
140 { 0x4A, CACHE, L3, 12, 6 * M, 64 },
141 { 0x4B, CACHE, L3, 16, 8 * M, 64 },
142 { 0x4C, CACHE, L3, 12, 12 * M, 64 },
143 { 0x4D, CACHE, L3, 16, 16 * M, 64 },
144 { 0x4E, CACHE, L2, 24, 6 * M, 64 },
145 { 0x4F, TLB, INST, NA, SMALL, 32 },
146 { 0x50, TLB, INST, NA, BOTH, 64 },
147 { 0x51, TLB, INST, NA, BOTH, 128 },
148 { 0x52, TLB, INST, NA, BOTH, 256 },
149 { 0x55, TLB, INST, FULLY, BOTH, 7 },
150 { 0x56, TLB, DATA0, 4, LARGE, 16 },
151 { 0x57, TLB, DATA0, 4, SMALL, 16 },
152 { 0x59, TLB, DATA0, FULLY, SMALL, 16 },
153 { 0x5A, TLB, DATA0, 4, LARGE, 32 },
154 { 0x5B, TLB, DATA, NA, BOTH, 64 },
155 { 0x5C, TLB, DATA, NA, BOTH, 128 },
156 { 0x5D, TLB, DATA, NA, BOTH, 256 },
157 { 0x60, CACHE, L1, 16 * K, 8, 64 },
158 { 0x61, CACHE, L1, 4, 8 * K, 64 },
159 { 0x62, CACHE, L1, 4, 16 * K, 64 },
160 { 0x63, CACHE, L1, 4, 32 * K, 64 },
161 { 0x70, CACHE, TRACE, 8, 12 * K, NA },
162 { 0x71, CACHE, TRACE, 8, 16 * K, NA },
163 { 0x72, CACHE, TRACE, 8, 32 * K, NA },
164 { 0x76, TLB, INST, NA, BOTH, 8 },
165 { 0x78, CACHE, L2, 4, 1 * M, 64 },
166 { 0x79, CACHE, L2_2LINESECTOR, 8, 128 * K, 64 },
167 { 0x7A, CACHE, L2_2LINESECTOR, 8, 256 * K, 64 },
168 { 0x7B, CACHE, L2_2LINESECTOR, 8, 512 * K, 64 },
169 { 0x7C, CACHE, L2_2LINESECTOR, 8, 1 * M, 64 },
170 { 0x7D, CACHE, L2, 8, 2 * M, 64 },
171 { 0x7F, CACHE, L2, 2, 512 * K, 64 },
172 { 0x80, CACHE, L2, 8, 512 * K, 64 },
173 { 0x82, CACHE, L2, 8, 256 * K, 32 },
174 { 0x83, CACHE, L2, 8, 512 * K, 32 },
175 { 0x84, CACHE, L2, 8, 1 * M, 32 },
176 { 0x85, CACHE, L2, 8, 2 * M, 32 },
177 { 0x86, CACHE, L2, 4, 512 * K, 64 },
178 { 0x87, CACHE, L2, 8, 1 * M, 64 },
179 { 0xB0, TLB, INST, 4, SMALL, 128 },
180 { 0xB1, TLB, INST, 4, LARGE, 8 },
181 { 0xB2, TLB, INST, 4, SMALL, 64 },
182 { 0xB3, TLB, DATA, 4, SMALL, 128 },
183 { 0xB4, TLB, DATA1, 4, SMALL, 256 },
184 { 0xB5, TLB, DATA1, 8, SMALL, 64 },
185 { 0xB6, TLB, DATA1, 8, SMALL, 128 },
186 { 0xBA, TLB, DATA1, 4, BOTH, 64 },
187 { 0xC1, STLB, DATA1, 8, SMALL, 1024},
188 { 0xCA, STLB, DATA1, 4, SMALL, 512 },
189 { 0xD0, CACHE, L3, 4, 512 * K, 64 },
190 { 0xD1, CACHE, L3, 4, 1 * M, 64 },
191 { 0xD2, CACHE, L3, 4, 2 * M, 64 },
192 { 0xD3, CACHE, L3, 4, 4 * M, 64 },
193 { 0xD4, CACHE, L3, 4, 8 * M, 64 },
194 { 0xD6, CACHE, L3, 8, 1 * M, 64 },
195 { 0xD7, CACHE, L3, 8, 2 * M, 64 },
196 { 0xD8, CACHE, L3, 8, 4 * M, 64 },
197 { 0xD9, CACHE, L3, 8, 8 * M, 64 },
198 { 0xDA, CACHE, L3, 8, 12 * M, 64 },
199 { 0xDC, CACHE, L3, 12, 1536 * K, 64 },
200 { 0xDD, CACHE, L3, 12, 3 * M, 64 },
201 { 0xDE, CACHE, L3, 12, 6 * M, 64 },
202 { 0xDF, CACHE, L3, 12, 12 * M, 64 },
203 { 0xE0, CACHE, L3, 12, 18 * M, 64 },
204 { 0xE2, CACHE, L3, 16, 2 * M, 64 },
205 { 0xE3, CACHE, L3, 16, 4 * M, 64 },
206 { 0xE4, CACHE, L3, 16, 8 * M, 64 },
207 { 0xE5, CACHE, L3, 16, 16 * M, 64 },
208 { 0xE6, CACHE, L3, 16, 24 * M, 64 },
209 { 0xF0, PREFETCH, NA, NA, 64, NA },
210 { 0xF1, PREFETCH, NA, NA, 128, NA },
211 { 0xFF, CACHE, NA, NA, 0, NA }
212 };
213 #define INTEL_LEAF2_DESC_NUM (sizeof(intel_cpuid_leaf2_descriptor_table) / \
214 sizeof(cpuid_cache_descriptor_t))
215
216 boolean_t cpuid_tsx_disabled = false; /* true if XNU disabled TSX */
217 boolean_t cpuid_tsx_supported = false;
218
219 static void do_cwas(i386_cpu_info_t *cpuinfo, boolean_t on_slave);
220 static void cpuid_do_precpuid_was(void);
221
222 static void cpuid_vmm_detect_pv_interface(i386_vmm_info_t *info_p, const char *signature,
223 bool (*)(i386_vmm_info_t*, const uint32_t, const uint32_t));
224 static bool cpuid_vmm_detect_applepv_features(i386_vmm_info_t *info_p, const uint32_t base, const uint32_t max_leaf);
225
226 static inline cpuid_cache_descriptor_t *
cpuid_leaf2_find(uint8_t value)227 cpuid_leaf2_find(uint8_t value)
228 {
229 unsigned int i;
230
231 for (i = 0; i < INTEL_LEAF2_DESC_NUM; i++) {
232 if (intel_cpuid_leaf2_descriptor_table[i].value == value) {
233 return &intel_cpuid_leaf2_descriptor_table[i];
234 }
235 }
236 return NULL;
237 }
238
239 /*
240 * CPU identification routines.
241 */
242
243 static i386_cpu_info_t cpuid_cpu_info;
244 static i386_cpu_info_t *cpuid_cpu_infop = NULL;
245
246 static void
cpuid_fn(uint32_t selector,uint32_t * result)247 cpuid_fn(uint32_t selector, uint32_t *result)
248 {
249 do_cpuid(selector, result);
250 DBG("cpuid_fn(0x%08x) eax:0x%08x ebx:0x%08x ecx:0x%08x edx:0x%08x\n",
251 selector, result[0], result[1], result[2], result[3]);
252 }
253
254 static const char *cache_type_str[LCACHE_MAX] = {
255 "Lnone", "L1I", "L1D", "L2U", "L3U"
256 };
257
258 static void
do_cwas(i386_cpu_info_t * cpuinfo,boolean_t on_slave)259 do_cwas(i386_cpu_info_t *cpuinfo, boolean_t on_slave)
260 {
261 extern int force_thread_policy_tecs;
262 cwa_classifier_e wa_reqd;
263
264 /*
265 * Workaround for reclaiming perf counter 3 due to TSX memory ordering erratum.
266 * This workaround does not support being forcibly set (since an MSR must be
267 * enumerated, lest we #GP when forced to access it.)
268 *
269 * Note that if disabling TSX is supported, disablement is prefered over forcing
270 * TSX transactions to abort.
271 */
272 if (cpuid_wa_required(CPU_INTEL_TSXDA) == CWA_ON) {
273 /* This must be executed on all logical processors */
274 wrmsr64(MSR_IA32_TSX_CTRL, MSR_IA32_TSXCTRL_TSX_CPU_CLEAR | MSR_IA32_TSXCTRL_RTM_DISABLE);
275 } else if (cpuid_wa_required(CPU_INTEL_TSXFA) == CWA_ON) {
276 /* This must be executed on all logical processors */
277 wrmsr64(MSR_IA32_TSX_FORCE_ABORT,
278 rdmsr64(MSR_IA32_TSX_FORCE_ABORT) | MSR_IA32_TSXFA_RTM_FORCE_ABORT);
279 }
280
281 if (((wa_reqd = cpuid_wa_required(CPU_INTEL_SRBDS)) & CWA_ON) != 0 &&
282 ((wa_reqd & CWA_FORCE_ON) == CWA_ON ||
283 (cpuinfo->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_SRBDS_CTRL) != 0)) {
284 /* This must be executed on all logical processors */
285 uint64_t mcuoptctrl = rdmsr64(MSR_IA32_MCU_OPT_CTRL);
286 mcuoptctrl |= MSR_IA32_MCUOPTCTRL_RNGDS_MITG_DIS;
287 wrmsr64(MSR_IA32_MCU_OPT_CTRL, mcuoptctrl);
288 }
289
290 if (on_slave) {
291 return;
292 }
293
294 switch (cpuid_wa_required(CPU_INTEL_SEGCHK)) {
295 case CWA_FORCE_ON:
296 force_thread_policy_tecs = 1;
297
298 /* If hyperthreaded, enable idle workaround */
299 if (cpuinfo->thread_count > cpuinfo->core_count) {
300 force_tecs_at_idle = 1;
301 }
302
303 OS_FALLTHROUGH;
304 case CWA_ON:
305 tecs_mode_supported = 1;
306 break;
307
308 case CWA_FORCE_OFF:
309 case CWA_OFF:
310 tecs_mode_supported = 0;
311 force_tecs_at_idle = 0;
312 force_thread_policy_tecs = 0;
313 break;
314
315 default:
316 break;
317 }
318 }
319
320 void
cpuid_do_was(void)321 cpuid_do_was(void)
322 {
323 do_cwas(cpuid_info(), TRUE);
324 }
325
326 /* this function is Intel-specific */
327 static void
cpuid_set_cache_info(i386_cpu_info_t * info_p)328 cpuid_set_cache_info( i386_cpu_info_t * info_p )
329 {
330 uint32_t cpuid_result[4];
331 uint32_t reg[4];
332 uint32_t index;
333 uint32_t linesizes[LCACHE_MAX];
334 unsigned int i;
335 unsigned int j;
336 boolean_t cpuid_deterministic_supported = FALSE;
337
338 DBG("cpuid_set_cache_info(%p)\n", info_p);
339
340 bzero( linesizes, sizeof(linesizes));
341
342 /* Get processor cache descriptor info using leaf 2. We don't use
343 * this internally, but must publish it for KEXTs.
344 */
345 cpuid_fn(2, cpuid_result);
346 for (j = 0; j < 4; j++) {
347 if ((cpuid_result[j] >> 31) == 1) { /* bit31 is validity */
348 continue;
349 }
350 ((uint32_t *)(void *)info_p->cache_info)[j] = cpuid_result[j];
351 }
352 /* first byte gives number of cpuid calls to get all descriptors */
353 for (i = 1; i < info_p->cache_info[0]; i++) {
354 if (i * 16 > sizeof(info_p->cache_info)) {
355 break;
356 }
357 cpuid_fn(2, cpuid_result);
358 for (j = 0; j < 4; j++) {
359 if ((cpuid_result[j] >> 31) == 1) {
360 continue;
361 }
362 ((uint32_t *)(void *)info_p->cache_info)[4 * i + j] =
363 cpuid_result[j];
364 }
365 }
366
367 /*
368 * Get cache info using leaf 4, the "deterministic cache parameters."
369 * Most processors Mac OS X supports implement this flavor of CPUID.
370 * Loop over each cache on the processor.
371 */
372 cpuid_fn(0, cpuid_result);
373 if (cpuid_result[eax] >= 4) {
374 cpuid_deterministic_supported = TRUE;
375 }
376
377 for (index = 0; cpuid_deterministic_supported; index++) {
378 cache_type_t type = Lnone;
379 uint32_t cache_type;
380 uint32_t cache_level;
381 uint32_t cache_sharing;
382 uint32_t cache_linesize;
383 uint32_t cache_sets;
384 uint32_t cache_associativity;
385 uint32_t cache_size;
386 uint32_t cache_partitions;
387 uint32_t colors;
388
389 reg[eax] = 4; /* cpuid request 4 */
390 reg[ecx] = index; /* index starting at 0 */
391 cpuid(reg);
392 DBG("cpuid(4) index=%d eax=0x%x\n", index, reg[eax]);
393 cache_type = bitfield32(reg[eax], 4, 0);
394 if (cache_type == 0) {
395 break; /* no more caches */
396 }
397 cache_level = bitfield32(reg[eax], 7, 5);
398 cache_sharing = bitfield32(reg[eax], 25, 14) + 1;
399 info_p->cpuid_cores_per_package
400 = bitfield32(reg[eax], 31, 26) + 1;
401 cache_linesize = bitfield32(reg[ebx], 11, 0) + 1;
402 cache_partitions = bitfield32(reg[ebx], 21, 12) + 1;
403 cache_associativity = bitfield32(reg[ebx], 31, 22) + 1;
404 cache_sets = bitfield32(reg[ecx], 31, 0) + 1;
405
406 /* Map type/levels returned by CPUID into cache_type_t */
407 switch (cache_level) {
408 case 1:
409 type = cache_type == 1 ? L1D :
410 cache_type == 2 ? L1I :
411 Lnone;
412 break;
413 case 2:
414 type = cache_type == 3 ? L2U :
415 Lnone;
416 break;
417 case 3:
418 type = cache_type == 3 ? L3U :
419 Lnone;
420 break;
421 default:
422 type = Lnone;
423 }
424
425 /* The total size of a cache is:
426 * ( linesize * sets * associativity * partitions )
427 */
428 if (type != Lnone) {
429 cache_size = cache_linesize * cache_sets *
430 cache_associativity * cache_partitions;
431 info_p->cache_size[type] = cache_size;
432 info_p->cache_sharing[type] = cache_sharing;
433 info_p->cache_partitions[type] = cache_partitions;
434 linesizes[type] = cache_linesize;
435
436 DBG(" cache_size[%s] : %d\n",
437 cache_type_str[type], cache_size);
438 DBG(" cache_sharing[%s] : %d\n",
439 cache_type_str[type], cache_sharing);
440 DBG(" cache_partitions[%s]: %d\n",
441 cache_type_str[type], cache_partitions);
442
443 /*
444 * Overwrite associativity determined via
445 * CPUID.0x80000006 -- this leaf is more
446 * accurate
447 */
448 if (type == L2U) {
449 info_p->cpuid_cache_L2_associativity = cache_associativity;
450 }
451 /*
452 * Adjust #sets to account for the N CBos
453 * This is because addresses are hashed across CBos
454 */
455 if (type == L3U && info_p->core_count) {
456 cache_sets = cache_sets / info_p->core_count;
457 }
458
459 /* Compute the number of page colors for this cache,
460 * which is:
461 * ( linesize * sets ) / page_size
462 *
463 * To help visualize this, consider two views of a
464 * physical address. To the cache, it is composed
465 * of a line offset, a set selector, and a tag.
466 * To VM, it is composed of a page offset, a page
467 * color, and other bits in the pageframe number:
468 *
469 * +-----------------+---------+--------+
470 * cache: | tag | set | offset |
471 * +-----------------+---------+--------+
472 *
473 * +-----------------+-------+----------+
474 * VM: | don't care | color | pg offset|
475 * +-----------------+-------+----------+
476 *
477 * The color is those bits in (set+offset) not covered
478 * by the page offset.
479 */
480 colors = (cache_linesize * cache_sets) >> 12;
481
482 if (colors > vm_cache_geometry_colors) {
483 vm_cache_geometry_colors = colors;
484 }
485 }
486 }
487 DBG(" vm_cache_geometry_colors: %d\n", vm_cache_geometry_colors);
488
489 /*
490 * If deterministic cache parameters are not available, use
491 * something else
492 */
493 if (info_p->cpuid_cores_per_package == 0) {
494 info_p->cpuid_cores_per_package = 1;
495
496 /* cpuid define in 1024 quantities */
497 info_p->cache_size[L2U] = info_p->cpuid_cache_size * 1024;
498 info_p->cache_sharing[L2U] = 1;
499 info_p->cache_partitions[L2U] = 1;
500
501 linesizes[L2U] = info_p->cpuid_cache_linesize;
502
503 DBG(" cache_size[L2U] : %d\n",
504 info_p->cache_size[L2U]);
505 DBG(" cache_sharing[L2U] : 1\n");
506 DBG(" cache_partitions[L2U]: 1\n");
507 DBG(" linesizes[L2U] : %d\n",
508 info_p->cpuid_cache_linesize);
509 }
510
511 /*
512 * What linesize to publish? We use the L2 linesize if any,
513 * else the L1D.
514 */
515 if (linesizes[L2U]) {
516 info_p->cache_linesize = linesizes[L2U];
517 } else if (linesizes[L1D]) {
518 info_p->cache_linesize = linesizes[L1D];
519 } else {
520 panic("no linesize");
521 }
522 DBG(" cache_linesize : %d\n", info_p->cache_linesize);
523
524 /*
525 * Extract and publish TLB information from Leaf 2 descriptors.
526 */
527 DBG(" %ld leaf2 descriptors:\n", sizeof(info_p->cache_info));
528 for (i = 1; i < sizeof(info_p->cache_info); i++) {
529 cpuid_cache_descriptor_t *descp;
530 int id;
531 int level;
532 int page;
533
534 DBG(" 0x%02x", info_p->cache_info[i]);
535 descp = cpuid_leaf2_find(info_p->cache_info[i]);
536 if (descp == NULL) {
537 continue;
538 }
539
540 switch (descp->type) {
541 case TLB:
542 page = (descp->size == SMALL) ? TLB_SMALL : TLB_LARGE;
543 /* determine I or D: */
544 switch (descp->level) {
545 case INST:
546 id = TLB_INST;
547 break;
548 case DATA:
549 case DATA0:
550 case DATA1:
551 id = TLB_DATA;
552 break;
553 default:
554 continue;
555 }
556 /* determine level: */
557 switch (descp->level) {
558 case DATA1:
559 level = 1;
560 break;
561 default:
562 level = 0;
563 }
564 info_p->cpuid_tlb[id][page][level] = descp->entries;
565 break;
566 case STLB:
567 info_p->cpuid_stlb = descp->entries;
568 }
569 }
570 DBG("\n");
571 }
572
573 static void
cpuid_set_generic_info(i386_cpu_info_t * info_p)574 cpuid_set_generic_info(i386_cpu_info_t *info_p)
575 {
576 uint32_t reg[4];
577 char str[128], *p;
578
579 DBG("cpuid_set_generic_info(%p)\n", info_p);
580
581 /* do cpuid 0 to get vendor */
582 cpuid_fn(0, reg);
583 info_p->cpuid_max_basic = reg[eax];
584 bcopy((char *)®[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
585 bcopy((char *)®[ecx], &info_p->cpuid_vendor[8], 4);
586 bcopy((char *)®[edx], &info_p->cpuid_vendor[4], 4);
587 info_p->cpuid_vendor[12] = 0;
588
589 /* get extended cpuid results */
590 cpuid_fn(0x80000000, reg);
591 info_p->cpuid_max_ext = reg[eax];
592
593 /* check to see if we can get brand string */
594 if (info_p->cpuid_max_ext >= 0x80000004) {
595 /*
596 * The brand string 48 bytes (max), guaranteed to
597 * be NUL terminated.
598 */
599 cpuid_fn(0x80000002, reg);
600 bcopy((char *)reg, &str[0], 16);
601 cpuid_fn(0x80000003, reg);
602 bcopy((char *)reg, &str[16], 16);
603 cpuid_fn(0x80000004, reg);
604 bcopy((char *)reg, &str[32], 16);
605 for (p = str; *p != '\0'; p++) {
606 if (*p != ' ') {
607 break;
608 }
609 }
610 strlcpy(info_p->cpuid_brand_string,
611 p, sizeof(info_p->cpuid_brand_string));
612
613 if (!strncmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN,
614 min(sizeof(info_p->cpuid_brand_string),
615 strlen(CPUID_STRING_UNKNOWN) + 1))) {
616 /*
617 * This string means we have a firmware-programmable brand string,
618 * and the firmware couldn't figure out what sort of CPU we have.
619 */
620 info_p->cpuid_brand_string[0] = '\0';
621 }
622 }
623
624 /* Get cache and addressing info. */
625 if (info_p->cpuid_max_ext >= 0x80000006) {
626 uint32_t assoc;
627 cpuid_fn(0x80000006, reg);
628 info_p->cpuid_cache_linesize = bitfield32(reg[ecx], 7, 0);
629 assoc = bitfield32(reg[ecx], 15, 12);
630 /*
631 * L2 associativity is encoded, though in an insufficiently
632 * descriptive fashion, e.g. 24-way is mapped to 16-way.
633 * Represent a fully associative cache as 0xFFFF.
634 * Overwritten by associativity as determined via CPUID.4
635 * if available.
636 */
637 if (assoc == 6) {
638 assoc = 8;
639 } else if (assoc == 8) {
640 assoc = 16;
641 } else if (assoc == 0xF) {
642 assoc = 0xFFFF;
643 }
644 info_p->cpuid_cache_L2_associativity = assoc;
645 info_p->cpuid_cache_size = bitfield32(reg[ecx], 31, 16);
646 cpuid_fn(0x80000008, reg);
647 info_p->cpuid_address_bits_physical =
648 bitfield32(reg[eax], 7, 0);
649 info_p->cpuid_address_bits_virtual =
650 bitfield32(reg[eax], 15, 8);
651 }
652
653 /*
654 * Get processor signature and decode
655 * and bracket this with the approved procedure for reading the
656 * the microcode version number a.k.a. signature a.k.a. BIOS ID
657 */
658 wrmsr64(MSR_IA32_BIOS_SIGN_ID, 0);
659 cpuid_fn(1, reg);
660 info_p->cpuid_microcode_version =
661 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);
662 info_p->cpuid_signature = reg[eax];
663 info_p->cpuid_stepping = bitfield32(reg[eax], 3, 0);
664 info_p->cpuid_model = bitfield32(reg[eax], 7, 4);
665 info_p->cpuid_family = bitfield32(reg[eax], 11, 8);
666 info_p->cpuid_type = bitfield32(reg[eax], 13, 12);
667 info_p->cpuid_extmodel = bitfield32(reg[eax], 19, 16);
668 info_p->cpuid_extfamily = bitfield32(reg[eax], 27, 20);
669 info_p->cpuid_brand = bitfield32(reg[ebx], 7, 0);
670 info_p->cpuid_features = quad(reg[ecx], reg[edx]);
671
672 /* Get "processor flag"; necessary for microcode update matching */
673 info_p->cpuid_processor_flag = (rdmsr64(MSR_IA32_PLATFORM_ID) >> 50) & 0x7;
674
675 /* Fold extensions into family/model */
676 if (info_p->cpuid_family == 0x0f) {
677 info_p->cpuid_family += info_p->cpuid_extfamily;
678 }
679 if (info_p->cpuid_family == 0x0f || info_p->cpuid_family == 0x06) {
680 info_p->cpuid_model += (info_p->cpuid_extmodel << 4);
681 }
682
683 if (info_p->cpuid_features & CPUID_FEATURE_HTT) {
684 info_p->cpuid_logical_per_package =
685 bitfield32(reg[ebx], 23, 16);
686 } else {
687 info_p->cpuid_logical_per_package = 1;
688 }
689
690 if (info_p->cpuid_max_ext >= 0x80000001) {
691 cpuid_fn(0x80000001, reg);
692 info_p->cpuid_extfeatures =
693 quad(reg[ecx], reg[edx]);
694 }
695
696 DBG(" max_basic : %d\n", info_p->cpuid_max_basic);
697 DBG(" max_ext : 0x%08x\n", info_p->cpuid_max_ext);
698 DBG(" vendor : %s\n", info_p->cpuid_vendor);
699 DBG(" brand_string : %s\n", info_p->cpuid_brand_string);
700 DBG(" signature : 0x%08x\n", info_p->cpuid_signature);
701 DBG(" stepping : %d\n", info_p->cpuid_stepping);
702 DBG(" model : %d\n", info_p->cpuid_model);
703 DBG(" family : %d\n", info_p->cpuid_family);
704 DBG(" type : %d\n", info_p->cpuid_type);
705 DBG(" extmodel : %d\n", info_p->cpuid_extmodel);
706 DBG(" extfamily : %d\n", info_p->cpuid_extfamily);
707 DBG(" brand : %d\n", info_p->cpuid_brand);
708 DBG(" features : 0x%016llx\n", info_p->cpuid_features);
709 DBG(" extfeatures : 0x%016llx\n", info_p->cpuid_extfeatures);
710 DBG(" logical_per_package : %d\n", info_p->cpuid_logical_per_package);
711 DBG(" microcode_version : 0x%08x\n", info_p->cpuid_microcode_version);
712
713 /* Fold in the Invariant TSC feature bit, if present */
714 if (info_p->cpuid_max_ext >= 0x80000007) {
715 cpuid_fn(0x80000007, reg);
716 info_p->cpuid_extfeatures |=
717 reg[edx] & (uint32_t)CPUID_EXTFEATURE_TSCI;
718 DBG(" extfeatures : 0x%016llx\n",
719 info_p->cpuid_extfeatures);
720 }
721
722 if (info_p->cpuid_max_basic >= 0x5) {
723 cpuid_mwait_leaf_t *cmp = &info_p->cpuid_mwait_leaf;
724
725 /*
726 * Extract the Monitor/Mwait Leaf info:
727 */
728 cpuid_fn(5, reg);
729 cmp->linesize_min = reg[eax];
730 cmp->linesize_max = reg[ebx];
731 cmp->extensions = reg[ecx];
732 cmp->sub_Cstates = reg[edx];
733 info_p->cpuid_mwait_leafp = cmp;
734
735 DBG(" Monitor/Mwait Leaf:\n");
736 DBG(" linesize_min : %d\n", cmp->linesize_min);
737 DBG(" linesize_max : %d\n", cmp->linesize_max);
738 DBG(" extensions : %d\n", cmp->extensions);
739 DBG(" sub_Cstates : 0x%08x\n", cmp->sub_Cstates);
740 }
741
742 if (info_p->cpuid_max_basic >= 0x6) {
743 cpuid_thermal_leaf_t *ctp = &info_p->cpuid_thermal_leaf;
744
745 /*
746 * The thermal and Power Leaf:
747 */
748 cpuid_fn(6, reg);
749 ctp->sensor = bitfield32(reg[eax], 0, 0);
750 ctp->dynamic_acceleration = bitfield32(reg[eax], 1, 1);
751 ctp->invariant_APIC_timer = bitfield32(reg[eax], 2, 2);
752 ctp->core_power_limits = bitfield32(reg[eax], 4, 4);
753 ctp->fine_grain_clock_mod = bitfield32(reg[eax], 5, 5);
754 ctp->package_thermal_intr = bitfield32(reg[eax], 6, 6);
755 ctp->thresholds = bitfield32(reg[ebx], 3, 0);
756 ctp->ACNT_MCNT = bitfield32(reg[ecx], 0, 0);
757 ctp->hardware_feedback = bitfield32(reg[ecx], 1, 1);
758 ctp->energy_policy = bitfield32(reg[ecx], 3, 3);
759 info_p->cpuid_thermal_leafp = ctp;
760
761 DBG(" Thermal/Power Leaf:\n");
762 DBG(" sensor : %d\n", ctp->sensor);
763 DBG(" dynamic_acceleration : %d\n", ctp->dynamic_acceleration);
764 DBG(" invariant_APIC_timer : %d\n", ctp->invariant_APIC_timer);
765 DBG(" core_power_limits : %d\n", ctp->core_power_limits);
766 DBG(" fine_grain_clock_mod : %d\n", ctp->fine_grain_clock_mod);
767 DBG(" package_thermal_intr : %d\n", ctp->package_thermal_intr);
768 DBG(" thresholds : %d\n", ctp->thresholds);
769 DBG(" ACNT_MCNT : %d\n", ctp->ACNT_MCNT);
770 DBG(" ACNT2 : %d\n", ctp->hardware_feedback);
771 DBG(" energy_policy : %d\n", ctp->energy_policy);
772 }
773
774 if (info_p->cpuid_max_basic >= 0xa) {
775 cpuid_arch_perf_leaf_t *capp = &info_p->cpuid_arch_perf_leaf;
776
777 /*
778 * Architectural Performance Monitoring Leaf:
779 */
780 cpuid_fn(0xa, reg);
781 capp->version = bitfield32(reg[eax], 7, 0);
782 capp->number = bitfield32(reg[eax], 15, 8);
783 capp->width = bitfield32(reg[eax], 23, 16);
784 capp->events_number = bitfield32(reg[eax], 31, 24);
785 capp->events = reg[ebx];
786 capp->fixed_number = bitfield32(reg[edx], 4, 0);
787 capp->fixed_width = bitfield32(reg[edx], 12, 5);
788 info_p->cpuid_arch_perf_leafp = capp;
789
790 DBG(" Architectural Performance Monitoring Leaf:\n");
791 DBG(" version : %d\n", capp->version);
792 DBG(" number : %d\n", capp->number);
793 DBG(" width : %d\n", capp->width);
794 DBG(" events_number : %d\n", capp->events_number);
795 DBG(" events : %d\n", capp->events);
796 DBG(" fixed_number : %d\n", capp->fixed_number);
797 DBG(" fixed_width : %d\n", capp->fixed_width);
798 }
799
800 if (info_p->cpuid_max_basic >= 0xd) {
801 cpuid_xsave_leaf_t *xsp;
802 /*
803 * XSAVE Features:
804 */
805 xsp = &info_p->cpuid_xsave_leaf[0];
806 info_p->cpuid_xsave_leafp = xsp;
807 xsp->extended_state[eax] = 0xd;
808 xsp->extended_state[ecx] = 0;
809 cpuid(xsp->extended_state);
810 DBG(" XSAVE Main leaf:\n");
811 DBG(" EAX : 0x%x\n", xsp->extended_state[eax]);
812 DBG(" EBX : 0x%x\n", xsp->extended_state[ebx]);
813 DBG(" ECX : 0x%x\n", xsp->extended_state[ecx]);
814 DBG(" EDX : 0x%x\n", xsp->extended_state[edx]);
815
816 xsp = &info_p->cpuid_xsave_leaf[1];
817 xsp->extended_state[eax] = 0xd;
818 xsp->extended_state[ecx] = 1;
819 cpuid(xsp->extended_state);
820 DBG(" XSAVE Sub-leaf1:\n");
821 DBG(" EAX : 0x%x\n", xsp->extended_state[eax]);
822 DBG(" EBX : 0x%x\n", xsp->extended_state[ebx]);
823 DBG(" ECX : 0x%x\n", xsp->extended_state[ecx]);
824 DBG(" EDX : 0x%x\n", xsp->extended_state[edx]);
825 }
826
827 if (info_p->cpuid_model >= CPUID_MODEL_IVYBRIDGE) {
828 /*
829 * Leaf7 Features:
830 */
831 cpuid_fn(0x7, reg);
832 info_p->cpuid_leaf7_features = quad(reg[ecx], reg[ebx]);
833 info_p->cpuid_leaf7_extfeatures = reg[edx];
834
835 cpuid_tsx_supported = (reg[ebx] & (CPUID_LEAF7_FEATURE_HLE | CPUID_LEAF7_FEATURE_RTM)) != 0;
836
837 DBG(" Feature Leaf7:\n");
838 DBG(" EBX : 0x%x\n", reg[ebx]);
839 DBG(" ECX : 0x%x\n", reg[ecx]);
840 DBG(" EDX : 0x%x\n", reg[edx]);
841 }
842
843 if (info_p->cpuid_max_basic >= 0x15) {
844 /*
845 * TCS/CCC frequency leaf:
846 */
847 cpuid_fn(0x15, reg);
848 info_p->cpuid_tsc_leaf.denominator = reg[eax];
849 info_p->cpuid_tsc_leaf.numerator = reg[ebx];
850
851 DBG(" TSC/CCC Information Leaf:\n");
852 DBG(" numerator : 0x%x\n", reg[ebx]);
853 DBG(" denominator : 0x%x\n", reg[eax]);
854 }
855
856 return;
857 }
858
859 static uint32_t
cpuid_set_cpufamily(i386_cpu_info_t * info_p)860 cpuid_set_cpufamily(i386_cpu_info_t *info_p)
861 {
862 uint32_t cpufamily = CPUFAMILY_UNKNOWN;
863
864 switch (info_p->cpuid_family) {
865 case 6:
866 switch (info_p->cpuid_model) {
867 case 23:
868 cpufamily = CPUFAMILY_INTEL_PENRYN;
869 break;
870 case CPUID_MODEL_NEHALEM:
871 case CPUID_MODEL_FIELDS:
872 case CPUID_MODEL_DALES:
873 case CPUID_MODEL_NEHALEM_EX:
874 cpufamily = CPUFAMILY_INTEL_NEHALEM;
875 break;
876 case CPUID_MODEL_DALES_32NM:
877 case CPUID_MODEL_WESTMERE:
878 case CPUID_MODEL_WESTMERE_EX:
879 cpufamily = CPUFAMILY_INTEL_WESTMERE;
880 break;
881 case CPUID_MODEL_SANDYBRIDGE:
882 case CPUID_MODEL_JAKETOWN:
883 cpufamily = CPUFAMILY_INTEL_SANDYBRIDGE;
884 break;
885 case CPUID_MODEL_IVYBRIDGE:
886 case CPUID_MODEL_IVYBRIDGE_EP:
887 cpufamily = CPUFAMILY_INTEL_IVYBRIDGE;
888 break;
889 case CPUID_MODEL_HASWELL:
890 case CPUID_MODEL_HASWELL_EP:
891 case CPUID_MODEL_HASWELL_ULT:
892 case CPUID_MODEL_CRYSTALWELL:
893 cpufamily = CPUFAMILY_INTEL_HASWELL;
894 break;
895 case CPUID_MODEL_BROADWELL:
896 case CPUID_MODEL_BRYSTALWELL:
897 cpufamily = CPUFAMILY_INTEL_BROADWELL;
898 break;
899 case CPUID_MODEL_SKYLAKE:
900 case CPUID_MODEL_SKYLAKE_DT:
901 case CPUID_MODEL_SKYLAKE_W:
902 cpufamily = CPUFAMILY_INTEL_SKYLAKE;
903 break;
904 case CPUID_MODEL_KABYLAKE:
905 case CPUID_MODEL_KABYLAKE_DT:
906 cpufamily = CPUFAMILY_INTEL_KABYLAKE;
907 break;
908 case CPUID_MODEL_ICELAKE:
909 case CPUID_MODEL_ICELAKE_H:
910 case CPUID_MODEL_ICELAKE_DT:
911 cpufamily = CPUFAMILY_INTEL_ICELAKE;
912 break;
913 }
914 break;
915 }
916
917 info_p->cpuid_cpufamily = cpufamily;
918 DBG("cpuid_set_cpufamily(%p) returning 0x%x\n", info_p, cpufamily);
919 return cpufamily;
920 }
921 /*
922 * Must be invoked either when executing single threaded, or with
923 * independent synchronization.
924 */
925 void
cpuid_set_info(void)926 cpuid_set_info(void)
927 {
928 i386_cpu_info_t *info_p = &cpuid_cpu_info;
929 boolean_t enable_x86_64h = TRUE;
930
931 /* Perform pre-cpuid workarounds (since their effects impact values returned via cpuid) */
932 cpuid_do_precpuid_was();
933
934 cpuid_set_generic_info(info_p);
935
936 /* verify we are running on a supported CPU */
937 if ((strncmp(CPUID_VID_INTEL, info_p->cpuid_vendor,
938 min(strlen(CPUID_STRING_UNKNOWN) + 1,
939 sizeof(info_p->cpuid_vendor)))) ||
940 (cpuid_set_cpufamily(info_p) == CPUFAMILY_UNKNOWN)) {
941 panic("Unsupported CPU");
942 }
943
944 info_p->cpuid_cpu_type = CPU_TYPE_X86;
945
946 if (!PE_parse_boot_argn("-enable_x86_64h", &enable_x86_64h, sizeof(enable_x86_64h))) {
947 boolean_t disable_x86_64h = FALSE;
948
949 if (PE_parse_boot_argn("-disable_x86_64h", &disable_x86_64h, sizeof(disable_x86_64h))) {
950 enable_x86_64h = FALSE;
951 }
952 }
953
954 if (enable_x86_64h &&
955 ((info_p->cpuid_features & CPUID_X86_64_H_FEATURE_SUBSET) == CPUID_X86_64_H_FEATURE_SUBSET) &&
956 ((info_p->cpuid_extfeatures & CPUID_X86_64_H_EXTFEATURE_SUBSET) == CPUID_X86_64_H_EXTFEATURE_SUBSET) &&
957 ((info_p->cpuid_leaf7_features & CPUID_X86_64_H_LEAF7_FEATURE_SUBSET) == CPUID_X86_64_H_LEAF7_FEATURE_SUBSET)) {
958 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_64_H;
959 } else {
960 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
961 }
962 /* cpuid_set_cache_info must be invoked after set_generic_info */
963
964 /*
965 * Find the number of enabled cores and threads
966 * (which determines whether SMT/Hyperthreading is active).
967 */
968
969 /*
970 * Not all VMMs emulate MSR_CORE_THREAD_COUNT (0x35).
971 */
972 if (0 != (info_p->cpuid_features & CPUID_FEATURE_VMM) &&
973 PE_parse_boot_argn("-nomsr35h", NULL, 0)) {
974 info_p->core_count = 1;
975 info_p->thread_count = 1;
976 cpuid_set_cache_info(info_p);
977 } else {
978 switch (info_p->cpuid_cpufamily) {
979 case CPUFAMILY_INTEL_PENRYN:
980 cpuid_set_cache_info(info_p);
981 info_p->core_count = info_p->cpuid_cores_per_package;
982 info_p->thread_count = info_p->cpuid_logical_per_package;
983 break;
984 case CPUFAMILY_INTEL_WESTMERE: {
985 /*
986 * This should be the same as Nehalem but an A0 silicon bug returns
987 * invalid data in the top 12 bits. Hence, we use only bits [19..16]
988 * rather than [31..16] for core count - which actually can't exceed 8.
989 */
990 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
991 if (0 == msr) {
992 /* Provide a non-zero default for some VMMs */
993 msr = (1 << 16) | 1;
994 }
995 info_p->core_count = bitfield32((uint32_t)msr, 19, 16);
996 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0);
997 cpuid_set_cache_info(info_p);
998 break;
999 }
1000 default: {
1001 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
1002 if (0 == msr) {
1003 /* Provide a non-zero default for some VMMs */
1004 msr = (1 << 16) | 1;
1005 }
1006 info_p->core_count = bitfield32((uint32_t)msr, 31, 16);
1007 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0);
1008 cpuid_set_cache_info(info_p);
1009 break;
1010 }
1011 }
1012 }
1013
1014 DBG("cpuid_set_info():\n");
1015 DBG(" core_count : %d\n", info_p->core_count);
1016 DBG(" thread_count : %d\n", info_p->thread_count);
1017 DBG(" cpu_type: 0x%08x\n", info_p->cpuid_cpu_type);
1018 DBG(" cpu_subtype: 0x%08x\n", info_p->cpuid_cpu_subtype);
1019
1020 info_p->cpuid_model_string = ""; /* deprecated */
1021
1022 /* Init CPU LBRs */
1023 i386_lbr_init(info_p, true);
1024
1025 do_cwas(info_p, FALSE);
1026 }
1027
1028 static struct table {
1029 uint64_t mask;
1030 const char *name;
1031 } feature_map[] = {
1032 {CPUID_FEATURE_FPU, "FPU"},
1033 {CPUID_FEATURE_VME, "VME"},
1034 {CPUID_FEATURE_DE, "DE"},
1035 {CPUID_FEATURE_PSE, "PSE"},
1036 {CPUID_FEATURE_TSC, "TSC"},
1037 {CPUID_FEATURE_MSR, "MSR"},
1038 {CPUID_FEATURE_PAE, "PAE"},
1039 {CPUID_FEATURE_MCE, "MCE"},
1040 {CPUID_FEATURE_CX8, "CX8"},
1041 {CPUID_FEATURE_APIC, "APIC"},
1042 {CPUID_FEATURE_SEP, "SEP"},
1043 {CPUID_FEATURE_MTRR, "MTRR"},
1044 {CPUID_FEATURE_PGE, "PGE"},
1045 {CPUID_FEATURE_MCA, "MCA"},
1046 {CPUID_FEATURE_CMOV, "CMOV"},
1047 {CPUID_FEATURE_PAT, "PAT"},
1048 {CPUID_FEATURE_PSE36, "PSE36"},
1049 {CPUID_FEATURE_PSN, "PSN"},
1050 {CPUID_FEATURE_CLFSH, "CLFSH"},
1051 {CPUID_FEATURE_DS, "DS"},
1052 {CPUID_FEATURE_ACPI, "ACPI"},
1053 {CPUID_FEATURE_MMX, "MMX"},
1054 {CPUID_FEATURE_FXSR, "FXSR"},
1055 {CPUID_FEATURE_SSE, "SSE"},
1056 {CPUID_FEATURE_SSE2, "SSE2"},
1057 {CPUID_FEATURE_SS, "SS"},
1058 {CPUID_FEATURE_HTT, "HTT"},
1059 {CPUID_FEATURE_TM, "TM"},
1060 {CPUID_FEATURE_PBE, "PBE"},
1061 {CPUID_FEATURE_SSE3, "SSE3"},
1062 {CPUID_FEATURE_PCLMULQDQ, "PCLMULQDQ"},
1063 {CPUID_FEATURE_DTES64, "DTES64"},
1064 {CPUID_FEATURE_MONITOR, "MON"},
1065 {CPUID_FEATURE_DSCPL, "DSCPL"},
1066 {CPUID_FEATURE_VMX, "VMX"},
1067 {CPUID_FEATURE_SMX, "SMX"},
1068 {CPUID_FEATURE_EST, "EST"},
1069 {CPUID_FEATURE_TM2, "TM2"},
1070 {CPUID_FEATURE_SSSE3, "SSSE3"},
1071 {CPUID_FEATURE_CID, "CID"},
1072 {CPUID_FEATURE_FMA, "FMA"},
1073 {CPUID_FEATURE_CX16, "CX16"},
1074 {CPUID_FEATURE_xTPR, "TPR"},
1075 {CPUID_FEATURE_PDCM, "PDCM"},
1076 {CPUID_FEATURE_SSE4_1, "SSE4.1"},
1077 {CPUID_FEATURE_SSE4_2, "SSE4.2"},
1078 {CPUID_FEATURE_x2APIC, "x2APIC"},
1079 {CPUID_FEATURE_MOVBE, "MOVBE"},
1080 {CPUID_FEATURE_POPCNT, "POPCNT"},
1081 {CPUID_FEATURE_AES, "AES"},
1082 {CPUID_FEATURE_VMM, "VMM"},
1083 {CPUID_FEATURE_PCID, "PCID"},
1084 {CPUID_FEATURE_XSAVE, "XSAVE"},
1085 {CPUID_FEATURE_OSXSAVE, "OSXSAVE"},
1086 {CPUID_FEATURE_SEGLIM64, "SEGLIM64"},
1087 {CPUID_FEATURE_TSCTMR, "TSCTMR"},
1088 {CPUID_FEATURE_AVX1_0, "AVX1.0"},
1089 {CPUID_FEATURE_RDRAND, "RDRAND"},
1090 {CPUID_FEATURE_F16C, "F16C"},
1091 {0, 0}
1092 },
1093 extfeature_map[] = {
1094 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"},
1095 {CPUID_EXTFEATURE_XD, "XD"},
1096 {CPUID_EXTFEATURE_1GBPAGE, "1GBPAGE"},
1097 {CPUID_EXTFEATURE_EM64T, "EM64T"},
1098 {CPUID_EXTFEATURE_LAHF, "LAHF"},
1099 {CPUID_EXTFEATURE_LZCNT, "LZCNT"},
1100 {CPUID_EXTFEATURE_PREFETCHW, "PREFETCHW"},
1101 {CPUID_EXTFEATURE_RDTSCP, "RDTSCP"},
1102 {CPUID_EXTFEATURE_TSCI, "TSCI"},
1103 {0, 0}
1104 },
1105 leaf7_feature_map[] = {
1106 {CPUID_LEAF7_FEATURE_RDWRFSGS, "RDWRFSGS"},
1107 {CPUID_LEAF7_FEATURE_TSCOFF, "TSC_THREAD_OFFSET"},
1108 {CPUID_LEAF7_FEATURE_SGX, "SGX"},
1109 {CPUID_LEAF7_FEATURE_BMI1, "BMI1"},
1110 {CPUID_LEAF7_FEATURE_HLE, "HLE"},
1111 {CPUID_LEAF7_FEATURE_AVX2, "AVX2"},
1112 {CPUID_LEAF7_FEATURE_FDPEO, "FDPEO"},
1113 {CPUID_LEAF7_FEATURE_SMEP, "SMEP"},
1114 {CPUID_LEAF7_FEATURE_BMI2, "BMI2"},
1115 {CPUID_LEAF7_FEATURE_ERMS, "ERMS"},
1116 {CPUID_LEAF7_FEATURE_INVPCID, "INVPCID"},
1117 {CPUID_LEAF7_FEATURE_RTM, "RTM"},
1118 {CPUID_LEAF7_FEATURE_PQM, "PQM"},
1119 {CPUID_LEAF7_FEATURE_FPU_CSDS, "FPU_CSDS"},
1120 {CPUID_LEAF7_FEATURE_MPX, "MPX"},
1121 {CPUID_LEAF7_FEATURE_PQE, "PQE"},
1122 {CPUID_LEAF7_FEATURE_AVX512F, "AVX512F"},
1123 {CPUID_LEAF7_FEATURE_AVX512DQ, "AVX512DQ"},
1124 {CPUID_LEAF7_FEATURE_RDSEED, "RDSEED"},
1125 {CPUID_LEAF7_FEATURE_ADX, "ADX"},
1126 {CPUID_LEAF7_FEATURE_SMAP, "SMAP"},
1127 {CPUID_LEAF7_FEATURE_AVX512IFMA, "AVX512IFMA"},
1128 {CPUID_LEAF7_FEATURE_CLFSOPT, "CLFSOPT"},
1129 {CPUID_LEAF7_FEATURE_CLWB, "CLWB"},
1130 {CPUID_LEAF7_FEATURE_IPT, "IPT"},
1131 {CPUID_LEAF7_FEATURE_AVX512CD, "AVX512CD"},
1132 {CPUID_LEAF7_FEATURE_SHA, "SHA"},
1133 {CPUID_LEAF7_FEATURE_AVX512BW, "AVX512BW"},
1134 {CPUID_LEAF7_FEATURE_AVX512VL, "AVX512VL"},
1135 {CPUID_LEAF7_FEATURE_PREFETCHWT1, "PREFETCHWT1"},
1136 {CPUID_LEAF7_FEATURE_AVX512VBMI, "AVX512VBMI"},
1137 {CPUID_LEAF7_FEATURE_UMIP, "UMIP"},
1138 {CPUID_LEAF7_FEATURE_PKU, "PKU"},
1139 {CPUID_LEAF7_FEATURE_OSPKE, "OSPKE"},
1140 {CPUID_LEAF7_FEATURE_WAITPKG, "WAITPKG"},
1141 {CPUID_LEAF7_FEATURE_GFNI, "GFNI"},
1142 {CPUID_LEAF7_FEATURE_VAES, "VAES"},
1143 {CPUID_LEAF7_FEATURE_VPCLMULQDQ, "VPCLMULQDQ"},
1144 {CPUID_LEAF7_FEATURE_AVX512VNNI, "AVX512VNNI"},
1145 {CPUID_LEAF7_FEATURE_AVX512BITALG, "AVX512BITALG"},
1146 {CPUID_LEAF7_FEATURE_AVX512VPCDQ, "AVX512VPOPCNTDQ"},
1147 {CPUID_LEAF7_FEATURE_RDPID, "RDPID"},
1148 {CPUID_LEAF7_FEATURE_CLDEMOTE, "CLDEMOTE"},
1149 {CPUID_LEAF7_FEATURE_MOVDIRI, "MOVDIRI"},
1150 {CPUID_LEAF7_FEATURE_MOVDIRI64B, "MOVDIRI64B"},
1151 {CPUID_LEAF7_FEATURE_SGXLC, "SGXLC"},
1152 {0, 0}
1153 },
1154 leaf7_extfeature_map[] = {
1155 { CPUID_LEAF7_EXTFEATURE_AVX5124VNNIW, "AVX5124VNNIW" },
1156 { CPUID_LEAF7_EXTFEATURE_AVX5124FMAPS, "AVX5124FMAPS" },
1157 { CPUID_LEAF7_EXTFEATURE_FSREPMOV, "FSREPMOV" },
1158 { CPUID_LEAF7_EXTFEATURE_MDCLEAR, "MDCLEAR" },
1159 { CPUID_LEAF7_EXTFEATURE_TSXFA, "TSXFA" },
1160 { CPUID_LEAF7_EXTFEATURE_IBRS, "IBRS" },
1161 { CPUID_LEAF7_EXTFEATURE_STIBP, "STIBP" },
1162 { CPUID_LEAF7_EXTFEATURE_L1DF, "L1DF" },
1163 { CPUID_LEAF7_EXTFEATURE_ACAPMSR, "ACAPMSR" },
1164 { CPUID_LEAF7_EXTFEATURE_CCAPMSR, "CCAPMSR" },
1165 { CPUID_LEAF7_EXTFEATURE_SSBD, "SSBD" },
1166 {0, 0}
1167 };
1168
1169 static char *
cpuid_get_names(struct table * map,uint64_t bits,char * buf,unsigned buf_len)1170 cpuid_get_names(struct table *map, uint64_t bits, char *buf, unsigned buf_len)
1171 {
1172 size_t len = 0;
1173 char *p = buf;
1174 int i;
1175
1176 for (i = 0; map[i].mask != 0; i++) {
1177 if ((bits & map[i].mask) == 0) {
1178 continue;
1179 }
1180 if (len && ((size_t) (p - buf) < (buf_len - 1))) {
1181 *p++ = ' ';
1182 }
1183 len = min(strlen(map[i].name), (size_t)((buf_len - 1) - (p - buf)));
1184 if (len == 0) {
1185 break;
1186 }
1187 bcopy(map[i].name, p, len);
1188 p += len;
1189 }
1190 *p = '\0';
1191 return buf;
1192 }
1193
1194 i386_cpu_info_t *
cpuid_info(void)1195 cpuid_info(void)
1196 {
1197 /* Set-up the cpuid_info stucture lazily */
1198 if (cpuid_cpu_infop == NULL) {
1199 PE_parse_boot_argn("-cpuid", &cpuid_dbg, sizeof(cpuid_dbg));
1200 cpuid_set_info();
1201 cpuid_cpu_infop = &cpuid_cpu_info;
1202 }
1203 return cpuid_cpu_infop;
1204 }
1205
1206 char *
cpuid_get_feature_names(uint64_t features,char * buf,unsigned buf_len)1207 cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len)
1208 {
1209 return cpuid_get_names(feature_map, features, buf, buf_len);
1210 }
1211
1212 char *
cpuid_get_extfeature_names(uint64_t extfeatures,char * buf,unsigned buf_len)1213 cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len)
1214 {
1215 return cpuid_get_names(extfeature_map, extfeatures, buf, buf_len);
1216 }
1217
1218 char *
cpuid_get_leaf7_feature_names(uint64_t features,char * buf,unsigned buf_len)1219 cpuid_get_leaf7_feature_names(uint64_t features, char *buf, unsigned buf_len)
1220 {
1221 return cpuid_get_names(leaf7_feature_map, features, buf, buf_len);
1222 }
1223
1224 char *
cpuid_get_leaf7_extfeature_names(uint64_t features,char * buf,unsigned buf_len)1225 cpuid_get_leaf7_extfeature_names(uint64_t features, char *buf, unsigned buf_len)
1226 {
1227 return cpuid_get_names(leaf7_extfeature_map, features, buf, buf_len);
1228 }
1229
1230 void
cpuid_feature_display(const char * header)1231 cpuid_feature_display(
1232 const char *header)
1233 {
1234 char buf[320];
1235
1236 kprintf("%s: %s", header,
1237 cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf)));
1238 if (cpuid_leaf7_features()) {
1239 kprintf(" %s", cpuid_get_leaf7_feature_names(
1240 cpuid_leaf7_features(), buf, sizeof(buf)));
1241 }
1242 if (cpuid_leaf7_extfeatures()) {
1243 kprintf(" %s", cpuid_get_leaf7_extfeature_names(
1244 cpuid_leaf7_extfeatures(), buf, sizeof(buf)));
1245 }
1246 kprintf("\n");
1247 if (cpuid_features() & CPUID_FEATURE_HTT) {
1248 #define s_if_plural(n) ((n > 1) ? "s" : "")
1249 kprintf(" HTT: %d core%s per package;"
1250 " %d logical cpu%s per package\n",
1251 cpuid_cpu_infop->cpuid_cores_per_package,
1252 s_if_plural(cpuid_cpu_infop->cpuid_cores_per_package),
1253 cpuid_cpu_infop->cpuid_logical_per_package,
1254 s_if_plural(cpuid_cpu_infop->cpuid_logical_per_package));
1255 }
1256 }
1257
1258 void
cpuid_extfeature_display(const char * header)1259 cpuid_extfeature_display(
1260 const char *header)
1261 {
1262 char buf[256];
1263
1264 kprintf("%s: %s\n", header,
1265 cpuid_get_extfeature_names(cpuid_extfeatures(),
1266 buf, sizeof(buf)));
1267 }
1268
1269 void
cpuid_cpu_display(const char * header)1270 cpuid_cpu_display(
1271 const char *header)
1272 {
1273 if (cpuid_cpu_infop->cpuid_brand_string[0] != '\0') {
1274 kprintf("%s: %s\n", header, cpuid_cpu_infop->cpuid_brand_string);
1275 }
1276 }
1277
1278 unsigned int
cpuid_family(void)1279 cpuid_family(void)
1280 {
1281 return cpuid_info()->cpuid_family;
1282 }
1283
1284 uint32_t
cpuid_cpufamily(void)1285 cpuid_cpufamily(void)
1286 {
1287 return cpuid_info()->cpuid_cpufamily;
1288 }
1289
1290 cpu_type_t
cpuid_cputype(void)1291 cpuid_cputype(void)
1292 {
1293 return cpuid_info()->cpuid_cpu_type;
1294 }
1295
1296 cpu_subtype_t
cpuid_cpusubtype(void)1297 cpuid_cpusubtype(void)
1298 {
1299 return cpuid_info()->cpuid_cpu_subtype;
1300 }
1301
1302 uint64_t
cpuid_features(void)1303 cpuid_features(void)
1304 {
1305 static int checked = 0;
1306 char fpu_arg[20] = { 0 };
1307
1308 (void) cpuid_info();
1309 if (!checked) {
1310 /* check for boot-time fpu limitations */
1311 if (PE_parse_boot_argn("_fpu", &fpu_arg[0], sizeof(fpu_arg))) {
1312 printf("limiting fpu features to: %s\n", fpu_arg);
1313 if (!strncmp("387", fpu_arg, sizeof("387")) || !strncmp("mmx", fpu_arg, sizeof("mmx"))) {
1314 printf("no sse or sse2\n");
1315 cpuid_cpu_infop->cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
1316 } else if (!strncmp("sse", fpu_arg, sizeof("sse"))) {
1317 printf("no sse2\n");
1318 cpuid_cpu_infop->cpuid_features &= ~(CPUID_FEATURE_SSE2);
1319 }
1320 }
1321 checked = 1;
1322 }
1323 return cpuid_cpu_infop->cpuid_features;
1324 }
1325
1326 uint64_t
cpuid_extfeatures(void)1327 cpuid_extfeatures(void)
1328 {
1329 return cpuid_info()->cpuid_extfeatures;
1330 }
1331
1332 uint64_t
cpuid_leaf7_features(void)1333 cpuid_leaf7_features(void)
1334 {
1335 return cpuid_info()->cpuid_leaf7_features;
1336 }
1337
1338 uint64_t
cpuid_leaf7_extfeatures(void)1339 cpuid_leaf7_extfeatures(void)
1340 {
1341 return cpuid_info()->cpuid_leaf7_extfeatures;
1342 }
1343
1344 const char *
cpuid_vmm_family_string(void)1345 cpuid_vmm_family_string(void)
1346 {
1347 switch (cpuid_vmm_info()->cpuid_vmm_family) {
1348 case CPUID_VMM_FAMILY_NONE:
1349 return "None";
1350
1351 case CPUID_VMM_FAMILY_VMWARE:
1352 return "VMWare";
1353
1354 case CPUID_VMM_FAMILY_PARALLELS:
1355 return "Parallels";
1356
1357 case CPUID_VMM_FAMILY_HYVE:
1358 return "xHyve";
1359
1360 case CPUID_VMM_FAMILY_HVF:
1361 return "HVF";
1362
1363 case CPUID_VMM_FAMILY_KVM:
1364 return "KVM";
1365
1366 case CPUID_VMM_FAMILY_UNKNOWN:
1367 /*FALLTHROUGH*/
1368 default:
1369 return "Unknown VMM";
1370 }
1371 }
1372
1373 static i386_vmm_info_t *_cpuid_vmm_infop = NULL;
1374 static i386_vmm_info_t _cpuid_vmm_info;
1375
1376 static void
cpuid_init_vmm_info(i386_vmm_info_t * info_p)1377 cpuid_init_vmm_info(i386_vmm_info_t *info_p)
1378 {
1379 uint32_t reg[4], maxbasic_regs[4];
1380 uint32_t max_vmm_leaf;
1381
1382 bzero(info_p, sizeof(*info_p));
1383
1384 if (!cpuid_vmm_present()) {
1385 return;
1386 }
1387
1388 DBG("cpuid_init_vmm_info(%p)\n", info_p);
1389
1390 /*
1391 * Get the highest basic leaf value, then save the cpuid details for that leaf
1392 * for comparison with the [ostensible] VMM leaf.
1393 */
1394 cpuid_fn(0, reg);
1395 cpuid_fn(reg[eax], maxbasic_regs);
1396
1397 /* do cpuid 0x40000000 to get VMM vendor */
1398 cpuid_fn(0x40000000, reg);
1399
1400 /*
1401 * If leaf 0x40000000 is non-existent, cpuid will return the values as
1402 * if the highest basic leaf was requested, so compare to those values
1403 * we just retrieved to see if no vmm is present.
1404 */
1405 if (bcmp(reg, maxbasic_regs, sizeof(reg)) == 0) {
1406 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_NONE;
1407 DBG(" vmm_vendor : NONE\n");
1408 return;
1409 }
1410
1411 max_vmm_leaf = reg[eax];
1412 bcopy((char *)®[ebx], &info_p->cpuid_vmm_vendor[0], 4);
1413 bcopy((char *)®[ecx], &info_p->cpuid_vmm_vendor[4], 4);
1414 bcopy((char *)®[edx], &info_p->cpuid_vmm_vendor[8], 4);
1415 info_p->cpuid_vmm_vendor[12] = '\0';
1416
1417 if (0 == strcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_VMWARE)) {
1418 /* VMware identification string: kb.vmware.com/kb/1009458 */
1419 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_VMWARE;
1420 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_PARALLELS, 12)) {
1421 /* Parallels identification string */
1422 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_PARALLELS;
1423 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_HYVE, 12)) {
1424 /* bhyve/xhyve identification string */
1425 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_HYVE;
1426 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_HVF, 12)) {
1427 /* HVF identification string */
1428 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_HVF;
1429 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_KVM, 12)) {
1430 /* KVM identification string */
1431 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_KVM;
1432 } else {
1433 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_UNKNOWN;
1434 }
1435
1436 /* VMM generic leaves: https://lkml.org/lkml/2008/10/1/246 */
1437 if (max_vmm_leaf >= 0x40000010) {
1438 cpuid_fn(0x40000010, reg);
1439
1440 info_p->cpuid_vmm_tsc_frequency = reg[eax];
1441 info_p->cpuid_vmm_bus_frequency = reg[ebx];
1442 }
1443
1444 cpuid_vmm_detect_pv_interface(info_p, APPLEPV_SIGNATURE, &cpuid_vmm_detect_applepv_features);
1445
1446 DBG(" vmm_vendor : %s\n", info_p->cpuid_vmm_vendor);
1447 DBG(" vmm_family : %u\n", info_p->cpuid_vmm_family);
1448 DBG(" vmm_bus_frequency : %u\n", info_p->cpuid_vmm_bus_frequency);
1449 DBG(" vmm_tsc_frequency : %u\n", info_p->cpuid_vmm_tsc_frequency);
1450 }
1451
1452 boolean_t
cpuid_vmm_present(void)1453 cpuid_vmm_present(void)
1454 {
1455 return (cpuid_features() & CPUID_FEATURE_VMM) ? TRUE : FALSE;
1456 }
1457
1458 i386_vmm_info_t *
cpuid_vmm_info(void)1459 cpuid_vmm_info(void)
1460 {
1461 if (_cpuid_vmm_infop == NULL) {
1462 cpuid_init_vmm_info(&_cpuid_vmm_info);
1463 _cpuid_vmm_infop = &_cpuid_vmm_info;
1464 }
1465 return _cpuid_vmm_infop;
1466 }
1467
1468 uint32_t
cpuid_vmm_family(void)1469 cpuid_vmm_family(void)
1470 {
1471 return cpuid_vmm_info()->cpuid_vmm_family;
1472 }
1473
1474 uint64_t
cpuid_vmm_get_applepv_features(void)1475 cpuid_vmm_get_applepv_features(void)
1476 {
1477 return cpuid_vmm_info()->cpuid_vmm_applepv_features;
1478 }
1479
1480 cwa_classifier_e
cpuid_wa_required(cpu_wa_e wa)1481 cpuid_wa_required(cpu_wa_e wa)
1482 {
1483 i386_cpu_info_t *info_p = &cpuid_cpu_info;
1484 static uint64_t bootarg_cpu_wa_enables = 0;
1485 static uint64_t bootarg_cpu_wa_disables = 0;
1486 static int bootargs_overrides_processed = 0;
1487 uint32_t reg[4];
1488
1489 if (!bootargs_overrides_processed) {
1490 if (!PE_parse_boot_argn("cwae", &bootarg_cpu_wa_enables, sizeof(bootarg_cpu_wa_enables))) {
1491 bootarg_cpu_wa_enables = 0;
1492 }
1493
1494 if (!PE_parse_boot_argn("cwad", &bootarg_cpu_wa_disables, sizeof(bootarg_cpu_wa_disables))) {
1495 bootarg_cpu_wa_disables = 0;
1496 }
1497 bootargs_overrides_processed = 1;
1498 }
1499
1500 if (bootarg_cpu_wa_enables & (1 << wa)) {
1501 return CWA_FORCE_ON;
1502 }
1503
1504 if (bootarg_cpu_wa_disables & (1 << wa)) {
1505 return CWA_FORCE_OFF;
1506 }
1507
1508 switch (wa) {
1509 case CPU_INTEL_SEGCHK:
1510 /* First, check to see if this CPU requires the workaround */
1511 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_ACAPMSR) != 0) {
1512 /* We have ARCHCAP, so check it for either RDCL_NO or MDS_NO */
1513 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES);
1514 if ((archcap_msr & (MSR_IA32_ARCH_CAPABILITIES_RDCL_NO | MSR_IA32_ARCH_CAPABILITIES_MDS_NO)) != 0) {
1515 /* Workaround not needed */
1516 return CWA_OFF;
1517 }
1518 }
1519
1520 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_MDCLEAR) != 0) {
1521 return CWA_ON;
1522 }
1523
1524 /*
1525 * If the CPU supports the ARCHCAP MSR and neither the RDCL_NO bit nor the MDS_NO
1526 * bit are set, OR the CPU does not support the ARCHCAP MSR and the CPU does
1527 * not enumerate the presence of the enhanced VERW instruction, report
1528 * that the workaround should not be enabled.
1529 */
1530 break;
1531
1532 case CPU_INTEL_TSXFA:
1533 /*
1534 * Note that if TSX was disabled in cpuid_do_precpuid_was(), the cached cpuid
1535 * info will indicate that RTM is *not* supported and this workaround will not
1536 * be enabled.
1537 */
1538 /*
1539 * Otherwise, if the CPU supports both TSX(HLE) and FORCE_ABORT, return that
1540 * the workaround should be enabled.
1541 */
1542 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_TSXFA) != 0 &&
1543 (info_p->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_RTM) != 0) {
1544 return CWA_ON;
1545 }
1546 break;
1547
1548 case CPU_INTEL_TSXDA:
1549 /*
1550 * Since this workaround might be requested before cpuid_set_info() is complete,
1551 * we need to invoke cpuid directly when looking for the required bits.
1552 */
1553 cpuid_fn(0x7, reg);
1554 if (reg[edx] & CPUID_LEAF7_EXTFEATURE_ACAPMSR) {
1555 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES);
1556 /*
1557 * If this CPU supports TSX (HLE being the proxy for TSX detection) AND it does
1558 * not include a hardware fix for TAA and it supports the TSX_CTRL MSR, disable TSX entirely.
1559 * (Note this can be overridden (above) if the cwad boot-arg's value has bit 2 set.)
1560 */
1561 if ((reg[ebx] & CPUID_LEAF7_FEATURE_HLE) != 0 &&
1562 (archcap_msr & (MSR_IA32_ARCH_CAPABILITIES_TAA_NO | MSR_IA32_ARCH_CAPABILITIES_TSX_CTRL))
1563 == MSR_IA32_ARCH_CAPABILITIES_TSX_CTRL) {
1564 return CWA_ON;
1565 }
1566 }
1567 break;
1568
1569 case CPU_INTEL_SRBDS:
1570 /*
1571 * SRBDS mitigations are enabled by default. CWA_ON returned here indicates
1572 * the caller should disable the mitigation. Mitigations should be disabled
1573 * at least for CPUs that advertise MDS_NO *and* (either TAA_NO is set OR TSX
1574 * has been disabled).
1575 */
1576 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_SRBDS_CTRL) != 0) {
1577 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_ACAPMSR) != 0) {
1578 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES);
1579 if ((archcap_msr & MSR_IA32_ARCH_CAPABILITIES_MDS_NO) != 0 &&
1580 ((archcap_msr & MSR_IA32_ARCH_CAPABILITIES_TAA_NO) != 0 ||
1581 cpuid_tsx_disabled)) {
1582 return CWA_ON;
1583 }
1584 }
1585 }
1586 break;
1587
1588 case CPU_INTEL_RSBST:
1589 /*
1590 * RSB-stuffing in the kernel exit trampolines (when returning to user)
1591 * RSB depth is 32. This workaround must be explicitly enabled via the
1592 * cwae boot-arg.
1593 */
1594 break;
1595
1596 default:
1597 break;
1598 }
1599
1600 return CWA_OFF;
1601 }
1602
1603 static void
cpuid_do_precpuid_was(void)1604 cpuid_do_precpuid_was(void)
1605 {
1606 /*
1607 * Note that care must be taken not to use any data from the cached cpuid data since it is
1608 * likely uninitialized at this point. That includes calling functions that make use of
1609 * that data as well.
1610 */
1611
1612 /* Note the TSX disablement, we do not support force-on since it depends on MSRs being present */
1613 if (cpuid_wa_required(CPU_INTEL_TSXDA) == CWA_ON) {
1614 /* This must be executed on all logical processors */
1615 wrmsr64(MSR_IA32_TSX_CTRL, MSR_IA32_TSXCTRL_TSX_CPU_CLEAR | MSR_IA32_TSXCTRL_RTM_DISABLE);
1616 cpuid_tsx_disabled = true;
1617 }
1618 }
1619
1620
1621 /*
1622 * Hunt for Apple Paravirtualization support in the hypervisor class leaves [0x4000_0000-0x4001_0000].
1623 * Hypervisor interfaces are expected to be found at 0x100 boundaries for compatibility.
1624 */
1625
1626 static bool
cpuid_vmm_detect_applepv_features(i386_vmm_info_t * info_p,const uint32_t base,const uint32_t max_leaf)1627 cpuid_vmm_detect_applepv_features(i386_vmm_info_t *info_p, const uint32_t base, const uint32_t max_leaf)
1628 {
1629 if ((max_leaf - base) < APPLEPV_LEAF_INDEX_MAX) {
1630 return false;
1631 }
1632
1633 /*
1634 * Issue cpuid to make sure the interface supports "AH#1" features.
1635 * This avoids a possible collision with "Hv#1" used by Hyper-V.
1636 */
1637 uint32_t reg[4];
1638 char interface[5];
1639 cpuid_fn(base + APPLEPV_INTERFACE_LEAF_INDEX, reg);
1640 memcpy(&interface[0], ®[eax], 4);
1641 interface[4] = '\0';
1642 if (0 == strcmp(interface, APPLEPV_INTERFACE)) {
1643 cpuid_fn(base + APPLEPV_FEATURES_LEAF_INDEX, reg);
1644 info_p->cpuid_vmm_applepv_features = quad(reg[ecx], reg[edx]);
1645 return true;
1646 }
1647 return false;
1648 }
1649
1650 static void
cpuid_vmm_detect_pv_interface(i386_vmm_info_t * info_p,const char * signature,bool (* searcher)(i386_vmm_info_t *,const uint32_t,const uint32_t))1651 cpuid_vmm_detect_pv_interface(i386_vmm_info_t *info_p, const char *signature,
1652 bool (*searcher)(i386_vmm_info_t*, const uint32_t, const uint32_t))
1653 {
1654 int hcalls;
1655 if (PE_parse_boot_argn("hcalls", &hcalls, sizeof(hcalls)) &&
1656 hcalls == 0) {
1657 return;
1658 }
1659
1660 assert(info_p);
1661 /*
1662 * Look for PV interface matching signature
1663 */
1664 for (uint32_t base = 0x40000100; base < 0x40010000; base += 0x100) {
1665 uint32_t reg[4];
1666 char vendor[13];
1667
1668 cpuid_fn(base, reg);
1669 memcpy(&vendor[0], ®[ebx], 4);
1670 memcpy(&vendor[4], ®[ecx], 4);
1671 memcpy(&vendor[8], ®[edx], 4);
1672 vendor[12] = '\0';
1673 if ((0 == strcmp(vendor, signature)) &&
1674 (reg[eax] - base) < 0x100 &&
1675 (*searcher)(info_p, base, reg[eax])) {
1676 break;
1677 }
1678 }
1679 }
1680