1 /*
2 * Copyright (c) 2000-2020 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 #include <vm/vm_page.h>
32 #include <pexpert/pexpert.h>
33
34 #include <i386/cpu_threads.h>
35 #include <i386/cpuid.h>
36 #include <i386/machine_routines.h>
37
38 int force_tecs_at_idle;
39 int tecs_mode_supported;
40
41 static boolean_t cpuid_dbg
42 #if DEBUG
43 = TRUE;
44 #else
45 = FALSE;
46 #endif
47 #define DBG(x...) \
48 do { \
49 if (cpuid_dbg) \
50 kprintf(x); \
51 } while (0) \
52
53 #define min(a, b) ((a) < (b) ? (a) : (b))
54 #define quad(hi, lo) (((uint64_t)(hi)) << 32 | (lo))
55
56 /*
57 * Leaf 2 cache descriptor encodings.
58 */
59 typedef enum {
60 _NULL_, /* NULL (empty) descriptor */
61 CACHE, /* Cache */
62 TLB, /* TLB */
63 STLB, /* Shared second-level unified TLB */
64 PREFETCH /* Prefetch size */
65 } cpuid_leaf2_desc_type_t;
66
67 typedef enum {
68 NA, /* Not Applicable */
69 FULLY, /* Fully-associative */
70 TRACE, /* Trace Cache (P4 only) */
71 INST, /* Instruction TLB */
72 DATA, /* Data TLB */
73 DATA0, /* Data TLB, 1st level */
74 DATA1, /* Data TLB, 2nd level */
75 L1, /* L1 (unified) cache */
76 L1_INST, /* L1 Instruction cache */
77 L1_DATA, /* L1 Data cache */
78 L2, /* L2 (unified) cache */
79 L3, /* L3 (unified) cache */
80 L2_2LINESECTOR, /* L2 (unified) cache with 2 lines per sector */
81 L3_2LINESECTOR, /* L3(unified) cache with 2 lines per sector */
82 SMALL, /* Small page TLB */
83 LARGE, /* Large page TLB */
84 BOTH /* Small and Large page TLB */
85 } cpuid_leaf2_qualifier_t;
86
87 typedef struct cpuid_cache_descriptor {
88 uint8_t value; /* descriptor code */
89 uint8_t type; /* cpuid_leaf2_desc_type_t */
90 uint8_t level; /* level of cache/TLB hierachy */
91 uint8_t ways; /* wayness of cache */
92 uint16_t size; /* cachesize or TLB pagesize */
93 uint16_t entries; /* number of TLB entries or linesize */
94 } cpuid_cache_descriptor_t;
95
96 /*
97 * These multipliers are used to encode 1*K .. 64*M in a 16 bit size field
98 */
99 #define K (1)
100 #define M (1024)
101
102 /*
103 * Intel cache descriptor table:
104 */
105 static const cpuid_cache_descriptor_t intel_cpuid_leaf2_descriptor_table[] = {
106 // -------------------------------------------------------
107 // value type level ways size entries
108 // -------------------------------------------------------
109 { 0x00, _NULL_, NA, NA, NA, NA },
110 { 0x01, TLB, INST, 4, SMALL, 32 },
111 { 0x02, TLB, INST, FULLY, LARGE, 2 },
112 { 0x03, TLB, DATA, 4, SMALL, 64 },
113 { 0x04, TLB, DATA, 4, LARGE, 8 },
114 { 0x05, TLB, DATA1, 4, LARGE, 32 },
115 { 0x06, CACHE, L1_INST, 4, 8 * K, 32 },
116 { 0x08, CACHE, L1_INST, 4, 16 * K, 32 },
117 { 0x09, CACHE, L1_INST, 4, 32 * K, 64 },
118 { 0x0A, CACHE, L1_DATA, 2, 8 * K, 32 },
119 { 0x0B, TLB, INST, 4, LARGE, 4 },
120 { 0x0C, CACHE, L1_DATA, 4, 16 * K, 32 },
121 { 0x0D, CACHE, L1_DATA, 4, 16 * K, 64 },
122 { 0x0E, CACHE, L1_DATA, 6, 24 * K, 64 },
123 { 0x21, CACHE, L2, 8, 256 * K, 64 },
124 { 0x22, CACHE, L3_2LINESECTOR, 4, 512 * K, 64 },
125 { 0x23, CACHE, L3_2LINESECTOR, 8, 1 * M, 64 },
126 { 0x25, CACHE, L3_2LINESECTOR, 8, 2 * M, 64 },
127 { 0x29, CACHE, L3_2LINESECTOR, 8, 4 * M, 64 },
128 { 0x2C, CACHE, L1_DATA, 8, 32 * K, 64 },
129 { 0x30, CACHE, L1_INST, 8, 32 * K, 64 },
130 { 0x40, CACHE, L2, NA, 0, NA },
131 { 0x41, CACHE, L2, 4, 128 * K, 32 },
132 { 0x42, CACHE, L2, 4, 256 * K, 32 },
133 { 0x43, CACHE, L2, 4, 512 * K, 32 },
134 { 0x44, CACHE, L2, 4, 1 * M, 32 },
135 { 0x45, CACHE, L2, 4, 2 * M, 32 },
136 { 0x46, CACHE, L3, 4, 4 * M, 64 },
137 { 0x47, CACHE, L3, 8, 8 * M, 64 },
138 { 0x48, CACHE, L2, 12, 3 * M, 64 },
139 { 0x49, CACHE, L2, 16, 4 * M, 64 },
140 { 0x4A, CACHE, L3, 12, 6 * M, 64 },
141 { 0x4B, CACHE, L3, 16, 8 * M, 64 },
142 { 0x4C, CACHE, L3, 12, 12 * M, 64 },
143 { 0x4D, CACHE, L3, 16, 16 * M, 64 },
144 { 0x4E, CACHE, L2, 24, 6 * M, 64 },
145 { 0x4F, TLB, INST, NA, SMALL, 32 },
146 { 0x50, TLB, INST, NA, BOTH, 64 },
147 { 0x51, TLB, INST, NA, BOTH, 128 },
148 { 0x52, TLB, INST, NA, BOTH, 256 },
149 { 0x55, TLB, INST, FULLY, BOTH, 7 },
150 { 0x56, TLB, DATA0, 4, LARGE, 16 },
151 { 0x57, TLB, DATA0, 4, SMALL, 16 },
152 { 0x59, TLB, DATA0, FULLY, SMALL, 16 },
153 { 0x5A, TLB, DATA0, 4, LARGE, 32 },
154 { 0x5B, TLB, DATA, NA, BOTH, 64 },
155 { 0x5C, TLB, DATA, NA, BOTH, 128 },
156 { 0x5D, TLB, DATA, NA, BOTH, 256 },
157 { 0x60, CACHE, L1, 16 * K, 8, 64 },
158 { 0x61, CACHE, L1, 4, 8 * K, 64 },
159 { 0x62, CACHE, L1, 4, 16 * K, 64 },
160 { 0x63, CACHE, L1, 4, 32 * K, 64 },
161 { 0x70, CACHE, TRACE, 8, 12 * K, NA },
162 { 0x71, CACHE, TRACE, 8, 16 * K, NA },
163 { 0x72, CACHE, TRACE, 8, 32 * K, NA },
164 { 0x76, TLB, INST, NA, BOTH, 8 },
165 { 0x78, CACHE, L2, 4, 1 * M, 64 },
166 { 0x79, CACHE, L2_2LINESECTOR, 8, 128 * K, 64 },
167 { 0x7A, CACHE, L2_2LINESECTOR, 8, 256 * K, 64 },
168 { 0x7B, CACHE, L2_2LINESECTOR, 8, 512 * K, 64 },
169 { 0x7C, CACHE, L2_2LINESECTOR, 8, 1 * M, 64 },
170 { 0x7D, CACHE, L2, 8, 2 * M, 64 },
171 { 0x7F, CACHE, L2, 2, 512 * K, 64 },
172 { 0x80, CACHE, L2, 8, 512 * K, 64 },
173 { 0x82, CACHE, L2, 8, 256 * K, 32 },
174 { 0x83, CACHE, L2, 8, 512 * K, 32 },
175 { 0x84, CACHE, L2, 8, 1 * M, 32 },
176 { 0x85, CACHE, L2, 8, 2 * M, 32 },
177 { 0x86, CACHE, L2, 4, 512 * K, 64 },
178 { 0x87, CACHE, L2, 8, 1 * M, 64 },
179 { 0xB0, TLB, INST, 4, SMALL, 128 },
180 { 0xB1, TLB, INST, 4, LARGE, 8 },
181 { 0xB2, TLB, INST, 4, SMALL, 64 },
182 { 0xB3, TLB, DATA, 4, SMALL, 128 },
183 { 0xB4, TLB, DATA1, 4, SMALL, 256 },
184 { 0xB5, TLB, DATA1, 8, SMALL, 64 },
185 { 0xB6, TLB, DATA1, 8, SMALL, 128 },
186 { 0xBA, TLB, DATA1, 4, BOTH, 64 },
187 { 0xC1, STLB, DATA1, 8, SMALL, 1024},
188 { 0xCA, STLB, DATA1, 4, SMALL, 512 },
189 { 0xD0, CACHE, L3, 4, 512 * K, 64 },
190 { 0xD1, CACHE, L3, 4, 1 * M, 64 },
191 { 0xD2, CACHE, L3, 4, 2 * M, 64 },
192 { 0xD3, CACHE, L3, 4, 4 * M, 64 },
193 { 0xD4, CACHE, L3, 4, 8 * M, 64 },
194 { 0xD6, CACHE, L3, 8, 1 * M, 64 },
195 { 0xD7, CACHE, L3, 8, 2 * M, 64 },
196 { 0xD8, CACHE, L3, 8, 4 * M, 64 },
197 { 0xD9, CACHE, L3, 8, 8 * M, 64 },
198 { 0xDA, CACHE, L3, 8, 12 * M, 64 },
199 { 0xDC, CACHE, L3, 12, 1536 * K, 64 },
200 { 0xDD, CACHE, L3, 12, 3 * M, 64 },
201 { 0xDE, CACHE, L3, 12, 6 * M, 64 },
202 { 0xDF, CACHE, L3, 12, 12 * M, 64 },
203 { 0xE0, CACHE, L3, 12, 18 * M, 64 },
204 { 0xE2, CACHE, L3, 16, 2 * M, 64 },
205 { 0xE3, CACHE, L3, 16, 4 * M, 64 },
206 { 0xE4, CACHE, L3, 16, 8 * M, 64 },
207 { 0xE5, CACHE, L3, 16, 16 * M, 64 },
208 { 0xE6, CACHE, L3, 16, 24 * M, 64 },
209 { 0xF0, PREFETCH, NA, NA, 64, NA },
210 { 0xF1, PREFETCH, NA, NA, 128, NA },
211 { 0xFF, CACHE, NA, NA, 0, NA }
212 };
213 #define INTEL_LEAF2_DESC_NUM (sizeof(intel_cpuid_leaf2_descriptor_table) / \
214 sizeof(cpuid_cache_descriptor_t))
215
216 boolean_t cpuid_tsx_disabled = false; /* true if XNU disabled TSX */
217 boolean_t cpuid_tsx_supported = false;
218
219 static void do_cwas(i386_cpu_info_t *cpuinfo, boolean_t on_slave);
220 static void cpuid_do_precpuid_was(void);
221
222 static void cpuid_vmm_detect_pv_interface(i386_vmm_info_t *info_p, const char *signature,
223 bool (*)(i386_vmm_info_t*, const uint32_t, const uint32_t));
224 static bool cpuid_vmm_detect_applepv_features(i386_vmm_info_t *info_p, const uint32_t base, const uint32_t max_leaf);
225
226 static inline const cpuid_cache_descriptor_t *
cpuid_leaf2_find(uint8_t value)227 cpuid_leaf2_find(uint8_t value)
228 {
229 unsigned int i;
230
231 for (i = 0; i < INTEL_LEAF2_DESC_NUM; i++) {
232 if (intel_cpuid_leaf2_descriptor_table[i].value == value) {
233 return &intel_cpuid_leaf2_descriptor_table[i];
234 }
235 }
236 return NULL;
237 }
238
239 /*
240 * CPU identification routines.
241 */
242
243 static i386_cpu_info_t cpuid_cpu_info;
244 static i386_cpu_info_t *cpuid_cpu_infop = NULL;
245
246 static void
cpuid_fn(uint32_t selector,uint32_t * result)247 cpuid_fn(uint32_t selector, uint32_t *result)
248 {
249 do_cpuid(selector, result);
250 DBG("cpuid_fn(0x%08x) eax:0x%08x ebx:0x%08x ecx:0x%08x edx:0x%08x\n",
251 selector, result[0], result[1], result[2], result[3]);
252 }
253
254 static const char *cache_type_str[LCACHE_MAX] = {
255 "Lnone", "L1I", "L1D", "L2U", "L3U"
256 };
257
258 static void
do_cwas(i386_cpu_info_t * cpuinfo,boolean_t on_slave)259 do_cwas(i386_cpu_info_t *cpuinfo, boolean_t on_slave)
260 {
261 extern int force_thread_policy_tecs;
262 cwa_classifier_e wa_reqd;
263
264 /*
265 * Workaround for reclaiming perf counter 3 due to TSX memory ordering erratum.
266 * This workaround does not support being forcibly set (since an MSR must be
267 * enumerated, lest we #GP when forced to access it.)
268 *
269 * Note that if disabling TSX is supported, disablement is prefered over forcing
270 * TSX transactions to abort.
271 */
272 if (cpuid_wa_required(CPU_INTEL_TSXDA) == CWA_ON) {
273 /* This must be executed on all logical processors */
274 wrmsr64(MSR_IA32_TSX_CTRL, MSR_IA32_TSXCTRL_TSX_CPU_CLEAR | MSR_IA32_TSXCTRL_RTM_DISABLE);
275 } else if (cpuid_wa_required(CPU_INTEL_TSXFA) == CWA_ON) {
276 /* This must be executed on all logical processors */
277 wrmsr64(MSR_IA32_TSX_FORCE_ABORT,
278 rdmsr64(MSR_IA32_TSX_FORCE_ABORT) | MSR_IA32_TSXFA_RTM_FORCE_ABORT);
279 }
280
281 if (((wa_reqd = cpuid_wa_required(CPU_INTEL_SRBDS)) & CWA_ON) != 0 &&
282 ((wa_reqd & CWA_FORCE_ON) == CWA_ON ||
283 (cpuinfo->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_SRBDS_CTRL) != 0)) {
284 /* This must be executed on all logical processors */
285 uint64_t mcuoptctrl = rdmsr64(MSR_IA32_MCU_OPT_CTRL);
286 mcuoptctrl |= MSR_IA32_MCUOPTCTRL_RNGDS_MITG_DIS;
287 wrmsr64(MSR_IA32_MCU_OPT_CTRL, mcuoptctrl);
288 }
289
290 if (on_slave) {
291 return;
292 }
293
294 switch (cpuid_wa_required(CPU_INTEL_SEGCHK)) {
295 case CWA_FORCE_ON:
296 force_thread_policy_tecs = 1;
297
298 /* If hyperthreaded, enable idle workaround */
299 if (cpuinfo->thread_count > cpuinfo->core_count) {
300 force_tecs_at_idle = 1;
301 }
302
303 OS_FALLTHROUGH;
304 case CWA_ON:
305 tecs_mode_supported = 1;
306 break;
307
308 case CWA_FORCE_OFF:
309 case CWA_OFF:
310 tecs_mode_supported = 0;
311 force_tecs_at_idle = 0;
312 force_thread_policy_tecs = 0;
313 break;
314
315 default:
316 break;
317 }
318 }
319
320 void
cpuid_do_was(void)321 cpuid_do_was(void)
322 {
323 do_cwas(cpuid_info(), TRUE);
324 }
325
326 /* this function is Intel-specific */
327 static void
cpuid_set_cache_info(i386_cpu_info_t * info_p)328 cpuid_set_cache_info( i386_cpu_info_t * info_p )
329 {
330 uint32_t cpuid_result[4];
331 uint32_t reg[4];
332 uint32_t index;
333 uint32_t linesizes[LCACHE_MAX];
334 unsigned int i;
335 unsigned int j;
336 boolean_t cpuid_deterministic_supported = FALSE;
337 unsigned int dcnt = 0;
338
339 DBG("cpuid_set_cache_info(%p)\n", info_p);
340
341 bzero( linesizes, sizeof(linesizes));
342
343 /* Get processor cache descriptor info using leaf 2. We don't use
344 * this internally, but must publish it for KEXTs.
345 */
346 for (i = 0; i < sizeof(info_p->cache_info) / 16; i++) {
347 /* byte 0 gives number of cpuid calls to get all descriptors */
348 if (i > 0 && i >= info_p->cache_info[0]) {
349 break;
350 }
351
352 cpuid_fn(2, cpuid_result);
353 for (j = 0; j < 4; j++) {
354 if ((cpuid_result[j] >> 31) == 1) {
355 continue;
356 }
357 memcpy(&info_p->cache_info[dcnt], &cpuid_result[j], 4);
358 dcnt += 4;
359 }
360 }
361
362 /*
363 * Get cache info using leaf 4, the "deterministic cache parameters."
364 * Most processors Mac OS X supports implement this flavor of CPUID.
365 * Loop over each cache on the processor.
366 */
367 cpuid_fn(0, cpuid_result);
368 if (cpuid_result[eax] >= 4) {
369 cpuid_deterministic_supported = TRUE;
370 }
371
372 for (index = 0; cpuid_deterministic_supported; index++) {
373 cache_type_t type = Lnone;
374 uint32_t cache_type;
375 uint32_t cache_level;
376 uint32_t cache_sharing;
377 uint32_t cache_linesize;
378 uint32_t cache_sets;
379 uint32_t cache_associativity;
380 uint32_t cache_size;
381 uint32_t cache_partitions;
382 uint32_t colors;
383
384 reg[eax] = 4; /* cpuid request 4 */
385 reg[ecx] = index; /* index starting at 0 */
386 cpuid(reg);
387 DBG("cpuid(4) index=%d eax=0x%x\n", index, reg[eax]);
388 cache_type = bitfield32(reg[eax], 4, 0);
389 if (cache_type == 0) {
390 break; /* no more caches */
391 }
392 cache_level = bitfield32(reg[eax], 7, 5);
393 cache_sharing = bitfield32(reg[eax], 25, 14) + 1;
394 info_p->cpuid_cores_per_package
395 = bitfield32(reg[eax], 31, 26) + 1;
396 cache_linesize = bitfield32(reg[ebx], 11, 0) + 1;
397 cache_partitions = bitfield32(reg[ebx], 21, 12) + 1;
398 cache_associativity = bitfield32(reg[ebx], 31, 22) + 1;
399 cache_sets = bitfield32(reg[ecx], 31, 0) + 1;
400
401 /* Map type/levels returned by CPUID into cache_type_t */
402 switch (cache_level) {
403 case 1:
404 type = cache_type == 1 ? L1D :
405 cache_type == 2 ? L1I :
406 Lnone;
407 break;
408 case 2:
409 type = cache_type == 3 ? L2U :
410 Lnone;
411 break;
412 case 3:
413 type = cache_type == 3 ? L3U :
414 Lnone;
415 break;
416 default:
417 type = Lnone;
418 }
419
420 /* The total size of a cache is:
421 * ( linesize * sets * associativity * partitions )
422 */
423 if (type != Lnone) {
424 cache_size = cache_linesize * cache_sets *
425 cache_associativity * cache_partitions;
426 info_p->cache_size[type] = cache_size;
427 info_p->cache_sharing[type] = cache_sharing;
428 info_p->cache_partitions[type] = cache_partitions;
429 linesizes[type] = cache_linesize;
430
431 DBG(" cache_size[%s] : %d\n",
432 cache_type_str[type], cache_size);
433 DBG(" cache_sharing[%s] : %d\n",
434 cache_type_str[type], cache_sharing);
435 DBG(" cache_partitions[%s]: %d\n",
436 cache_type_str[type], cache_partitions);
437
438 /*
439 * Overwrite associativity determined via
440 * CPUID.0x80000006 -- this leaf is more
441 * accurate
442 */
443 if (type == L2U) {
444 info_p->cpuid_cache_L2_associativity = cache_associativity;
445 }
446 /*
447 * Adjust #sets to account for the N CBos
448 * This is because addresses are hashed across CBos
449 */
450 if (type == L3U && info_p->core_count) {
451 cache_sets = cache_sets / info_p->core_count;
452 }
453
454 /* Compute the number of page colors for this cache,
455 * which is:
456 * ( linesize * sets ) / page_size
457 *
458 * To help visualize this, consider two views of a
459 * physical address. To the cache, it is composed
460 * of a line offset, a set selector, and a tag.
461 * To VM, it is composed of a page offset, a page
462 * color, and other bits in the pageframe number:
463 *
464 * +-----------------+---------+--------+
465 * cache: | tag | set | offset |
466 * +-----------------+---------+--------+
467 *
468 * +-----------------+-------+----------+
469 * VM: | don't care | color | pg offset|
470 * +-----------------+-------+----------+
471 *
472 * The color is those bits in (set+offset) not covered
473 * by the page offset.
474 */
475 colors = (cache_linesize * cache_sets) >> 12;
476
477 if (colors > vm_cache_geometry_colors) {
478 vm_cache_geometry_colors = colors;
479 }
480 }
481 }
482 DBG(" vm_cache_geometry_colors: %d\n", vm_cache_geometry_colors);
483
484 /*
485 * If deterministic cache parameters are not available, use
486 * something else
487 */
488 if (info_p->cpuid_cores_per_package == 0) {
489 info_p->cpuid_cores_per_package = 1;
490
491 /* cpuid define in 1024 quantities */
492 info_p->cache_size[L2U] = info_p->cpuid_cache_size * 1024;
493 info_p->cache_sharing[L2U] = 1;
494 info_p->cache_partitions[L2U] = 1;
495
496 linesizes[L2U] = info_p->cpuid_cache_linesize;
497
498 DBG(" cache_size[L2U] : %d\n",
499 info_p->cache_size[L2U]);
500 DBG(" cache_sharing[L2U] : 1\n");
501 DBG(" cache_partitions[L2U]: 1\n");
502 DBG(" linesizes[L2U] : %d\n",
503 info_p->cpuid_cache_linesize);
504 }
505
506 /*
507 * What linesize to publish? We use the L2 linesize if any,
508 * else the L1D.
509 */
510 if (linesizes[L2U]) {
511 info_p->cache_linesize = linesizes[L2U];
512 } else if (linesizes[L1D]) {
513 info_p->cache_linesize = linesizes[L1D];
514 } else {
515 panic("no linesize");
516 }
517 DBG(" cache_linesize : %d\n", info_p->cache_linesize);
518
519 /*
520 * Extract and publish TLB information from Leaf 2 descriptors.
521 */
522 DBG(" %ld leaf2 descriptors:\n", sizeof(info_p->cache_info));
523 for (i = 1; i < sizeof(info_p->cache_info); i++) {
524 const cpuid_cache_descriptor_t *descp;
525 int id;
526 int level;
527 int page;
528
529 DBG(" 0x%02x", info_p->cache_info[i]);
530 descp = cpuid_leaf2_find(info_p->cache_info[i]);
531 if (descp == NULL) {
532 continue;
533 }
534
535 switch (descp->type) {
536 case TLB:
537 page = (descp->size == SMALL) ? TLB_SMALL : TLB_LARGE;
538 /* determine I or D: */
539 switch (descp->level) {
540 case INST:
541 id = TLB_INST;
542 break;
543 case DATA:
544 case DATA0:
545 case DATA1:
546 id = TLB_DATA;
547 break;
548 default:
549 continue;
550 }
551 /* determine level: */
552 switch (descp->level) {
553 case DATA1:
554 level = 1;
555 break;
556 default:
557 level = 0;
558 }
559 info_p->cpuid_tlb[id][page][level] = descp->entries;
560 break;
561 case STLB:
562 info_p->cpuid_stlb = descp->entries;
563 }
564 }
565 DBG("\n");
566 }
567
568 static void
cpuid_set_generic_info(i386_cpu_info_t * info_p)569 cpuid_set_generic_info(i386_cpu_info_t *info_p)
570 {
571 uint32_t reg[4];
572 char str[128], *p;
573
574 DBG("cpuid_set_generic_info(%p)\n", info_p);
575
576 /* do cpuid 0 to get vendor */
577 cpuid_fn(0, reg);
578 info_p->cpuid_max_basic = reg[eax];
579 bcopy((char *)®[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
580 bcopy((char *)®[ecx], &info_p->cpuid_vendor[8], 4);
581 bcopy((char *)®[edx], &info_p->cpuid_vendor[4], 4);
582 info_p->cpuid_vendor[12] = 0;
583
584 /* get extended cpuid results */
585 cpuid_fn(0x80000000, reg);
586 info_p->cpuid_max_ext = reg[eax];
587
588 /* check to see if we can get brand string */
589 if (info_p->cpuid_max_ext >= 0x80000004) {
590 /*
591 * The brand string 48 bytes (max), guaranteed to
592 * be NUL terminated.
593 */
594 cpuid_fn(0x80000002, reg);
595 bcopy((char *)reg, &str[0], 16);
596 cpuid_fn(0x80000003, reg);
597 bcopy((char *)reg, &str[16], 16);
598 cpuid_fn(0x80000004, reg);
599 bcopy((char *)reg, &str[32], 16);
600 for (p = str; *p != '\0'; p++) {
601 if (*p != ' ') {
602 break;
603 }
604 }
605 strlcpy(info_p->cpuid_brand_string,
606 p, sizeof(info_p->cpuid_brand_string));
607
608 if (!strncmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN,
609 min(sizeof(info_p->cpuid_brand_string),
610 strlen(CPUID_STRING_UNKNOWN) + 1))) {
611 /*
612 * This string means we have a firmware-programmable brand string,
613 * and the firmware couldn't figure out what sort of CPU we have.
614 */
615 info_p->cpuid_brand_string[0] = '\0';
616 }
617 }
618
619 /* Get cache and addressing info. */
620 if (info_p->cpuid_max_ext >= 0x80000006) {
621 uint32_t assoc;
622 cpuid_fn(0x80000006, reg);
623 info_p->cpuid_cache_linesize = bitfield32(reg[ecx], 7, 0);
624 assoc = bitfield32(reg[ecx], 15, 12);
625 /*
626 * L2 associativity is encoded, though in an insufficiently
627 * descriptive fashion, e.g. 24-way is mapped to 16-way.
628 * Represent a fully associative cache as 0xFFFF.
629 * Overwritten by associativity as determined via CPUID.4
630 * if available.
631 */
632 if (assoc == 6) {
633 assoc = 8;
634 } else if (assoc == 8) {
635 assoc = 16;
636 } else if (assoc == 0xF) {
637 assoc = 0xFFFF;
638 }
639 info_p->cpuid_cache_L2_associativity = assoc;
640 info_p->cpuid_cache_size = bitfield32(reg[ecx], 31, 16);
641 cpuid_fn(0x80000008, reg);
642 info_p->cpuid_address_bits_physical =
643 bitfield32(reg[eax], 7, 0);
644 info_p->cpuid_address_bits_virtual =
645 bitfield32(reg[eax], 15, 8);
646 }
647
648 /*
649 * Get processor signature and decode
650 * and bracket this with the approved procedure for reading the
651 * the microcode version number a.k.a. signature a.k.a. BIOS ID
652 */
653 wrmsr64(MSR_IA32_BIOS_SIGN_ID, 0);
654 cpuid_fn(1, reg);
655 info_p->cpuid_microcode_version =
656 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);
657 info_p->cpuid_signature = reg[eax];
658 info_p->cpuid_stepping = bitfield32(reg[eax], 3, 0);
659 info_p->cpuid_model = bitfield32(reg[eax], 7, 4);
660 info_p->cpuid_family = bitfield32(reg[eax], 11, 8);
661 info_p->cpuid_type = bitfield32(reg[eax], 13, 12);
662 info_p->cpuid_extmodel = bitfield32(reg[eax], 19, 16);
663 info_p->cpuid_extfamily = bitfield32(reg[eax], 27, 20);
664 info_p->cpuid_brand = bitfield32(reg[ebx], 7, 0);
665 info_p->cpuid_features = quad(reg[ecx], reg[edx]);
666
667 /* Get "processor flag"; necessary for microcode update matching */
668 info_p->cpuid_processor_flag = (rdmsr64(MSR_IA32_PLATFORM_ID) >> 50) & 0x7;
669
670 /* Fold extensions into family/model */
671 if (info_p->cpuid_family == 0x0f) {
672 info_p->cpuid_family += info_p->cpuid_extfamily;
673 }
674 if (info_p->cpuid_family == 0x0f || info_p->cpuid_family == 0x06) {
675 info_p->cpuid_model += (info_p->cpuid_extmodel << 4);
676 }
677
678 if (info_p->cpuid_features & CPUID_FEATURE_HTT) {
679 info_p->cpuid_logical_per_package =
680 bitfield32(reg[ebx], 23, 16);
681 } else {
682 info_p->cpuid_logical_per_package = 1;
683 }
684
685 if (info_p->cpuid_max_ext >= 0x80000001) {
686 cpuid_fn(0x80000001, reg);
687 info_p->cpuid_extfeatures =
688 quad(reg[ecx], reg[edx]);
689 }
690
691 DBG(" max_basic : %d\n", info_p->cpuid_max_basic);
692 DBG(" max_ext : 0x%08x\n", info_p->cpuid_max_ext);
693 DBG(" vendor : %s\n", info_p->cpuid_vendor);
694 DBG(" brand_string : %s\n", info_p->cpuid_brand_string);
695 DBG(" signature : 0x%08x\n", info_p->cpuid_signature);
696 DBG(" stepping : %d\n", info_p->cpuid_stepping);
697 DBG(" model : %d\n", info_p->cpuid_model);
698 DBG(" family : %d\n", info_p->cpuid_family);
699 DBG(" type : %d\n", info_p->cpuid_type);
700 DBG(" extmodel : %d\n", info_p->cpuid_extmodel);
701 DBG(" extfamily : %d\n", info_p->cpuid_extfamily);
702 DBG(" brand : %d\n", info_p->cpuid_brand);
703 DBG(" features : 0x%016llx\n", info_p->cpuid_features);
704 DBG(" extfeatures : 0x%016llx\n", info_p->cpuid_extfeatures);
705 DBG(" logical_per_package : %d\n", info_p->cpuid_logical_per_package);
706 DBG(" microcode_version : 0x%08x\n", info_p->cpuid_microcode_version);
707
708 /* Fold in the Invariant TSC feature bit, if present */
709 if (info_p->cpuid_max_ext >= 0x80000007) {
710 cpuid_fn(0x80000007, reg);
711 info_p->cpuid_extfeatures |=
712 reg[edx] & (uint32_t)CPUID_EXTFEATURE_TSCI;
713 DBG(" extfeatures : 0x%016llx\n",
714 info_p->cpuid_extfeatures);
715 }
716
717 if (info_p->cpuid_max_basic >= 0x5) {
718 cpuid_mwait_leaf_t *cmp = &info_p->cpuid_mwait_leaf;
719
720 /*
721 * Extract the Monitor/Mwait Leaf info:
722 */
723 cpuid_fn(5, reg);
724 cmp->linesize_min = reg[eax];
725 cmp->linesize_max = reg[ebx];
726 cmp->extensions = reg[ecx];
727 cmp->sub_Cstates = reg[edx];
728 info_p->cpuid_mwait_leafp = cmp;
729
730 DBG(" Monitor/Mwait Leaf:\n");
731 DBG(" linesize_min : %d\n", cmp->linesize_min);
732 DBG(" linesize_max : %d\n", cmp->linesize_max);
733 DBG(" extensions : %d\n", cmp->extensions);
734 DBG(" sub_Cstates : 0x%08x\n", cmp->sub_Cstates);
735 }
736
737 if (info_p->cpuid_max_basic >= 0x6) {
738 cpuid_thermal_leaf_t *ctp = &info_p->cpuid_thermal_leaf;
739
740 /*
741 * The thermal and Power Leaf:
742 */
743 cpuid_fn(6, reg);
744 ctp->sensor = bitfield32(reg[eax], 0, 0);
745 ctp->dynamic_acceleration = bitfield32(reg[eax], 1, 1);
746 ctp->invariant_APIC_timer = bitfield32(reg[eax], 2, 2);
747 ctp->core_power_limits = bitfield32(reg[eax], 4, 4);
748 ctp->fine_grain_clock_mod = bitfield32(reg[eax], 5, 5);
749 ctp->package_thermal_intr = bitfield32(reg[eax], 6, 6);
750 ctp->thresholds = bitfield32(reg[ebx], 3, 0);
751 ctp->ACNT_MCNT = bitfield32(reg[ecx], 0, 0);
752 ctp->hardware_feedback = bitfield32(reg[ecx], 1, 1);
753 ctp->energy_policy = bitfield32(reg[ecx], 3, 3);
754 info_p->cpuid_thermal_leafp = ctp;
755
756 DBG(" Thermal/Power Leaf:\n");
757 DBG(" sensor : %d\n", ctp->sensor);
758 DBG(" dynamic_acceleration : %d\n", ctp->dynamic_acceleration);
759 DBG(" invariant_APIC_timer : %d\n", ctp->invariant_APIC_timer);
760 DBG(" core_power_limits : %d\n", ctp->core_power_limits);
761 DBG(" fine_grain_clock_mod : %d\n", ctp->fine_grain_clock_mod);
762 DBG(" package_thermal_intr : %d\n", ctp->package_thermal_intr);
763 DBG(" thresholds : %d\n", ctp->thresholds);
764 DBG(" ACNT_MCNT : %d\n", ctp->ACNT_MCNT);
765 DBG(" ACNT2 : %d\n", ctp->hardware_feedback);
766 DBG(" energy_policy : %d\n", ctp->energy_policy);
767 }
768
769 if (info_p->cpuid_max_basic >= 0xa) {
770 cpuid_arch_perf_leaf_t *capp = &info_p->cpuid_arch_perf_leaf;
771
772 /*
773 * Architectural Performance Monitoring Leaf:
774 */
775 cpuid_fn(0xa, reg);
776 capp->version = bitfield32(reg[eax], 7, 0);
777 capp->number = bitfield32(reg[eax], 15, 8);
778 capp->width = bitfield32(reg[eax], 23, 16);
779 capp->events_number = bitfield32(reg[eax], 31, 24);
780 capp->events = reg[ebx];
781 capp->fixed_number = bitfield32(reg[edx], 4, 0);
782 capp->fixed_width = bitfield32(reg[edx], 12, 5);
783 info_p->cpuid_arch_perf_leafp = capp;
784
785 DBG(" Architectural Performance Monitoring Leaf:\n");
786 DBG(" version : %d\n", capp->version);
787 DBG(" number : %d\n", capp->number);
788 DBG(" width : %d\n", capp->width);
789 DBG(" events_number : %d\n", capp->events_number);
790 DBG(" events : %d\n", capp->events);
791 DBG(" fixed_number : %d\n", capp->fixed_number);
792 DBG(" fixed_width : %d\n", capp->fixed_width);
793 }
794
795 if (info_p->cpuid_max_basic >= 0xd) {
796 cpuid_xsave_leaf_t *xsp;
797 /*
798 * XSAVE Features:
799 */
800 xsp = &info_p->cpuid_xsave_leaf[0];
801 info_p->cpuid_xsave_leafp = xsp;
802 xsp->extended_state[eax] = 0xd;
803 xsp->extended_state[ecx] = 0;
804 cpuid(xsp->extended_state);
805 DBG(" XSAVE Main leaf:\n");
806 DBG(" EAX : 0x%x\n", xsp->extended_state[eax]);
807 DBG(" EBX : 0x%x\n", xsp->extended_state[ebx]);
808 DBG(" ECX : 0x%x\n", xsp->extended_state[ecx]);
809 DBG(" EDX : 0x%x\n", xsp->extended_state[edx]);
810
811 xsp = &info_p->cpuid_xsave_leaf[1];
812 xsp->extended_state[eax] = 0xd;
813 xsp->extended_state[ecx] = 1;
814 cpuid(xsp->extended_state);
815 DBG(" XSAVE Sub-leaf1:\n");
816 DBG(" EAX : 0x%x\n", xsp->extended_state[eax]);
817 DBG(" EBX : 0x%x\n", xsp->extended_state[ebx]);
818 DBG(" ECX : 0x%x\n", xsp->extended_state[ecx]);
819 DBG(" EDX : 0x%x\n", xsp->extended_state[edx]);
820 }
821
822 if (info_p->cpuid_model >= CPUID_MODEL_IVYBRIDGE) {
823 /*
824 * Leaf7 Features:
825 */
826 cpuid_fn(0x7, reg);
827 info_p->cpuid_leaf7_features = quad(reg[ecx], reg[ebx]);
828 info_p->cpuid_leaf7_extfeatures = reg[edx];
829
830 cpuid_tsx_supported = (reg[ebx] & (CPUID_LEAF7_FEATURE_HLE | CPUID_LEAF7_FEATURE_RTM)) != 0;
831
832 DBG(" Feature Leaf7:\n");
833 DBG(" EBX : 0x%x\n", reg[ebx]);
834 DBG(" ECX : 0x%x\n", reg[ecx]);
835 DBG(" EDX : 0x%x\n", reg[edx]);
836 }
837
838 if (info_p->cpuid_max_basic >= 0x15) {
839 /*
840 * TCS/CCC frequency leaf:
841 */
842 cpuid_fn(0x15, reg);
843 info_p->cpuid_tsc_leaf.denominator = reg[eax];
844 info_p->cpuid_tsc_leaf.numerator = reg[ebx];
845
846 DBG(" TSC/CCC Information Leaf:\n");
847 DBG(" numerator : 0x%x\n", reg[ebx]);
848 DBG(" denominator : 0x%x\n", reg[eax]);
849 }
850
851 return;
852 }
853
854 static uint32_t
cpuid_set_cpufamily(i386_cpu_info_t * info_p)855 cpuid_set_cpufamily(i386_cpu_info_t *info_p)
856 {
857 uint32_t cpufamily = CPUFAMILY_UNKNOWN;
858
859 switch (info_p->cpuid_family) {
860 case 6:
861 switch (info_p->cpuid_model) {
862 case 23:
863 cpufamily = CPUFAMILY_INTEL_PENRYN;
864 break;
865 case CPUID_MODEL_NEHALEM:
866 case CPUID_MODEL_FIELDS:
867 case CPUID_MODEL_DALES:
868 case CPUID_MODEL_NEHALEM_EX:
869 cpufamily = CPUFAMILY_INTEL_NEHALEM;
870 break;
871 case CPUID_MODEL_DALES_32NM:
872 case CPUID_MODEL_WESTMERE:
873 case CPUID_MODEL_WESTMERE_EX:
874 cpufamily = CPUFAMILY_INTEL_WESTMERE;
875 break;
876 case CPUID_MODEL_SANDYBRIDGE:
877 case CPUID_MODEL_JAKETOWN:
878 cpufamily = CPUFAMILY_INTEL_SANDYBRIDGE;
879 break;
880 case CPUID_MODEL_IVYBRIDGE:
881 case CPUID_MODEL_IVYBRIDGE_EP:
882 cpufamily = CPUFAMILY_INTEL_IVYBRIDGE;
883 break;
884 case CPUID_MODEL_HASWELL:
885 case CPUID_MODEL_HASWELL_EP:
886 case CPUID_MODEL_HASWELL_ULT:
887 case CPUID_MODEL_CRYSTALWELL:
888 cpufamily = CPUFAMILY_INTEL_HASWELL;
889 break;
890 case CPUID_MODEL_BROADWELL:
891 case CPUID_MODEL_BRYSTALWELL:
892 cpufamily = CPUFAMILY_INTEL_BROADWELL;
893 break;
894 case CPUID_MODEL_SKYLAKE:
895 case CPUID_MODEL_SKYLAKE_DT:
896 case CPUID_MODEL_SKYLAKE_W:
897 cpufamily = CPUFAMILY_INTEL_SKYLAKE;
898 break;
899 case CPUID_MODEL_KABYLAKE:
900 case CPUID_MODEL_KABYLAKE_DT:
901 cpufamily = CPUFAMILY_INTEL_KABYLAKE;
902 break;
903 case CPUID_MODEL_ICELAKE:
904 case CPUID_MODEL_ICELAKE_H:
905 case CPUID_MODEL_ICELAKE_DT:
906 cpufamily = CPUFAMILY_INTEL_ICELAKE;
907 break;
908 }
909 break;
910 }
911
912 info_p->cpuid_cpufamily = cpufamily;
913 DBG("cpuid_set_cpufamily(%p) returning 0x%x\n", info_p, cpufamily);
914 return cpufamily;
915 }
916 /*
917 * Must be invoked either when executing single threaded, or with
918 * independent synchronization.
919 */
920 void
cpuid_set_info(void)921 cpuid_set_info(void)
922 {
923 i386_cpu_info_t *info_p = &cpuid_cpu_info;
924 boolean_t enable_x86_64h = TRUE;
925
926 /* Perform pre-cpuid workarounds (since their effects impact values returned via cpuid) */
927 cpuid_do_precpuid_was();
928
929 cpuid_set_generic_info(info_p);
930
931 /* verify we are running on a supported CPU */
932 if ((strncmp(CPUID_VID_INTEL, info_p->cpuid_vendor,
933 min(strlen(CPUID_STRING_UNKNOWN) + 1,
934 sizeof(info_p->cpuid_vendor)))) ||
935 (cpuid_set_cpufamily(info_p) == CPUFAMILY_UNKNOWN)) {
936 panic("Unsupported CPU");
937 }
938
939 info_p->cpuid_cpu_type = CPU_TYPE_X86;
940
941 if (!PE_parse_boot_argn("-enable_x86_64h", &enable_x86_64h, sizeof(enable_x86_64h))) {
942 boolean_t disable_x86_64h = FALSE;
943
944 if (PE_parse_boot_argn("-disable_x86_64h", &disable_x86_64h, sizeof(disable_x86_64h))) {
945 enable_x86_64h = FALSE;
946 }
947 }
948
949 if (enable_x86_64h &&
950 ((info_p->cpuid_features & CPUID_X86_64_H_FEATURE_SUBSET) == CPUID_X86_64_H_FEATURE_SUBSET) &&
951 ((info_p->cpuid_extfeatures & CPUID_X86_64_H_EXTFEATURE_SUBSET) == CPUID_X86_64_H_EXTFEATURE_SUBSET) &&
952 ((info_p->cpuid_leaf7_features & CPUID_X86_64_H_LEAF7_FEATURE_SUBSET) == CPUID_X86_64_H_LEAF7_FEATURE_SUBSET)) {
953 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_64_H;
954 } else {
955 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
956 }
957 /* cpuid_set_cache_info must be invoked after set_generic_info */
958
959 /*
960 * Find the number of enabled cores and threads
961 * (which determines whether SMT/Hyperthreading is active).
962 */
963
964 /*
965 * Not all VMMs emulate MSR_CORE_THREAD_COUNT (0x35).
966 */
967 if (0 != (info_p->cpuid_features & CPUID_FEATURE_VMM) &&
968 PE_parse_boot_argn("-nomsr35h", NULL, 0)) {
969 info_p->core_count = 1;
970 info_p->thread_count = 1;
971 cpuid_set_cache_info(info_p);
972 } else {
973 switch (info_p->cpuid_cpufamily) {
974 case CPUFAMILY_INTEL_PENRYN:
975 cpuid_set_cache_info(info_p);
976 info_p->core_count = info_p->cpuid_cores_per_package;
977 info_p->thread_count = info_p->cpuid_logical_per_package;
978 break;
979 case CPUFAMILY_INTEL_WESTMERE: {
980 /*
981 * This should be the same as Nehalem but an A0 silicon bug returns
982 * invalid data in the top 12 bits. Hence, we use only bits [19..16]
983 * rather than [31..16] for core count - which actually can't exceed 8.
984 */
985 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
986 if (0 == msr) {
987 /* Provide a non-zero default for some VMMs */
988 msr = (1 << 16) | 1;
989 }
990 info_p->core_count = bitfield32((uint32_t)msr, 19, 16);
991 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0);
992 cpuid_set_cache_info(info_p);
993 break;
994 }
995 default: {
996 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
997 if (0 == msr) {
998 /* Provide a non-zero default for some VMMs */
999 msr = (1 << 16) | 1;
1000 }
1001 info_p->core_count = bitfield32((uint32_t)msr, 31, 16);
1002 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0);
1003 cpuid_set_cache_info(info_p);
1004 break;
1005 }
1006 }
1007 }
1008
1009 DBG("cpuid_set_info():\n");
1010 DBG(" core_count : %d\n", info_p->core_count);
1011 DBG(" thread_count : %d\n", info_p->thread_count);
1012 DBG(" cpu_type: 0x%08x\n", info_p->cpuid_cpu_type);
1013 DBG(" cpu_subtype: 0x%08x\n", info_p->cpuid_cpu_subtype);
1014
1015 info_p->cpuid_model_string = ""; /* deprecated */
1016
1017 /* Init CPU LBRs */
1018 i386_lbr_init(info_p, true);
1019
1020 do_cwas(info_p, FALSE);
1021 }
1022
1023 static struct table {
1024 uint64_t mask;
1025 const char *name;
1026 } feature_map[] = {
1027 {CPUID_FEATURE_FPU, "FPU"},
1028 {CPUID_FEATURE_VME, "VME"},
1029 {CPUID_FEATURE_DE, "DE"},
1030 {CPUID_FEATURE_PSE, "PSE"},
1031 {CPUID_FEATURE_TSC, "TSC"},
1032 {CPUID_FEATURE_MSR, "MSR"},
1033 {CPUID_FEATURE_PAE, "PAE"},
1034 {CPUID_FEATURE_MCE, "MCE"},
1035 {CPUID_FEATURE_CX8, "CX8"},
1036 {CPUID_FEATURE_APIC, "APIC"},
1037 {CPUID_FEATURE_SEP, "SEP"},
1038 {CPUID_FEATURE_MTRR, "MTRR"},
1039 {CPUID_FEATURE_PGE, "PGE"},
1040 {CPUID_FEATURE_MCA, "MCA"},
1041 {CPUID_FEATURE_CMOV, "CMOV"},
1042 {CPUID_FEATURE_PAT, "PAT"},
1043 {CPUID_FEATURE_PSE36, "PSE36"},
1044 {CPUID_FEATURE_PSN, "PSN"},
1045 {CPUID_FEATURE_CLFSH, "CLFSH"},
1046 {CPUID_FEATURE_DS, "DS"},
1047 {CPUID_FEATURE_ACPI, "ACPI"},
1048 {CPUID_FEATURE_MMX, "MMX"},
1049 {CPUID_FEATURE_FXSR, "FXSR"},
1050 {CPUID_FEATURE_SSE, "SSE"},
1051 {CPUID_FEATURE_SSE2, "SSE2"},
1052 {CPUID_FEATURE_SS, "SS"},
1053 {CPUID_FEATURE_HTT, "HTT"},
1054 {CPUID_FEATURE_TM, "TM"},
1055 {CPUID_FEATURE_PBE, "PBE"},
1056 {CPUID_FEATURE_SSE3, "SSE3"},
1057 {CPUID_FEATURE_PCLMULQDQ, "PCLMULQDQ"},
1058 {CPUID_FEATURE_DTES64, "DTES64"},
1059 {CPUID_FEATURE_MONITOR, "MON"},
1060 {CPUID_FEATURE_DSCPL, "DSCPL"},
1061 {CPUID_FEATURE_VMX, "VMX"},
1062 {CPUID_FEATURE_SMX, "SMX"},
1063 {CPUID_FEATURE_EST, "EST"},
1064 {CPUID_FEATURE_TM2, "TM2"},
1065 {CPUID_FEATURE_SSSE3, "SSSE3"},
1066 {CPUID_FEATURE_CID, "CID"},
1067 {CPUID_FEATURE_FMA, "FMA"},
1068 {CPUID_FEATURE_CX16, "CX16"},
1069 {CPUID_FEATURE_xTPR, "TPR"},
1070 {CPUID_FEATURE_PDCM, "PDCM"},
1071 {CPUID_FEATURE_SSE4_1, "SSE4.1"},
1072 {CPUID_FEATURE_SSE4_2, "SSE4.2"},
1073 {CPUID_FEATURE_x2APIC, "x2APIC"},
1074 {CPUID_FEATURE_MOVBE, "MOVBE"},
1075 {CPUID_FEATURE_POPCNT, "POPCNT"},
1076 {CPUID_FEATURE_AES, "AES"},
1077 {CPUID_FEATURE_VMM, "VMM"},
1078 {CPUID_FEATURE_PCID, "PCID"},
1079 {CPUID_FEATURE_XSAVE, "XSAVE"},
1080 {CPUID_FEATURE_OSXSAVE, "OSXSAVE"},
1081 {CPUID_FEATURE_SEGLIM64, "SEGLIM64"},
1082 {CPUID_FEATURE_TSCTMR, "TSCTMR"},
1083 {CPUID_FEATURE_AVX1_0, "AVX1.0"},
1084 {CPUID_FEATURE_RDRAND, "RDRAND"},
1085 {CPUID_FEATURE_F16C, "F16C"},
1086 {0, 0}
1087 },
1088 extfeature_map[] = {
1089 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"},
1090 {CPUID_EXTFEATURE_XD, "XD"},
1091 {CPUID_EXTFEATURE_1GBPAGE, "1GBPAGE"},
1092 {CPUID_EXTFEATURE_EM64T, "EM64T"},
1093 {CPUID_EXTFEATURE_LAHF, "LAHF"},
1094 {CPUID_EXTFEATURE_LZCNT, "LZCNT"},
1095 {CPUID_EXTFEATURE_PREFETCHW, "PREFETCHW"},
1096 {CPUID_EXTFEATURE_RDTSCP, "RDTSCP"},
1097 {CPUID_EXTFEATURE_TSCI, "TSCI"},
1098 {0, 0}
1099 },
1100 leaf7_feature_map[] = {
1101 {CPUID_LEAF7_FEATURE_RDWRFSGS, "RDWRFSGS"},
1102 {CPUID_LEAF7_FEATURE_TSCOFF, "TSC_THREAD_OFFSET"},
1103 {CPUID_LEAF7_FEATURE_SGX, "SGX"},
1104 {CPUID_LEAF7_FEATURE_BMI1, "BMI1"},
1105 {CPUID_LEAF7_FEATURE_HLE, "HLE"},
1106 {CPUID_LEAF7_FEATURE_AVX2, "AVX2"},
1107 {CPUID_LEAF7_FEATURE_FDPEO, "FDPEO"},
1108 {CPUID_LEAF7_FEATURE_SMEP, "SMEP"},
1109 {CPUID_LEAF7_FEATURE_BMI2, "BMI2"},
1110 {CPUID_LEAF7_FEATURE_ERMS, "ERMS"},
1111 {CPUID_LEAF7_FEATURE_INVPCID, "INVPCID"},
1112 {CPUID_LEAF7_FEATURE_RTM, "RTM"},
1113 {CPUID_LEAF7_FEATURE_PQM, "PQM"},
1114 {CPUID_LEAF7_FEATURE_FPU_CSDS, "FPU_CSDS"},
1115 {CPUID_LEAF7_FEATURE_MPX, "MPX"},
1116 {CPUID_LEAF7_FEATURE_PQE, "PQE"},
1117 {CPUID_LEAF7_FEATURE_AVX512F, "AVX512F"},
1118 {CPUID_LEAF7_FEATURE_AVX512DQ, "AVX512DQ"},
1119 {CPUID_LEAF7_FEATURE_RDSEED, "RDSEED"},
1120 {CPUID_LEAF7_FEATURE_ADX, "ADX"},
1121 {CPUID_LEAF7_FEATURE_SMAP, "SMAP"},
1122 {CPUID_LEAF7_FEATURE_AVX512IFMA, "AVX512IFMA"},
1123 {CPUID_LEAF7_FEATURE_CLFSOPT, "CLFSOPT"},
1124 {CPUID_LEAF7_FEATURE_CLWB, "CLWB"},
1125 {CPUID_LEAF7_FEATURE_IPT, "IPT"},
1126 {CPUID_LEAF7_FEATURE_AVX512CD, "AVX512CD"},
1127 {CPUID_LEAF7_FEATURE_SHA, "SHA"},
1128 {CPUID_LEAF7_FEATURE_AVX512BW, "AVX512BW"},
1129 {CPUID_LEAF7_FEATURE_AVX512VL, "AVX512VL"},
1130 {CPUID_LEAF7_FEATURE_PREFETCHWT1, "PREFETCHWT1"},
1131 {CPUID_LEAF7_FEATURE_AVX512VBMI, "AVX512VBMI"},
1132 {CPUID_LEAF7_FEATURE_UMIP, "UMIP"},
1133 {CPUID_LEAF7_FEATURE_PKU, "PKU"},
1134 {CPUID_LEAF7_FEATURE_OSPKE, "OSPKE"},
1135 {CPUID_LEAF7_FEATURE_WAITPKG, "WAITPKG"},
1136 {CPUID_LEAF7_FEATURE_GFNI, "GFNI"},
1137 {CPUID_LEAF7_FEATURE_VAES, "VAES"},
1138 {CPUID_LEAF7_FEATURE_VPCLMULQDQ, "VPCLMULQDQ"},
1139 {CPUID_LEAF7_FEATURE_AVX512VNNI, "AVX512VNNI"},
1140 {CPUID_LEAF7_FEATURE_AVX512BITALG, "AVX512BITALG"},
1141 {CPUID_LEAF7_FEATURE_AVX512VPCDQ, "AVX512VPOPCNTDQ"},
1142 {CPUID_LEAF7_FEATURE_RDPID, "RDPID"},
1143 {CPUID_LEAF7_FEATURE_CLDEMOTE, "CLDEMOTE"},
1144 {CPUID_LEAF7_FEATURE_MOVDIRI, "MOVDIRI"},
1145 {CPUID_LEAF7_FEATURE_MOVDIRI64B, "MOVDIRI64B"},
1146 {CPUID_LEAF7_FEATURE_SGXLC, "SGXLC"},
1147 {0, 0}
1148 },
1149 leaf7_extfeature_map[] = {
1150 { CPUID_LEAF7_EXTFEATURE_AVX5124VNNIW, "AVX5124VNNIW" },
1151 { CPUID_LEAF7_EXTFEATURE_AVX5124FMAPS, "AVX5124FMAPS" },
1152 { CPUID_LEAF7_EXTFEATURE_FSREPMOV, "FSREPMOV" },
1153 { CPUID_LEAF7_EXTFEATURE_MDCLEAR, "MDCLEAR" },
1154 { CPUID_LEAF7_EXTFEATURE_TSXFA, "TSXFA" },
1155 { CPUID_LEAF7_EXTFEATURE_IBRS, "IBRS" },
1156 { CPUID_LEAF7_EXTFEATURE_STIBP, "STIBP" },
1157 { CPUID_LEAF7_EXTFEATURE_L1DF, "L1DF" },
1158 { CPUID_LEAF7_EXTFEATURE_ACAPMSR, "ACAPMSR" },
1159 { CPUID_LEAF7_EXTFEATURE_CCAPMSR, "CCAPMSR" },
1160 { CPUID_LEAF7_EXTFEATURE_SSBD, "SSBD" },
1161 {0, 0}
1162 };
1163
1164 static char *
cpuid_get_names(struct table * map,uint64_t bits,char * buf,unsigned buf_len)1165 cpuid_get_names(struct table *map, uint64_t bits, char *buf, unsigned buf_len)
1166 {
1167 size_t len = 0;
1168 char *p = buf;
1169 int i;
1170
1171 for (i = 0; map[i].mask != 0; i++) {
1172 if ((bits & map[i].mask) == 0) {
1173 continue;
1174 }
1175 if (len && ((size_t) (p - buf) < (buf_len - 1))) {
1176 *p++ = ' ';
1177 }
1178 len = min(strlen(map[i].name), (size_t)((buf_len - 1) - (p - buf)));
1179 if (len == 0) {
1180 break;
1181 }
1182 bcopy(map[i].name, p, len);
1183 p += len;
1184 }
1185 *p = '\0';
1186 return buf;
1187 }
1188
1189 i386_cpu_info_t *
cpuid_info(void)1190 cpuid_info(void)
1191 {
1192 /* Set-up the cpuid_info stucture lazily */
1193 if (cpuid_cpu_infop == NULL) {
1194 PE_parse_boot_argn("-cpuid", &cpuid_dbg, sizeof(cpuid_dbg));
1195 cpuid_set_info();
1196 cpuid_cpu_infop = &cpuid_cpu_info;
1197 }
1198 return cpuid_cpu_infop;
1199 }
1200
1201 char *
cpuid_get_feature_names(uint64_t features,char * buf,unsigned buf_len)1202 cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len)
1203 {
1204 return cpuid_get_names(feature_map, features, buf, buf_len);
1205 }
1206
1207 char *
cpuid_get_extfeature_names(uint64_t extfeatures,char * buf,unsigned buf_len)1208 cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len)
1209 {
1210 return cpuid_get_names(extfeature_map, extfeatures, buf, buf_len);
1211 }
1212
1213 char *
cpuid_get_leaf7_feature_names(uint64_t features,char * buf,unsigned buf_len)1214 cpuid_get_leaf7_feature_names(uint64_t features, char *buf, unsigned buf_len)
1215 {
1216 return cpuid_get_names(leaf7_feature_map, features, buf, buf_len);
1217 }
1218
1219 char *
cpuid_get_leaf7_extfeature_names(uint64_t features,char * buf,unsigned buf_len)1220 cpuid_get_leaf7_extfeature_names(uint64_t features, char *buf, unsigned buf_len)
1221 {
1222 return cpuid_get_names(leaf7_extfeature_map, features, buf, buf_len);
1223 }
1224
1225 void
cpuid_feature_display(const char * header)1226 cpuid_feature_display(
1227 const char *header)
1228 {
1229 char buf[320];
1230
1231 kprintf("%s: %s", header,
1232 cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf)));
1233 if (cpuid_leaf7_features()) {
1234 kprintf(" %s", cpuid_get_leaf7_feature_names(
1235 cpuid_leaf7_features(), buf, sizeof(buf)));
1236 }
1237 if (cpuid_leaf7_extfeatures()) {
1238 kprintf(" %s", cpuid_get_leaf7_extfeature_names(
1239 cpuid_leaf7_extfeatures(), buf, sizeof(buf)));
1240 }
1241 kprintf("\n");
1242 if (cpuid_features() & CPUID_FEATURE_HTT) {
1243 #define s_if_plural(n) ((n > 1) ? "s" : "")
1244 kprintf(" HTT: %d core%s per package;"
1245 " %d logical cpu%s per package\n",
1246 cpuid_cpu_infop->cpuid_cores_per_package,
1247 s_if_plural(cpuid_cpu_infop->cpuid_cores_per_package),
1248 cpuid_cpu_infop->cpuid_logical_per_package,
1249 s_if_plural(cpuid_cpu_infop->cpuid_logical_per_package));
1250 }
1251 }
1252
1253 void
cpuid_extfeature_display(const char * header)1254 cpuid_extfeature_display(
1255 const char *header)
1256 {
1257 char buf[256];
1258
1259 kprintf("%s: %s\n", header,
1260 cpuid_get_extfeature_names(cpuid_extfeatures(),
1261 buf, sizeof(buf)));
1262 }
1263
1264 void
cpuid_cpu_display(const char * header)1265 cpuid_cpu_display(
1266 const char *header)
1267 {
1268 if (cpuid_cpu_infop->cpuid_brand_string[0] != '\0') {
1269 kprintf("%s: %s\n", header, cpuid_cpu_infop->cpuid_brand_string);
1270 }
1271 }
1272
1273 unsigned int
cpuid_family(void)1274 cpuid_family(void)
1275 {
1276 return cpuid_info()->cpuid_family;
1277 }
1278
1279 uint32_t
cpuid_cpufamily(void)1280 cpuid_cpufamily(void)
1281 {
1282 return cpuid_info()->cpuid_cpufamily;
1283 }
1284
1285 cpu_type_t
cpuid_cputype(void)1286 cpuid_cputype(void)
1287 {
1288 return cpuid_info()->cpuid_cpu_type;
1289 }
1290
1291 cpu_subtype_t
cpuid_cpusubtype(void)1292 cpuid_cpusubtype(void)
1293 {
1294 return cpuid_info()->cpuid_cpu_subtype;
1295 }
1296
1297 uint64_t
cpuid_features(void)1298 cpuid_features(void)
1299 {
1300 static int checked = 0;
1301 char fpu_arg[20] = { 0 };
1302
1303 (void) cpuid_info();
1304 if (!checked) {
1305 /* check for boot-time fpu limitations */
1306 if (PE_parse_boot_argn("_fpu", &fpu_arg[0], sizeof(fpu_arg))) {
1307 printf("limiting fpu features to: %s\n", fpu_arg);
1308 if (!strncmp("387", fpu_arg, sizeof("387")) || !strncmp("mmx", fpu_arg, sizeof("mmx"))) {
1309 printf("no sse or sse2\n");
1310 cpuid_cpu_infop->cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
1311 } else if (!strncmp("sse", fpu_arg, sizeof("sse"))) {
1312 printf("no sse2\n");
1313 cpuid_cpu_infop->cpuid_features &= ~(CPUID_FEATURE_SSE2);
1314 }
1315 }
1316 checked = 1;
1317 }
1318 return cpuid_cpu_infop->cpuid_features;
1319 }
1320
1321 uint64_t
cpuid_extfeatures(void)1322 cpuid_extfeatures(void)
1323 {
1324 return cpuid_info()->cpuid_extfeatures;
1325 }
1326
1327 uint64_t
cpuid_leaf7_features(void)1328 cpuid_leaf7_features(void)
1329 {
1330 return cpuid_info()->cpuid_leaf7_features;
1331 }
1332
1333 uint64_t
cpuid_leaf7_extfeatures(void)1334 cpuid_leaf7_extfeatures(void)
1335 {
1336 return cpuid_info()->cpuid_leaf7_extfeatures;
1337 }
1338
1339 const char *
cpuid_vmm_family_string(void)1340 cpuid_vmm_family_string(void)
1341 {
1342 switch (cpuid_vmm_info()->cpuid_vmm_family) {
1343 case CPUID_VMM_FAMILY_NONE:
1344 return "None";
1345
1346 case CPUID_VMM_FAMILY_VMWARE:
1347 return "VMWare";
1348
1349 case CPUID_VMM_FAMILY_PARALLELS:
1350 return "Parallels";
1351
1352 case CPUID_VMM_FAMILY_HYVE:
1353 return "xHyve";
1354
1355 case CPUID_VMM_FAMILY_HVF:
1356 return "HVF";
1357
1358 case CPUID_VMM_FAMILY_KVM:
1359 return "KVM";
1360
1361 case CPUID_VMM_FAMILY_UNKNOWN:
1362 /*FALLTHROUGH*/
1363 default:
1364 return "Unknown VMM";
1365 }
1366 }
1367
1368 static i386_vmm_info_t *_cpuid_vmm_infop = NULL;
1369 static i386_vmm_info_t _cpuid_vmm_info;
1370
1371 static void
cpuid_init_vmm_info(i386_vmm_info_t * info_p)1372 cpuid_init_vmm_info(i386_vmm_info_t *info_p)
1373 {
1374 uint32_t reg[4], maxbasic_regs[4];
1375 uint32_t max_vmm_leaf;
1376
1377 bzero(info_p, sizeof(*info_p));
1378
1379 if (!cpuid_vmm_present()) {
1380 return;
1381 }
1382
1383 DBG("cpuid_init_vmm_info(%p)\n", info_p);
1384
1385 /*
1386 * Get the highest basic leaf value, then save the cpuid details for that leaf
1387 * for comparison with the [ostensible] VMM leaf.
1388 */
1389 cpuid_fn(0, reg);
1390 cpuid_fn(reg[eax], maxbasic_regs);
1391
1392 /* do cpuid 0x40000000 to get VMM vendor */
1393 cpuid_fn(0x40000000, reg);
1394
1395 /*
1396 * If leaf 0x40000000 is non-existent, cpuid will return the values as
1397 * if the highest basic leaf was requested, so compare to those values
1398 * we just retrieved to see if no vmm is present.
1399 */
1400 if (bcmp(reg, maxbasic_regs, sizeof(reg)) == 0) {
1401 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_NONE;
1402 DBG(" vmm_vendor : NONE\n");
1403 return;
1404 }
1405
1406 max_vmm_leaf = reg[eax];
1407 bcopy((char *)®[ebx], &info_p->cpuid_vmm_vendor[0], 4);
1408 bcopy((char *)®[ecx], &info_p->cpuid_vmm_vendor[4], 4);
1409 bcopy((char *)®[edx], &info_p->cpuid_vmm_vendor[8], 4);
1410 info_p->cpuid_vmm_vendor[12] = '\0';
1411
1412 if (0 == strcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_VMWARE)) {
1413 /* VMware identification string: kb.vmware.com/kb/1009458 */
1414 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_VMWARE;
1415 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_PARALLELS, 12)) {
1416 /* Parallels identification string */
1417 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_PARALLELS;
1418 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_HYVE, 12)) {
1419 /* bhyve/xhyve identification string */
1420 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_HYVE;
1421 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_HVF, 12)) {
1422 /* HVF identification string */
1423 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_HVF;
1424 } else if (0 == bcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_KVM, 12)) {
1425 /* KVM identification string */
1426 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_KVM;
1427 if (max_vmm_leaf >= 0x40000001) {
1428 cpuid_fn(0x40000001, reg);
1429 info_p->cpuid_vmm_kvm_features =
1430 quad(reg[edx], reg[eax]);
1431 }
1432 } else {
1433 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_UNKNOWN;
1434 }
1435
1436 /* VMM generic leaves: https://lkml.org/lkml/2008/10/1/246 */
1437 if (max_vmm_leaf >= 0x40000010) {
1438 cpuid_fn(0x40000010, reg);
1439
1440 info_p->cpuid_vmm_tsc_frequency = reg[eax];
1441 info_p->cpuid_vmm_bus_frequency = reg[ebx];
1442 }
1443
1444 cpuid_vmm_detect_pv_interface(info_p, APPLEPV_SIGNATURE, &cpuid_vmm_detect_applepv_features);
1445
1446 DBG(" vmm_vendor : %s\n", info_p->cpuid_vmm_vendor);
1447 DBG(" vmm_family : %u\n", info_p->cpuid_vmm_family);
1448 DBG(" vmm_bus_frequency : %u\n", info_p->cpuid_vmm_bus_frequency);
1449 DBG(" vmm_tsc_frequency : %u\n", info_p->cpuid_vmm_tsc_frequency);
1450 }
1451
1452 boolean_t
cpuid_vmm_present(void)1453 cpuid_vmm_present(void)
1454 {
1455 return (cpuid_features() & CPUID_FEATURE_VMM) ? TRUE : FALSE;
1456 }
1457
1458 i386_vmm_info_t *
cpuid_vmm_info(void)1459 cpuid_vmm_info(void)
1460 {
1461 if (_cpuid_vmm_infop == NULL) {
1462 cpuid_init_vmm_info(&_cpuid_vmm_info);
1463 _cpuid_vmm_infop = &_cpuid_vmm_info;
1464 }
1465 return _cpuid_vmm_infop;
1466 }
1467
1468 uint32_t
cpuid_vmm_family(void)1469 cpuid_vmm_family(void)
1470 {
1471 return cpuid_vmm_info()->cpuid_vmm_family;
1472 }
1473
1474 uint64_t
cpuid_vmm_get_kvm_features(void)1475 cpuid_vmm_get_kvm_features(void)
1476 {
1477 return cpuid_vmm_info()->cpuid_vmm_kvm_features;
1478 }
1479
1480 uint64_t
cpuid_vmm_get_applepv_features(void)1481 cpuid_vmm_get_applepv_features(void)
1482 {
1483 return cpuid_vmm_info()->cpuid_vmm_applepv_features;
1484 }
1485
1486 cwa_classifier_e
cpuid_wa_required(cpu_wa_e wa)1487 cpuid_wa_required(cpu_wa_e wa)
1488 {
1489 i386_cpu_info_t *info_p = &cpuid_cpu_info;
1490 static uint64_t bootarg_cpu_wa_enables = 0;
1491 static uint64_t bootarg_cpu_wa_disables = 0;
1492 static int bootargs_overrides_processed = 0;
1493 uint32_t reg[4];
1494
1495 if (!bootargs_overrides_processed) {
1496 if (!PE_parse_boot_argn("cwae", &bootarg_cpu_wa_enables, sizeof(bootarg_cpu_wa_enables))) {
1497 bootarg_cpu_wa_enables = 0;
1498 }
1499
1500 if (!PE_parse_boot_argn("cwad", &bootarg_cpu_wa_disables, sizeof(bootarg_cpu_wa_disables))) {
1501 bootarg_cpu_wa_disables = 0;
1502 }
1503 bootargs_overrides_processed = 1;
1504 }
1505
1506 if (bootarg_cpu_wa_enables & (1 << wa)) {
1507 return CWA_FORCE_ON;
1508 }
1509
1510 if (bootarg_cpu_wa_disables & (1 << wa)) {
1511 return CWA_FORCE_OFF;
1512 }
1513
1514 switch (wa) {
1515 case CPU_INTEL_SEGCHK:
1516 /* First, check to see if this CPU requires the workaround */
1517 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_ACAPMSR) != 0) {
1518 /* We have ARCHCAP, so check it for either RDCL_NO or MDS_NO */
1519 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES);
1520 if ((archcap_msr & (MSR_IA32_ARCH_CAPABILITIES_RDCL_NO | MSR_IA32_ARCH_CAPABILITIES_MDS_NO)) != 0) {
1521 /* Workaround not needed */
1522 return CWA_OFF;
1523 }
1524 }
1525
1526 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_MDCLEAR) != 0) {
1527 return CWA_ON;
1528 }
1529
1530 /*
1531 * If the CPU supports the ARCHCAP MSR and neither the RDCL_NO bit nor the MDS_NO
1532 * bit are set, OR the CPU does not support the ARCHCAP MSR and the CPU does
1533 * not enumerate the presence of the enhanced VERW instruction, report
1534 * that the workaround should not be enabled.
1535 */
1536 break;
1537
1538 case CPU_INTEL_TSXFA:
1539 /*
1540 * Note that if TSX was disabled in cpuid_do_precpuid_was(), the cached cpuid
1541 * info will indicate that RTM is *not* supported and this workaround will not
1542 * be enabled.
1543 */
1544 /*
1545 * Otherwise, if the CPU supports both TSX(HLE) and FORCE_ABORT, return that
1546 * the workaround should be enabled.
1547 */
1548 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_TSXFA) != 0 &&
1549 (info_p->cpuid_leaf7_features & CPUID_LEAF7_FEATURE_RTM) != 0) {
1550 return CWA_ON;
1551 }
1552 break;
1553
1554 case CPU_INTEL_TSXDA:
1555 /*
1556 * Since this workaround might be requested before cpuid_set_info() is complete,
1557 * we need to invoke cpuid directly when looking for the required bits.
1558 */
1559 cpuid_fn(0x7, reg);
1560 if (reg[edx] & CPUID_LEAF7_EXTFEATURE_ACAPMSR) {
1561 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES);
1562 /*
1563 * If this CPU supports TSX (HLE being the proxy for TSX detection) AND it does
1564 * not include a hardware fix for TAA and it supports the TSX_CTRL MSR, disable TSX entirely.
1565 * (Note this can be overridden (above) if the cwad boot-arg's value has bit 2 set.)
1566 */
1567 if ((reg[ebx] & CPUID_LEAF7_FEATURE_HLE) != 0 &&
1568 (archcap_msr & (MSR_IA32_ARCH_CAPABILITIES_TAA_NO | MSR_IA32_ARCH_CAPABILITIES_TSX_CTRL))
1569 == MSR_IA32_ARCH_CAPABILITIES_TSX_CTRL) {
1570 return CWA_ON;
1571 }
1572 }
1573 break;
1574
1575 case CPU_INTEL_SRBDS:
1576 /*
1577 * SRBDS mitigations are enabled by default. CWA_ON returned here indicates
1578 * the caller should disable the mitigation. Mitigations should be disabled
1579 * at least for CPUs that advertise MDS_NO *and* (either TAA_NO is set OR TSX
1580 * has been disabled).
1581 */
1582 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_SRBDS_CTRL) != 0) {
1583 if ((info_p->cpuid_leaf7_extfeatures & CPUID_LEAF7_EXTFEATURE_ACAPMSR) != 0) {
1584 uint64_t archcap_msr = rdmsr64(MSR_IA32_ARCH_CAPABILITIES);
1585 if ((archcap_msr & MSR_IA32_ARCH_CAPABILITIES_MDS_NO) != 0 &&
1586 ((archcap_msr & MSR_IA32_ARCH_CAPABILITIES_TAA_NO) != 0 ||
1587 cpuid_tsx_disabled)) {
1588 return CWA_ON;
1589 }
1590 }
1591 }
1592 break;
1593
1594 case CPU_INTEL_RSBST:
1595 /*
1596 * RSB-stuffing in the kernel exit trampolines (when returning to user)
1597 * RSB depth is 32. This workaround must be explicitly enabled via the
1598 * cwae boot-arg.
1599 */
1600 break;
1601
1602 default:
1603 break;
1604 }
1605
1606 return CWA_OFF;
1607 }
1608
1609 static void
cpuid_do_precpuid_was(void)1610 cpuid_do_precpuid_was(void)
1611 {
1612 /*
1613 * Note that care must be taken not to use any data from the cached cpuid data since it is
1614 * likely uninitialized at this point. That includes calling functions that make use of
1615 * that data as well.
1616 */
1617
1618 /* Note the TSX disablement, we do not support force-on since it depends on MSRs being present */
1619 if (cpuid_wa_required(CPU_INTEL_TSXDA) == CWA_ON) {
1620 /* This must be executed on all logical processors */
1621 wrmsr64(MSR_IA32_TSX_CTRL, MSR_IA32_TSXCTRL_TSX_CPU_CLEAR | MSR_IA32_TSXCTRL_RTM_DISABLE);
1622 cpuid_tsx_disabled = true;
1623 }
1624 }
1625
1626
1627 /*
1628 * Hunt for Apple Paravirtualization support in the hypervisor class leaves [0x4000_0000-0x4001_0000].
1629 * Hypervisor interfaces are expected to be found at 0x100 boundaries for compatibility.
1630 */
1631
1632 static bool
cpuid_vmm_detect_applepv_features(i386_vmm_info_t * info_p,const uint32_t base,const uint32_t max_leaf)1633 cpuid_vmm_detect_applepv_features(i386_vmm_info_t *info_p, const uint32_t base, const uint32_t max_leaf)
1634 {
1635 if ((max_leaf - base) < APPLEPV_LEAF_INDEX_MAX) {
1636 return false;
1637 }
1638
1639 /*
1640 * Issue cpuid to make sure the interface supports "AH#1" features.
1641 * This avoids a possible collision with "Hv#1" used by Hyper-V.
1642 */
1643 uint32_t reg[4];
1644 char interface[5];
1645 cpuid_fn(base + APPLEPV_INTERFACE_LEAF_INDEX, reg);
1646 memcpy(&interface[0], ®[eax], 4);
1647 interface[4] = '\0';
1648 if (0 == strcmp(interface, APPLEPV_INTERFACE)) {
1649 cpuid_fn(base + APPLEPV_FEATURES_LEAF_INDEX, reg);
1650 info_p->cpuid_vmm_applepv_features = quad(reg[ecx], reg[edx]);
1651 return true;
1652 }
1653 return false;
1654 }
1655
1656 static void
cpuid_vmm_detect_pv_interface(i386_vmm_info_t * info_p,const char * signature,bool (* searcher)(i386_vmm_info_t *,const uint32_t,const uint32_t))1657 cpuid_vmm_detect_pv_interface(i386_vmm_info_t *info_p, const char *signature,
1658 bool (*searcher)(i386_vmm_info_t*, const uint32_t, const uint32_t))
1659 {
1660 int hcalls;
1661 if (PE_parse_boot_argn("hcalls", &hcalls, sizeof(hcalls)) &&
1662 hcalls == 0) {
1663 return;
1664 }
1665
1666 assert(info_p);
1667 /*
1668 * Look for PV interface matching signature
1669 */
1670 for (uint32_t base = 0x40000100; base < 0x40010000; base += 0x100) {
1671 uint32_t reg[4];
1672 char vendor[13];
1673
1674 cpuid_fn(base, reg);
1675 memcpy(&vendor[0], ®[ebx], 4);
1676 memcpy(&vendor[4], ®[ecx], 4);
1677 memcpy(&vendor[8], ®[edx], 4);
1678 vendor[12] = '\0';
1679 if ((0 == strcmp(vendor, signature)) &&
1680 (reg[eax] - base) < 0x100 &&
1681 (*searcher)(info_p, base, reg[eax])) {
1682 break;
1683 }
1684 }
1685 }
1686