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26
27 #include <arm64/cpc_arm64.h>
28 #include <kern/assert.h>
29 #include <kern/cpc.h>
30 #include <stdint.h>
31 #include <stdbool.h>
32 #include <stddef.h>
33
34 struct cpc_event {
35 const char *cev_name;
36 uint16_t cev_selector;
37 };
38
39 struct cpc_event_list {
40 unsigned int cel_event_count;
41 struct cpc_event cel_events[];
42 };
43
44 static const struct cpc_event_list _cpc_known_cpmu_events;
45 static const struct cpc_event_list _cpc_known_upmu_events = {
46 .cel_event_count = 0,
47 .cel_events = {},
48 };
49
50 const struct cpc_event_list *_cpc_known_events[CPC_HW_COUNT] = {
51 [CPC_HW_CPMU] = &_cpc_known_cpmu_events,
52 [CPC_HW_UPMU] = &_cpc_known_upmu_events,
53 };
54
55 static const struct cpc_event *
_cpc_select_event(cpc_hw_t hw,uint16_t selector)56 _cpc_select_event(cpc_hw_t hw, uint16_t selector)
57 {
58 assert(hw < CPC_HW_COUNT);
59 const struct cpc_event_list *list = _cpc_known_events[hw];
60 for (unsigned int i = 0; i < list->cel_event_count; i++) {
61 if (list->cel_events[i].cev_selector == selector) {
62 return &list->cel_events[i];
63 }
64 }
65 return NULL;
66 }
67
68 static
69 #if !CPC_INSECURE
70 const
71 #endif // !CPC_INSECURE
72 cpc_event_policy_t _cpc_event_policy = CPC_EVPOL_DEFAULT;
73
74 cpc_event_policy_t
cpc_get_event_policy(void)75 cpc_get_event_policy(void)
76 {
77 return _cpc_event_policy;
78 }
79
80 #if CPC_INSECURE
81
82 void
cpc_set_event_policy(cpc_event_policy_t new_policy)83 cpc_set_event_policy(cpc_event_policy_t new_policy)
84 {
85 _cpc_event_policy = new_policy;
86 }
87
88 #endif // CPC_INSECURE
89
90 bool
cpc_event_allowed(cpc_hw_t hw,uint16_t event_selector)91 cpc_event_allowed(
92 cpc_hw_t hw,
93 uint16_t event_selector)
94 {
95 if (event_selector == 0) {
96 return true;
97 }
98 switch (_cpc_event_policy) {
99 #if CPC_INSECURE
100 case CPC_EVPOL_ALLOW_ALL:
101 return true;
102 #endif // CPC_INSECURE
103 case CPC_EVPOL_DENY_ALL:
104 return false;
105 case CPC_EVPOL_RESTRICT_TO_KNOWN:
106 return _cpc_select_event(hw, event_selector) != NULL;
107 }
108 return false;
109 }
110
111 static const struct cpc_event_list _cpc_known_cpmu_events = {
112 #if ARM64_BOARD_CONFIG_T6000
113 .cel_event_count = 60,
114 .cel_events = {
115 { .cev_selector = 0x0000, .cev_name = "NONE" },
116 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
117 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
118 { .cev_selector = 0x0004, .cev_name = "L1I_TLB_FILL" },
119 { .cev_selector = 0x0005, .cev_name = "L1D_TLB_FILL" },
120 { .cev_selector = 0x0007, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
121 { .cev_selector = 0x0008, .cev_name = "MMU_TABLE_WALK_DATA" },
122 { .cev_selector = 0x000a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
123 { .cev_selector = 0x000b, .cev_name = "L2_TLB_MISS_DATA" },
124 { .cev_selector = 0x000d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
125 { .cev_selector = 0x0052, .cev_name = "SCHEDULE_UOP" },
126 { .cev_selector = 0x006c, .cev_name = "INTERRUPT_PENDING" },
127 { .cev_selector = 0x0070, .cev_name = "MAP_STALL_DISPATCH" },
128 { .cev_selector = 0x0075, .cev_name = "MAP_REWIND" },
129 { .cev_selector = 0x0076, .cev_name = "MAP_STALL" },
130 { .cev_selector = 0x007c, .cev_name = "MAP_INT_UOP" },
131 { .cev_selector = 0x007d, .cev_name = "MAP_LDST_UOP" },
132 { .cev_selector = 0x007e, .cev_name = "MAP_SIMD_UOP" },
133 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
134 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
135 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
136 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
137 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
138 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
139 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
140 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
141 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
142 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
143 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
144 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
145 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
146 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
147 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
148 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
149 { .cev_selector = 0x00a0, .cev_name = "L1D_TLB_ACCESS" },
150 { .cev_selector = 0x00a1, .cev_name = "L1D_TLB_MISS" },
151 { .cev_selector = 0x00a2, .cev_name = "L1D_CACHE_MISS_ST" },
152 { .cev_selector = 0x00a3, .cev_name = "L1D_CACHE_MISS_LD" },
153 { .cev_selector = 0x00a6, .cev_name = "LD_UNIT_UOP" },
154 { .cev_selector = 0x00a7, .cev_name = "ST_UNIT_UOP" },
155 { .cev_selector = 0x00a8, .cev_name = "L1D_CACHE_WRITEBACK" },
156 { .cev_selector = 0x00b1, .cev_name = "LDST_X64_UOP" },
157 { .cev_selector = 0x00b2, .cev_name = "LDST_XPG_UOP" },
158 { .cev_selector = 0x00b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
159 { .cev_selector = 0x00b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
160 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
161 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
162 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
163 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
164 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
165 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
166 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
167 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
168 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
169 { .cev_selector = 0x00d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
170 { .cev_selector = 0x00d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
171 { .cev_selector = 0x00db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
172 { .cev_selector = 0x00de, .cev_name = "FETCH_RESTART" },
173 { .cev_selector = 0x00e5, .cev_name = "ST_NT_UOP" },
174 { .cev_selector = 0x00e6, .cev_name = "LD_NT_UOP" },
175 },
176 #elif ARM64_BOARD_CONFIG_T6020
177 .cel_event_count = 59,
178 .cel_events = {
179 { .cev_selector = 0x0000, .cev_name = "NONE" },
180 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
181 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
182 { .cev_selector = 0x0004, .cev_name = "L1I_TLB_FILL" },
183 { .cev_selector = 0x0005, .cev_name = "L1D_TLB_FILL" },
184 { .cev_selector = 0x0007, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
185 { .cev_selector = 0x0008, .cev_name = "MMU_TABLE_WALK_DATA" },
186 { .cev_selector = 0x000a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
187 { .cev_selector = 0x000b, .cev_name = "L2_TLB_MISS_DATA" },
188 { .cev_selector = 0x000d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
189 { .cev_selector = 0x006c, .cev_name = "INTERRUPT_PENDING" },
190 { .cev_selector = 0x0070, .cev_name = "MAP_STALL_DISPATCH" },
191 { .cev_selector = 0x0075, .cev_name = "MAP_REWIND" },
192 { .cev_selector = 0x0076, .cev_name = "MAP_STALL" },
193 { .cev_selector = 0x007c, .cev_name = "MAP_INT_UOP" },
194 { .cev_selector = 0x007d, .cev_name = "MAP_LDST_UOP" },
195 { .cev_selector = 0x007e, .cev_name = "MAP_SIMD_UOP" },
196 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
197 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
198 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
199 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
200 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
201 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
202 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
203 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
204 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
205 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
206 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
207 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
208 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
209 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
210 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
211 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
212 { .cev_selector = 0x00a0, .cev_name = "L1D_TLB_ACCESS" },
213 { .cev_selector = 0x00a1, .cev_name = "L1D_TLB_MISS" },
214 { .cev_selector = 0x00a2, .cev_name = "L1D_CACHE_MISS_ST" },
215 { .cev_selector = 0x00a3, .cev_name = "L1D_CACHE_MISS_LD" },
216 { .cev_selector = 0x00a6, .cev_name = "LD_UNIT_UOP" },
217 { .cev_selector = 0x00a7, .cev_name = "ST_UNIT_UOP" },
218 { .cev_selector = 0x00a8, .cev_name = "L1D_CACHE_WRITEBACK" },
219 { .cev_selector = 0x00b1, .cev_name = "LDST_X64_UOP" },
220 { .cev_selector = 0x00b2, .cev_name = "LDST_XPG_UOP" },
221 { .cev_selector = 0x00b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
222 { .cev_selector = 0x00b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
223 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
224 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
225 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
226 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
227 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
228 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
229 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
230 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
231 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
232 { .cev_selector = 0x00d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
233 { .cev_selector = 0x00d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
234 { .cev_selector = 0x00db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
235 { .cev_selector = 0x00de, .cev_name = "FETCH_RESTART" },
236 { .cev_selector = 0x00e5, .cev_name = "ST_NT_UOP" },
237 { .cev_selector = 0x00e6, .cev_name = "LD_NT_UOP" },
238 },
239 #elif ARM64_BOARD_CONFIG_T6030
240 .cel_event_count = 60,
241 .cel_events = {
242 { .cev_selector = 0x0000, .cev_name = "NONE" },
243 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
244 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
245 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
246 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
247 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
248 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
249 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
250 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
251 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
252 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
253 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
254 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
255 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
256 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
257 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
258 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
259 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
260 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
261 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
262 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
263 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
264 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
265 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
266 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
267 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
268 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
269 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
270 { .cev_selector = 0x01d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
271 { .cev_selector = 0x01d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
272 { .cev_selector = 0x01db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
273 { .cev_selector = 0x01de, .cev_name = "FETCH_RESTART" },
274 { .cev_selector = 0x0269, .cev_name = "MAP_UOP" },
275 { .cev_selector = 0x026c, .cev_name = "INTERRUPT_PENDING" },
276 { .cev_selector = 0x0270, .cev_name = "MAP_STALL_DISPATCH" },
277 { .cev_selector = 0x0275, .cev_name = "MAP_REWIND" },
278 { .cev_selector = 0x0276, .cev_name = "MAP_STALL" },
279 { .cev_selector = 0x027c, .cev_name = "MAP_INT_UOP" },
280 { .cev_selector = 0x027d, .cev_name = "MAP_LDST_UOP" },
281 { .cev_selector = 0x027e, .cev_name = "MAP_SIMD_UOP" },
282 { .cev_selector = 0x0404, .cev_name = "L1I_TLB_FILL" },
283 { .cev_selector = 0x0405, .cev_name = "L1D_TLB_FILL" },
284 { .cev_selector = 0x0407, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
285 { .cev_selector = 0x0408, .cev_name = "MMU_TABLE_WALK_DATA" },
286 { .cev_selector = 0x040a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
287 { .cev_selector = 0x040b, .cev_name = "L2_TLB_MISS_DATA" },
288 { .cev_selector = 0x040d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
289 { .cev_selector = 0x05a0, .cev_name = "L1D_TLB_ACCESS" },
290 { .cev_selector = 0x05a1, .cev_name = "L1D_TLB_MISS" },
291 { .cev_selector = 0x05a2, .cev_name = "L1D_CACHE_MISS_ST" },
292 { .cev_selector = 0x05a3, .cev_name = "L1D_CACHE_MISS_LD" },
293 { .cev_selector = 0x05a6, .cev_name = "LD_UNIT_UOP" },
294 { .cev_selector = 0x05a7, .cev_name = "ST_UNIT_UOP" },
295 { .cev_selector = 0x05a8, .cev_name = "L1D_CACHE_WRITEBACK" },
296 { .cev_selector = 0x05b1, .cev_name = "LDST_X64_UOP" },
297 { .cev_selector = 0x05b2, .cev_name = "LDST_XPG_UOP" },
298 { .cev_selector = 0x05b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
299 { .cev_selector = 0x05b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
300 { .cev_selector = 0x05e5, .cev_name = "ST_NT_UOP" },
301 { .cev_selector = 0x05e6, .cev_name = "LD_NT_UOP" },
302 },
303 #elif ARM64_BOARD_CONFIG_T6031
304 .cel_event_count = 60,
305 .cel_events = {
306 { .cev_selector = 0x0000, .cev_name = "NONE" },
307 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
308 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
309 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
310 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
311 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
312 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
313 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
314 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
315 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
316 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
317 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
318 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
319 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
320 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
321 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
322 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
323 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
324 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
325 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
326 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
327 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
328 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
329 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
330 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
331 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
332 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
333 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
334 { .cev_selector = 0x01d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
335 { .cev_selector = 0x01d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
336 { .cev_selector = 0x01db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
337 { .cev_selector = 0x01de, .cev_name = "FETCH_RESTART" },
338 { .cev_selector = 0x0269, .cev_name = "MAP_UOP" },
339 { .cev_selector = 0x026c, .cev_name = "INTERRUPT_PENDING" },
340 { .cev_selector = 0x0270, .cev_name = "MAP_STALL_DISPATCH" },
341 { .cev_selector = 0x0275, .cev_name = "MAP_REWIND" },
342 { .cev_selector = 0x0276, .cev_name = "MAP_STALL" },
343 { .cev_selector = 0x027c, .cev_name = "MAP_INT_UOP" },
344 { .cev_selector = 0x027d, .cev_name = "MAP_LDST_UOP" },
345 { .cev_selector = 0x027e, .cev_name = "MAP_SIMD_UOP" },
346 { .cev_selector = 0x0404, .cev_name = "L1I_TLB_FILL" },
347 { .cev_selector = 0x0405, .cev_name = "L1D_TLB_FILL" },
348 { .cev_selector = 0x0407, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
349 { .cev_selector = 0x0408, .cev_name = "MMU_TABLE_WALK_DATA" },
350 { .cev_selector = 0x040a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
351 { .cev_selector = 0x040b, .cev_name = "L2_TLB_MISS_DATA" },
352 { .cev_selector = 0x040d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
353 { .cev_selector = 0x05a0, .cev_name = "L1D_TLB_ACCESS" },
354 { .cev_selector = 0x05a1, .cev_name = "L1D_TLB_MISS" },
355 { .cev_selector = 0x05a2, .cev_name = "L1D_CACHE_MISS_ST" },
356 { .cev_selector = 0x05a3, .cev_name = "L1D_CACHE_MISS_LD" },
357 { .cev_selector = 0x05a6, .cev_name = "LD_UNIT_UOP" },
358 { .cev_selector = 0x05a7, .cev_name = "ST_UNIT_UOP" },
359 { .cev_selector = 0x05a8, .cev_name = "L1D_CACHE_WRITEBACK" },
360 { .cev_selector = 0x05b1, .cev_name = "LDST_X64_UOP" },
361 { .cev_selector = 0x05b2, .cev_name = "LDST_XPG_UOP" },
362 { .cev_selector = 0x05b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
363 { .cev_selector = 0x05b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
364 { .cev_selector = 0x05e5, .cev_name = "ST_NT_UOP" },
365 { .cev_selector = 0x05e6, .cev_name = "LD_NT_UOP" },
366 },
367 #elif ARM64_BOARD_CONFIG_T8101
368 .cel_event_count = 60,
369 .cel_events = {
370 { .cev_selector = 0x0000, .cev_name = "NONE" },
371 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
372 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
373 { .cev_selector = 0x0004, .cev_name = "L1I_TLB_FILL" },
374 { .cev_selector = 0x0005, .cev_name = "L1D_TLB_FILL" },
375 { .cev_selector = 0x0007, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
376 { .cev_selector = 0x0008, .cev_name = "MMU_TABLE_WALK_DATA" },
377 { .cev_selector = 0x000a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
378 { .cev_selector = 0x000b, .cev_name = "L2_TLB_MISS_DATA" },
379 { .cev_selector = 0x000d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
380 { .cev_selector = 0x0052, .cev_name = "SCHEDULE_UOP" },
381 { .cev_selector = 0x006c, .cev_name = "INTERRUPT_PENDING" },
382 { .cev_selector = 0x0070, .cev_name = "MAP_STALL_DISPATCH" },
383 { .cev_selector = 0x0075, .cev_name = "MAP_REWIND" },
384 { .cev_selector = 0x0076, .cev_name = "MAP_STALL" },
385 { .cev_selector = 0x007c, .cev_name = "MAP_INT_UOP" },
386 { .cev_selector = 0x007d, .cev_name = "MAP_LDST_UOP" },
387 { .cev_selector = 0x007e, .cev_name = "MAP_SIMD_UOP" },
388 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
389 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
390 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
391 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
392 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
393 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
394 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
395 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
396 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
397 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
398 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
399 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
400 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
401 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
402 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
403 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
404 { .cev_selector = 0x00a0, .cev_name = "L1D_TLB_ACCESS" },
405 { .cev_selector = 0x00a1, .cev_name = "L1D_TLB_MISS" },
406 { .cev_selector = 0x00a2, .cev_name = "L1D_CACHE_MISS_ST" },
407 { .cev_selector = 0x00a3, .cev_name = "L1D_CACHE_MISS_LD" },
408 { .cev_selector = 0x00a6, .cev_name = "LD_UNIT_UOP" },
409 { .cev_selector = 0x00a7, .cev_name = "ST_UNIT_UOP" },
410 { .cev_selector = 0x00a8, .cev_name = "L1D_CACHE_WRITEBACK" },
411 { .cev_selector = 0x00b1, .cev_name = "LDST_X64_UOP" },
412 { .cev_selector = 0x00b2, .cev_name = "LDST_XPG_UOP" },
413 { .cev_selector = 0x00b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
414 { .cev_selector = 0x00b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
415 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
416 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
417 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
418 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
419 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
420 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
421 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
422 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
423 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
424 { .cev_selector = 0x00d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
425 { .cev_selector = 0x00d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
426 { .cev_selector = 0x00db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
427 { .cev_selector = 0x00de, .cev_name = "FETCH_RESTART" },
428 { .cev_selector = 0x00e5, .cev_name = "ST_NT_UOP" },
429 { .cev_selector = 0x00e6, .cev_name = "LD_NT_UOP" },
430 },
431 #elif ARM64_BOARD_CONFIG_T8103
432 .cel_event_count = 60,
433 .cel_events = {
434 { .cev_selector = 0x0000, .cev_name = "NONE" },
435 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
436 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
437 { .cev_selector = 0x0004, .cev_name = "L1I_TLB_FILL" },
438 { .cev_selector = 0x0005, .cev_name = "L1D_TLB_FILL" },
439 { .cev_selector = 0x0007, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
440 { .cev_selector = 0x0008, .cev_name = "MMU_TABLE_WALK_DATA" },
441 { .cev_selector = 0x000a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
442 { .cev_selector = 0x000b, .cev_name = "L2_TLB_MISS_DATA" },
443 { .cev_selector = 0x000d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
444 { .cev_selector = 0x0052, .cev_name = "SCHEDULE_UOP" },
445 { .cev_selector = 0x006c, .cev_name = "INTERRUPT_PENDING" },
446 { .cev_selector = 0x0070, .cev_name = "MAP_STALL_DISPATCH" },
447 { .cev_selector = 0x0075, .cev_name = "MAP_REWIND" },
448 { .cev_selector = 0x0076, .cev_name = "MAP_STALL" },
449 { .cev_selector = 0x007c, .cev_name = "MAP_INT_UOP" },
450 { .cev_selector = 0x007d, .cev_name = "MAP_LDST_UOP" },
451 { .cev_selector = 0x007e, .cev_name = "MAP_SIMD_UOP" },
452 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
453 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
454 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
455 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
456 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
457 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
458 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
459 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
460 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
461 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
462 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
463 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
464 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
465 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
466 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
467 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
468 { .cev_selector = 0x00a0, .cev_name = "L1D_TLB_ACCESS" },
469 { .cev_selector = 0x00a1, .cev_name = "L1D_TLB_MISS" },
470 { .cev_selector = 0x00a2, .cev_name = "L1D_CACHE_MISS_ST" },
471 { .cev_selector = 0x00a3, .cev_name = "L1D_CACHE_MISS_LD" },
472 { .cev_selector = 0x00a6, .cev_name = "LD_UNIT_UOP" },
473 { .cev_selector = 0x00a7, .cev_name = "ST_UNIT_UOP" },
474 { .cev_selector = 0x00a8, .cev_name = "L1D_CACHE_WRITEBACK" },
475 { .cev_selector = 0x00b1, .cev_name = "LDST_X64_UOP" },
476 { .cev_selector = 0x00b2, .cev_name = "LDST_XPG_UOP" },
477 { .cev_selector = 0x00b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
478 { .cev_selector = 0x00b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
479 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
480 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
481 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
482 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
483 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
484 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
485 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
486 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
487 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
488 { .cev_selector = 0x00d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
489 { .cev_selector = 0x00d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
490 { .cev_selector = 0x00db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
491 { .cev_selector = 0x00de, .cev_name = "FETCH_RESTART" },
492 { .cev_selector = 0x00e5, .cev_name = "ST_NT_UOP" },
493 { .cev_selector = 0x00e6, .cev_name = "LD_NT_UOP" },
494 },
495 #elif ARM64_BOARD_CONFIG_T8112
496 .cel_event_count = 59,
497 .cel_events = {
498 { .cev_selector = 0x0000, .cev_name = "NONE" },
499 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
500 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
501 { .cev_selector = 0x0004, .cev_name = "L1I_TLB_FILL" },
502 { .cev_selector = 0x0005, .cev_name = "L1D_TLB_FILL" },
503 { .cev_selector = 0x0007, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
504 { .cev_selector = 0x0008, .cev_name = "MMU_TABLE_WALK_DATA" },
505 { .cev_selector = 0x000a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
506 { .cev_selector = 0x000b, .cev_name = "L2_TLB_MISS_DATA" },
507 { .cev_selector = 0x000d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
508 { .cev_selector = 0x006c, .cev_name = "INTERRUPT_PENDING" },
509 { .cev_selector = 0x0070, .cev_name = "MAP_STALL_DISPATCH" },
510 { .cev_selector = 0x0075, .cev_name = "MAP_REWIND" },
511 { .cev_selector = 0x0076, .cev_name = "MAP_STALL" },
512 { .cev_selector = 0x007c, .cev_name = "MAP_INT_UOP" },
513 { .cev_selector = 0x007d, .cev_name = "MAP_LDST_UOP" },
514 { .cev_selector = 0x007e, .cev_name = "MAP_SIMD_UOP" },
515 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
516 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
517 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
518 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
519 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
520 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
521 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
522 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
523 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
524 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
525 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
526 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
527 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
528 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
529 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
530 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
531 { .cev_selector = 0x00a0, .cev_name = "L1D_TLB_ACCESS" },
532 { .cev_selector = 0x00a1, .cev_name = "L1D_TLB_MISS" },
533 { .cev_selector = 0x00a2, .cev_name = "L1D_CACHE_MISS_ST" },
534 { .cev_selector = 0x00a3, .cev_name = "L1D_CACHE_MISS_LD" },
535 { .cev_selector = 0x00a6, .cev_name = "LD_UNIT_UOP" },
536 { .cev_selector = 0x00a7, .cev_name = "ST_UNIT_UOP" },
537 { .cev_selector = 0x00a8, .cev_name = "L1D_CACHE_WRITEBACK" },
538 { .cev_selector = 0x00b1, .cev_name = "LDST_X64_UOP" },
539 { .cev_selector = 0x00b2, .cev_name = "LDST_XPG_UOP" },
540 { .cev_selector = 0x00b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
541 { .cev_selector = 0x00b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
542 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
543 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
544 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
545 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
546 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
547 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
548 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
549 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
550 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
551 { .cev_selector = 0x00d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
552 { .cev_selector = 0x00d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
553 { .cev_selector = 0x00db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
554 { .cev_selector = 0x00de, .cev_name = "FETCH_RESTART" },
555 { .cev_selector = 0x00e5, .cev_name = "ST_NT_UOP" },
556 { .cev_selector = 0x00e6, .cev_name = "LD_NT_UOP" },
557 },
558 #elif ARM64_BOARD_CONFIG_T8122_T8130
559 .cel_event_count = 60,
560 .cel_events = {
561 { .cev_selector = 0x0000, .cev_name = "NONE" },
562 { .cev_selector = 0x0001, .cev_name = "RETIRE_UOP" },
563 { .cev_selector = 0x0002, .cev_name = "CORE_ACTIVE_CYCLE" },
564 { .cev_selector = 0x0084, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
565 { .cev_selector = 0x008c, .cev_name = "INST_ALL" },
566 { .cev_selector = 0x008d, .cev_name = "INST_BRANCH" },
567 { .cev_selector = 0x008e, .cev_name = "INST_BRANCH_CALL" },
568 { .cev_selector = 0x008f, .cev_name = "INST_BRANCH_RET" },
569 { .cev_selector = 0x0090, .cev_name = "INST_BRANCH_TAKEN" },
570 { .cev_selector = 0x0093, .cev_name = "INST_BRANCH_INDIR" },
571 { .cev_selector = 0x0094, .cev_name = "INST_BRANCH_COND" },
572 { .cev_selector = 0x0095, .cev_name = "INST_INT_LD" },
573 { .cev_selector = 0x0096, .cev_name = "INST_INT_ST" },
574 { .cev_selector = 0x0097, .cev_name = "INST_INT_ALU" },
575 { .cev_selector = 0x0098, .cev_name = "INST_SIMD_LD" },
576 { .cev_selector = 0x0099, .cev_name = "INST_SIMD_ST" },
577 { .cev_selector = 0x009a, .cev_name = "INST_SIMD_ALU" },
578 { .cev_selector = 0x009b, .cev_name = "INST_LDST" },
579 { .cev_selector = 0x009c, .cev_name = "INST_BARRIER" },
580 { .cev_selector = 0x00bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
581 { .cev_selector = 0x00c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
582 { .cev_selector = 0x00c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
583 { .cev_selector = 0x00c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
584 { .cev_selector = 0x00c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
585 { .cev_selector = 0x00c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
586 { .cev_selector = 0x00c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
587 { .cev_selector = 0x00ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
588 { .cev_selector = 0x00cb, .cev_name = "BRANCH_MISPRED_NONSPEC" },
589 { .cev_selector = 0x01d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
590 { .cev_selector = 0x01d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
591 { .cev_selector = 0x01db, .cev_name = "L1I_CACHE_MISS_DEMAND" },
592 { .cev_selector = 0x01de, .cev_name = "FETCH_RESTART" },
593 { .cev_selector = 0x0269, .cev_name = "MAP_UOP" },
594 { .cev_selector = 0x026c, .cev_name = "INTERRUPT_PENDING" },
595 { .cev_selector = 0x0270, .cev_name = "MAP_STALL_DISPATCH" },
596 { .cev_selector = 0x0275, .cev_name = "MAP_REWIND" },
597 { .cev_selector = 0x0276, .cev_name = "MAP_STALL" },
598 { .cev_selector = 0x027c, .cev_name = "MAP_INT_UOP" },
599 { .cev_selector = 0x027d, .cev_name = "MAP_LDST_UOP" },
600 { .cev_selector = 0x027e, .cev_name = "MAP_SIMD_UOP" },
601 { .cev_selector = 0x0404, .cev_name = "L1I_TLB_FILL" },
602 { .cev_selector = 0x0405, .cev_name = "L1D_TLB_FILL" },
603 { .cev_selector = 0x0407, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
604 { .cev_selector = 0x0408, .cev_name = "MMU_TABLE_WALK_DATA" },
605 { .cev_selector = 0x040a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
606 { .cev_selector = 0x040b, .cev_name = "L2_TLB_MISS_DATA" },
607 { .cev_selector = 0x040d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
608 { .cev_selector = 0x05a0, .cev_name = "L1D_TLB_ACCESS" },
609 { .cev_selector = 0x05a1, .cev_name = "L1D_TLB_MISS" },
610 { .cev_selector = 0x05a2, .cev_name = "L1D_CACHE_MISS_ST" },
611 { .cev_selector = 0x05a3, .cev_name = "L1D_CACHE_MISS_LD" },
612 { .cev_selector = 0x05a6, .cev_name = "LD_UNIT_UOP" },
613 { .cev_selector = 0x05a7, .cev_name = "ST_UNIT_UOP" },
614 { .cev_selector = 0x05a8, .cev_name = "L1D_CACHE_WRITEBACK" },
615 { .cev_selector = 0x05b1, .cev_name = "LDST_X64_UOP" },
616 { .cev_selector = 0x05b2, .cev_name = "LDST_XPG_UOP" },
617 { .cev_selector = 0x05b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
618 { .cev_selector = 0x05b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
619 { .cev_selector = 0x05e5, .cev_name = "ST_NT_UOP" },
620 { .cev_selector = 0x05e6, .cev_name = "LD_NT_UOP" },
621 },
622 #elif ARM64_BOARD_CONFIG_T8132
623 .cel_event_count = 62,
624 .cel_events = {
625 { .cev_selector = 0x0000, .cev_name = "NONE" },
626 { .cev_selector = 0x0008, .cev_name = "INST_ALL" },
627 { .cev_selector = 0x0011, .cev_name = "CORE_ACTIVE_CYCLE" },
628 { .cev_selector = 0x0021, .cev_name = "INST_BRANCH" },
629 { .cev_selector = 0x0022, .cev_name = "BRANCH_MISPRED_NONSPEC" },
630 { .cev_selector = 0x003a, .cev_name = "RETIRE_UOP" },
631 { .cev_selector = 0x003b, .cev_name = "MAP_UOP" },
632 { .cev_selector = 0x0182, .cev_name = "MAP_DISPATCH_BUBBLE_IC" },
633 { .cev_selector = 0x0183, .cev_name = "MAP_DISPATCH_BUBBLE_ITLB" },
634 { .cev_selector = 0x01d4, .cev_name = "L1I_TLB_MISS_DEMAND" },
635 { .cev_selector = 0x01d6, .cev_name = "MAP_DISPATCH_BUBBLE" },
636 { .cev_selector = 0x01de, .cev_name = "FETCH_RESTART" },
637 { .cev_selector = 0x026c, .cev_name = "INTERRUPT_PENDING" },
638 { .cev_selector = 0x0270, .cev_name = "MAP_STALL_DISPATCH" },
639 { .cev_selector = 0x0275, .cev_name = "MAP_REWIND" },
640 { .cev_selector = 0x0276, .cev_name = "MAP_STALL" },
641 { .cev_selector = 0x027c, .cev_name = "MAP_INT_UOP" },
642 { .cev_selector = 0x027d, .cev_name = "MAP_LDST_UOP" },
643 { .cev_selector = 0x027e, .cev_name = "MAP_SIMD_UOP" },
644 { .cev_selector = 0x0404, .cev_name = "L1I_TLB_FILL" },
645 { .cev_selector = 0x0405, .cev_name = "L1D_TLB_FILL" },
646 { .cev_selector = 0x0407, .cev_name = "MMU_TABLE_WALK_INSTRUCTION" },
647 { .cev_selector = 0x0408, .cev_name = "MMU_TABLE_WALK_DATA" },
648 { .cev_selector = 0x040a, .cev_name = "L2_TLB_MISS_INSTRUCTION" },
649 { .cev_selector = 0x040b, .cev_name = "L2_TLB_MISS_DATA" },
650 { .cev_selector = 0x040d, .cev_name = "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" },
651 { .cev_selector = 0x05a0, .cev_name = "L1D_TLB_ACCESS" },
652 { .cev_selector = 0x05a1, .cev_name = "L1D_TLB_MISS" },
653 { .cev_selector = 0x05a2, .cev_name = "L1D_CACHE_MISS_ST" },
654 { .cev_selector = 0x05a3, .cev_name = "L1D_CACHE_MISS_LD" },
655 { .cev_selector = 0x05a6, .cev_name = "LD_UNIT_UOP" },
656 { .cev_selector = 0x05a7, .cev_name = "ST_UNIT_UOP" },
657 { .cev_selector = 0x05a8, .cev_name = "L1D_CACHE_WRITEBACK" },
658 { .cev_selector = 0x05b1, .cev_name = "LDST_X64_UOP" },
659 { .cev_selector = 0x05b2, .cev_name = "LDST_XPG_UOP" },
660 { .cev_selector = 0x05b3, .cev_name = "ATOMIC_OR_EXCLUSIVE_SUCC" },
661 { .cev_selector = 0x05b4, .cev_name = "ATOMIC_OR_EXCLUSIVE_FAIL" },
662 { .cev_selector = 0x05e5, .cev_name = "ST_NT_UOP" },
663 { .cev_selector = 0x05e6, .cev_name = "LD_NT_UOP" },
664 { .cev_selector = 0x0884, .cev_name = "FLUSH_RESTART_OTHER_NONSPEC" },
665 { .cev_selector = 0x088e, .cev_name = "INST_BRANCH_CALL" },
666 { .cev_selector = 0x088f, .cev_name = "INST_BRANCH_RET" },
667 { .cev_selector = 0x0890, .cev_name = "INST_BRANCH_TAKEN" },
668 { .cev_selector = 0x0893, .cev_name = "INST_BRANCH_INDIR" },
669 { .cev_selector = 0x0894, .cev_name = "INST_BRANCH_COND" },
670 { .cev_selector = 0x0895, .cev_name = "INST_INT_LD" },
671 { .cev_selector = 0x0896, .cev_name = "INST_INT_ST" },
672 { .cev_selector = 0x0897, .cev_name = "INST_INT_ALU" },
673 { .cev_selector = 0x0898, .cev_name = "INST_SIMD_LD" },
674 { .cev_selector = 0x0899, .cev_name = "INST_SIMD_ST" },
675 { .cev_selector = 0x089a, .cev_name = "INST_SIMD_ALU" },
676 { .cev_selector = 0x089b, .cev_name = "INST_LDST" },
677 { .cev_selector = 0x089c, .cev_name = "INST_BARRIER" },
678 { .cev_selector = 0x08bf, .cev_name = "L1D_CACHE_MISS_LD_NONSPEC" },
679 { .cev_selector = 0x08c0, .cev_name = "L1D_CACHE_MISS_ST_NONSPEC" },
680 { .cev_selector = 0x08c1, .cev_name = "L1D_TLB_MISS_NONSPEC" },
681 { .cev_selector = 0x08c4, .cev_name = "ST_MEMORY_ORDER_VIOLATION_NONSPEC" },
682 { .cev_selector = 0x08c5, .cev_name = "BRANCH_COND_MISPRED_NONSPEC" },
683 { .cev_selector = 0x08c6, .cev_name = "BRANCH_INDIR_MISPRED_NONSPEC" },
684 { .cev_selector = 0x08c8, .cev_name = "BRANCH_RET_INDIR_MISPRED_NONSPEC" },
685 { .cev_selector = 0x08ca, .cev_name = "BRANCH_CALL_INDIR_MISPRED_NONSPEC" },
686 { .cev_selector = 0x4006, .cev_name = "L1I_CACHE_MISS_DEMAND" },
687 },
688 #else
689 .cel_event_count = 0,
690 .cel_events = {},
691 #endif
692 };
693